JP2009252004A - Cache system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cache system that performs efficient processing and reduces power consumption. <P>SOLUTION: The cache system has an instruction cache data RAM 10 serving as a cache data storage part configured to store cache data to a plurality of ways of each index entry, and a way validity bit control part 16 serving as a way information control part for controlling way information indicating whether each way of each index entry corresponds to a valid way capable of storing inconsecutively addressed cache data for other cache data to be stored in the cache data storage part or an invalid way restricting the storage of inconsecutively addressed cache data for other cache data. The cache data storage part is configured to integrate an invalid way with a valid way of the same or different index entry as or from the invalid way. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a cache system, and more particularly to a cache system mounted on a processor.

  Conventionally, in order to eliminate the bottleneck of memory access, microprocessors are mainly equipped with a cache memory on a chip. As a configuration of the cache memory, a set associative method using a plurality of ways is often used. As a technique for improving the hit rate in a set associative cache system, for example, Patent Document 1 proposes a technique for temporarily increasing the number of ways.

  Conventionally, a cache memory is used with a fixed line size once it is mounted. Reading tag information from the cache tag memory is performed for each cache line regardless of the mode of cache access from the processor core. For this reason, even when accessing consecutive addresses, use of the cache tag memory is required every time the boundary of the cache line is crossed, resulting in useless power consumption. Further, when the line size is small with respect to continuous address data, the number of transfers to the main memory during refilling is increased. On the other hand, the number of lines decreases as the line size is increased in a cache memory having a fixed cache capacity. As the number of lines decreases, cache misses in the case of accessing discontinuous addresses will increase. Furthermore, in the case of the technique of Patent Document 1, it is necessary to newly install an auxiliary cache for temporarily increasing the number of ways. As described above, according to the conventional technique, it is difficult to enable efficient processing and to reduce power consumption.

JP-A-6-231044

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a cache system that enables efficient processing and can reduce power consumption.

  According to one aspect of the present invention, a cache data storage unit configured to store cache data in a plurality of ways for each index, and addresses are discontinuous with respect to other cache data stored in the cache data storage unit An index indicating which of the valid way, which is a way that can store cache data, and the invalid way, which is a way that limits the storage of cache data whose address is discontinuous with respect to other cache data A way information control unit that controls way information representing each way, and the cache data storage unit is configured to be able to integrate invalid ways into valid ways with the same or different index as invalid ways. A featured cache system is provided.

  According to the present invention, it is possible to perform efficient processing and reduce power consumption.

  Exemplary embodiments of a cache system according to the present invention will be explained below in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the cache system according to the first embodiment of the present invention. The cache system according to the present embodiment is an instruction cache system including an instruction cache memory, and inherently employs a 2-way set associative method including way 0 and way 1. The instruction cache memory stores a program that is a group of instructions to the processor.

  The cache system according to the present embodiment includes various cache systems including a data cache memory other than the instruction cache memory, and a higher order than the 2-way, based on the following explanation summary by an engineer in the field to which the present invention belongs. It can be transformed into a set associative cache system. Accordingly, the following description should be broadly understood as the contents disclosed for the relevant field, and is not intended to limit the present invention.

  The cache system according to the present embodiment includes an instruction cache data RAM (Random Access Memory) 10, a cache tag RAM 11, an instruction cache control unit 12, a tag comparison circuit 13, and an instruction fetch unit 15. The instruction cache data RAM 10 functions as a cache data storage unit that stores cache data. The cache tag RAM 11 functions as a cache tag storage unit that stores cache tag information. The instruction cache control unit 12 controls the entire cache system.

  The tag comparison circuit 13 compares the tag information of the address accessed by the processor with the tag information read from the cache tag RAM 11 and outputs the comparison result to the instruction cache control unit 12. The instruction fetch unit 15 fetches an instruction code. A way valid (WV) bit control unit 16 is included in the instruction cache control unit 12. The way-valid bit control unit 16 controls the way-valid bit via the way-valid bit control line 17.

  FIG. 2 explains the structure of the instruction cache data RAM 10. The instruction cache data RAM 10 has an array structure in which a plurality of lines are arranged in parallel. Each line is assigned an index (Index 0 to Index x) indicating the number of lines. Each line stores a maximum of two cache data according to the number of ways. The instruction cache data RAM 10 is configured to store cache data in way 0 and way 1 for each index.

  FIG. 3 is a diagram for explaining the structure of the cache tag RAM 11 and the valid bits. Similarly to the instruction cache data RAM 10, the cache tag RAM 11 has an array structure. The cache tag RAM 11 is configured to be able to store cache tag information in two ways for each index.

  For example, the valid bit WV is mounted in the cache tag RAM 11 as a bit on a memory. The way valid bit WV is way information that indicates which of the valid way and the invalid way corresponds to each way for each index. The effective way is a way capable of storing cache data whose addresses are discontinuous with respect to other cache data stored in the instruction cache data RAM 10. The invalid way is a way in which storage of cache data whose addresses are discontinuous with respect to other cache data stored in the instruction cache data RAM 10 is restricted. The invalid way stores only cache data at addresses that are continuous with other cache data stored in the instruction cache data RAM 10.

  The way valid bit WV is set for each index and has a bit width corresponding to the original number of ways. In this embodiment, the valid bit WV has a 2-bit configuration. For example, when the way valid bit WV is assigned to the way 0 as the upper 1 bit and the way 1 as the lower 1 bit among the 2 bits, the invalid way is represented by “0”, and the valid way is represented by “1”. To do. The way bit WV is not limited to being mounted in the cache tag RAM 11, and may be mounted at any position. The waived bit WV may be mounted in the instruction cache control unit 12 as a register, for example.

  Further, the cache tag RAM 11 stores a replace bit R that indicates a way to be refilled next, and a valid bit V that indicates whether the stored data is valid as tag information. The replace bit R is set for each index and adopts a 1-bit configuration. For example, the replace bit R represents “0” when the next refill is way 0 and “1” when the next refill is way 1. The replacement bit R is set according to, for example, an LRU (Least Recently Used) method in which data that has not been accessed for a long time is preferentially refilled. The valid bit V is set for each way of each index and takes a 1-bit configuration. The valid bit V represents, for example, “0” when the stored data is invalid as tag information and “1” when it is valid as tag information.

  The address of the instruction requested from the processor is supplied to the instruction cache control unit 12 via the instruction fetch unit 15. The request from the processor includes a sequential request and a branch request. A sequential request is an access to consecutive addresses. A branch request is an access to a discontinuous address. The instruction cache data RAM 10 reads data designated by the index part of the address from the instruction cache control unit 12. The cache tag RAM 11 reads the tag information specified by the index part of the address from the instruction cache control unit 12. The tag comparison circuit 13 compares the read tag information with the tag information of the requested address, and outputs the comparison result to the instruction cache control unit 12.

  When any tag information read from the cache tag RAM 11 matches the tag information of the requested address, the instruction cache control unit 12 selects the hit cache data. The cache data selected by the instruction cache control unit 12 is output to the instruction fetch unit 15. If any tag information read from the cache tag RAM 11 does not match the tag information of the requested address (cache miss), the refill is performed for the way designated by the replace bit R. In this way, the cache system outputs the instruction code requested from the processor.

  4 and 5 describe way integration in the cache system according to the present embodiment. For example, as shown above the white arrow in FIG. 4, it is assumed that the valid bits WV are “11” for all indexes. The way valid bit WV “11” indicates that both way 0 and way 1 are valid ways.

  For the way valid bit WV “11”, as shown above the white arrow in FIG. 5, for example, for the index 0 of the instruction cache data RAM 10, the cache data of the line A (Line A) in the way 0, the way 1 Assume that the cache data of line J (Line J) is stored in. Here, it is assumed that the line J is data whose addresses are discontinuous with respect to the line A. In the index 0 of the cache tag RAM 11, the tag information of the line A is stored in the way 0 and the tag information of the line J is stored in the way 1. The valid bit V of index 0 is “1” for both way 0 and way 1, and the data stored in the cache tag RAM 11 indicates that both way 0 and way 1 are valid tag information. The replace bit R “1” of index 0 indicates that the line J stored in the way 1 is refilled first.

  The valid bit V of index 1, index x-1, and index x is "0" for both way 0 and way 1, and the data stored in the cache tag RAM 11 is invalid as tag information for both way 0 and way 1. Represents something. The tag information of the index 1, index x-1, and index x in the cache tag RAM 11 is "don't care" (indicated as "-" in the figure) for both way 0 and way 1.

  Since the tag information is invalid, the replace bit R and the cache data of the instruction cache data RAM 10 are also set to “don't care” for the index 1, the index x−1, and the index x. In the index 2, since the way valid bit WV is “11”, both the way 0 and the way 1 are valid. The way 0 stores a line T (Line T), and the way 1 stores a line L (Line L). The line L is data having discontinuous addresses with respect to the line T. The replace bit R “1” of the index 2 indicates that the line L stored in the way 1 is refilled first.

  Next, as shown below the white arrow in FIG. 4, it is assumed that the weighted bit WV for index 0 is “10”. The way valid bit WV “10” indicates that the way 0 is a valid way and the way 1 is an invalid way. For the way valid bit WV “10”, as shown below the white arrow in FIG. 5, the index 0 of the instruction cache data RAM 10 has the cache data of line A in way 0 and the line B (Line) in way 1. B) cache data is stored. It is assumed that the line B is data of continuous addresses with respect to the line A.

  In the way 1, which is an invalid way, storage of cache data with discontinuous addresses for the line A stored in the immediately preceding way 0 is restricted, and only the cache data of the line B of addresses that are continuous with the line A is stored. Is stored. The way 1 that is set as the invalid way is integrated into the way 0 that is the valid way of the same index 0. The line with index 0 is handled in the same way as a direct-mapped cache line by integrating way 0 and way 1.

  In the index 0 of the cache tag RAM 11, the tag information of the line A is stored in the original way 0. The cache data stored in the original way 1 is uniquely determined as the cache data of the line B of the continuous address with respect to the line A. Therefore, it is not necessary to store the tag information of the line B in the original way 1, and the tag information of the way 1 is “don't care” (indicated as “−” in the figure). The valid bit V of way 0 is “1”, and way 0 represents that valid cache data is stored. If it is determined whether the way 0 is valid or not, it is not necessary to determine whether the way 1 is valid. Therefore, the valid bit V of the way 1 is set to “don't care”. Since index 0 is treated as one cache line, the replace bit R is also set to “don't care”.

  The line with index 0 is used as a cache line having a line size twice that of the original set associative method by integrating way 0 and way 1. In response to the sequential request, the cache data of the lines A and B is output without the need to read and compare the tag information about the line B and select the cache data due to the hit of the line A.

  Further, the integrated way is divided into the original way 0 and way 1 by setting the way valid bit WV to “11”, and is reconfigured into the original set associative cache line. The instruction cache data RAM 10 and the cache tag RAM 11 dynamically change the number of ways to 1 or 2 for each index according to the way valid bit WV.

  The cache system according to the present embodiment dynamically expands the line size of cache lines that can be stored by integrating invalid ways with valid ways. By appropriately expanding the line size by way integration, access to the cache tag RAM 11 required every time the boundary of the cache line is exceeded is reduced for sequential requests to access consecutive addresses. By reducing access to the cache tag RAM 11, power consumption is reduced. In addition, a large amount of data can be refilled by one burst transfer, and the efficiency of refilling is improved. Cache misses can be suppressed by dynamically changing the number of ways according to the way valid bits WV. As a result, it is possible to perform efficient processing and reduce power consumption.

  In the case of a set associative system higher than 2 ways, the ways are dynamically integrated in the same manner as described above. The cache system according to the present invention is capable of integration from m ways to n ways (n is a positive integer satisfying m> n) for an m way (m is an integer of 2 or more) set associative method. .

  Next, a method for updating the valid bit WV will be described. In the first method, the valid bit WV is updated based on the number of sequential requests and branch requests. In the second method, the valid bit WV is updated based on the definition by the address decoder. In the third method, the way valid bit WV is updated according to the way information update instruction signal.

  FIG. 6 illustrates a configuration for updating the valid bit WV by the first method. The access counter 21 provided in the instruction cache control unit 12 counts the number of sequential requests and the number of branch requests. The count processing unit 22 obtains the ratio of the number of branch requests to the total number of sequential requests and branch requests counted by the access counter 21 in a certain time. The instruction cache control unit 12 holds a threshold value of the branch request ratio as a register value. The way bit control unit 16 determines that the instruction code pattern has a small number of branch requests when the ratio of branch requests is smaller than the threshold, and the instruction code with many branch requests when the ratio of branch requests is equal to or greater than the threshold. Judge as a pattern. The threshold value can be arbitrarily set according to the original line size of the cache memory, for example, and is set by the user, for example.

  Since the sequential request is an access to consecutive addresses, when an instruction is fetched to the end of a certain cache line, an access to the next cache line occurs. On the other hand, since the branch request is access to data with discontinuous addresses, a cache line to be accessed next to a certain cache line is not determined. Since the probability of a cache miss increases as the number of branch requests increases, it is desirable to keep the number of ways high for many branch requests. On the other hand, as the number of sequential requests increases, the access pattern becomes deterministic. Therefore, it is desirable to expand the line size by reducing the number of ways.

  In the first method, when the ratio of the branch request obtained by the count processing unit 22 is smaller than the threshold, the way valid bit control unit 16 sets the way valid bit WV that makes the number of ways low. On the other hand, when the ratio of the branch request obtained by the count processing unit 22 is equal to or greater than the threshold, the way-valid bit control unit 16 sets the way-valid bit WV having a higher number of ways. The way valid bit control unit 16 updates the way valid bit WV based on the number of sequential requests and the number of branch requests counted by the access counter 21. The cache system dynamically switches the number of ways by updating the way valid bit WV. This makes it possible to improve refill efficiency and reduce power consumption for many sequential requests, reduce cache misses for many branch requests, and enable efficient processing.

  The valid bit control unit 16 may update the valid bit WV based on the ratio of sequential requests. The valid bit control unit 16 may determine the instruction code pattern based only on the frequency of one of the branch request and the sequential request. The way valid bit control unit 16 may update the way valid bit WV based on at least one of the number of sequential requests and the number of branch requests counted by the access counter 21. The access counter 21 only needs to count at least one of the sequential request and the branch request.

  FIG. 7 illustrates a configuration for updating the valid bit WV by the second method. The address decoder 23 decodes the accessed address. The address decoder 23 is provided in the instruction cache control unit 12. The address decoder 23 may be provided in the instruction fetch unit 15 in addition to the instruction cache control unit 12, for example. It is assumed that the address decoder 23 can dynamically define the memory space.

  FIG. 8 shows an example of a memory map defined by the address decoder 23. Here, a case will be described as an example where a certain index line is handled in the same way as a direct-mapped cache line by integrating ways from the original 2-way set associative method. The address space for memory access is, in order of address, non-cache area (Un Cache), local memory area (Local Memory), reserved area (Reserved), 2-way set associative cache area (Cache (2-way)) Each memory space of the cache area for direct map (Cache (Direct)) is defined. The type and size of each area are stored in storage logic (register or small memory) in the address decoder 23. Note that the non-cache area, the local memory area, and the reserved area are not related to the switching of the valid bit WV by the second method, and thus detailed description thereof is omitted.

  In response to a cache access to the direct map cache area defined by the address decoder 23, the valid bit control unit 16 sets a valid bit WV as a cache line of the direct map. In response to a cache access to the 2-way set associative cache area defined by the address decoder 23, the way-valid bit control unit 16 sets the way-valid bit WV as a 2-way cache line. As described above, the valid bit control unit 16 updates the valid bit WV based on the definition of the address decoder 23.

  Furthermore, the address decoder 23 freely changes the address position and range of each area. For example, the address decoder 23 can move the boundary between the direct map cache area and the two-way set associative cache area, as indicated by hatched double arrows. In addition, as indicated by a white double arrow, the address decoder 23 can replace the direct map cache area and the 2-way set associative cache area. Thus, the address decoder 23 can dynamically define each area.

  The 2-way set associative cache area is suitable for a memory space in which program code that requires many conditional branches is provided, for example. The direct map cache area is suitable for, for example, a memory space in which program code that is expected to be sequentially executed so as to repeat execution of operations is provided. According to the second method, efficient processing according to the program code can be performed by properly using the cache area by the user.

  FIG. 9 illustrates a configuration for updating the valid bit WV by the third method. In this method, the way-valid bit WV is updated based on the way-valid bit update instruction signal that instructs to update the way-valid bit WV. The way valid bit update instruction signal is a way information update instruction signal instructing to update way information. The way-valid bit update instruction signal is input from the instruction fetch unit 15 to the way-valid bit control unit 16 via the way-valid bit update instruction path 25 provided between the instruction fetch unit 15 and the way-valid bit control unit 16. The The way valid bit update instruction path 25 functions as a way information update instruction path for transmitting a way valid bit update instruction signal.

  When a cache instruction for switching the number of ways is executed in the processor core, the instruction fetch unit 15 outputs a way bit update instruction signal. The way-valid bit control unit 16 updates the way-valid bit WV according to the way-valid bit update instruction signal from the instruction fetch unit 15. According to the third method, efficient processing can be made possible by user's free setting. The way valid bit update instruction path 25 is not limited to the case where it is provided between the instruction fetch unit 15 and the way valid bit control unit 16, and it is possible to transmit the way valid bit update instruction signal to the way valid bit control unit 16. It may be provided at any position.

  Next, way integration in a cache system according to a modification of the present embodiment will be described with reference to FIGS. The cache system according to this modification is characterized in that not only ways with the same index but also ways with different indexes can be integrated.

  For example, as shown above the white arrow in FIG. 10, it is assumed that the weighted bit WV for index 0 is “10”. As shown above the white arrow in FIG. 11 with respect to the valid bit WV “10”, the index 0 of the instruction cache data RAM 10 includes the cache data of the line A and the cache data of the line B having consecutive addresses. Stored.

  Next, as shown below the white arrow in FIG. 10, it is assumed that the valid bit WV for index 0 is “10” and the valid bit WV for index 1 is “00”. The way valid bit WV “00” of index 1 indicates that both way 0 and way 1 are invalid ways. For the valid bit WV “10” for index 0, the cache data of line A and the cache data of line B are stored in index 0 of the instruction cache data RAM 10 as shown below the white arrow in FIG. Stored. For the valid bit WV “00” for index 1, cache data for line C (Line C) and cache data for line D (Line D) are stored in index 1 of the instruction cache data RAM 10.

  It is assumed that the line C is data of continuous addresses with respect to the line B. It is assumed that the line D is data of continuous addresses with respect to the line C. Way 0 and way 1 of index 1 are integrated into way 0 and way 1 of index 0 different from index 1 across the boundary of the index.

  In the index 0 of the cache tag RAM 11, the tag information of the line A is stored in the original way 0. The cache data stored in the index 1 is uniquely determined to be the cache data of the line C and the line D having consecutive addresses with respect to the line A and the line B stored in the index 0. Therefore, it is not necessary to store the tag information of line C and the tag information of line D in index 1. Since it is not necessary to determine whether the way 0 and the way 1 of the index 1 are valid, both the valid bits V of the index 1 are “don't care” (indicated as “−” in the figure). Further, since index 0 and index 1 are treated as one cache line, the replace bit R of index 1 is also set to “don't care”.

  The lines of index 0 and index 1 are used as cache lines having a line size four times that of the original two-way set associative system by way integration. For sequential requests, line A, line B, line C, and line D are not required because the tag information of line B, line C, and line D is read and compared and cache data is selected by hitting line A. The cache data is output. The integrated way is divided into the original way by setting the way valid bit WV of index 0 and index 1 to “11”, and is reconfigured to the original set-associative cache line.

  A way may be integrated not only for two indexes but also for three or more indexes, and can be integrated for all indexes at the maximum. According to this modification, by integrating ways of not only the same index but also different indexes, a cache line having a line size exceeding the line size of the instruction cache data RAM 10 originally mounted can be freely set. The integration of ways for different indexes will eventually allow the processor to use the cache memory as if it were local memory.

(Second Embodiment)
FIG. 12 is a block diagram showing the configuration of the cache system according to the second embodiment of the present invention. The cache system according to the present embodiment includes a tag memory access control unit 35. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted. The cache system according to the present embodiment includes an instruction cache data RAM 30, a cache tag RAM 31, an instruction cache control unit 32, a tag comparison circuit 13, and an instruction fetch unit 15.

  The instruction cache data RAM 30 and the cache tag RAM 31 are divided into a memory bank corresponding to the way 0 and a memory bank corresponding to the way 1. Each memory bank corresponds to one way. The instruction cache control unit 32 includes a valid bit control unit 33 and a tag memory access control unit 35. The valid bit storage unit 34 is a register or a small-scale memory, and is provided in the valid bit control unit 33. The way-valid bit storage unit 34 stores the way-valid bit WV controlled by the way-valid bit control unit 33. The tag memory access control unit 35 controls access to each memory bank of the cache tag RAM 31 based on the valid bit WV stored in the valid bit storage unit 34. Note that the tag information, the valid bit V, and the replace bit R, which are information other than the way valid bit WV, are stored in the cache tag RAM 31 as in the first embodiment.

  For example, suppose that the valid bit WV stored in the valid bit storage unit 34 for a certain index is “11”. The way valid bit WV “11” indicates that both way 0 and way 1 are valid ways. The tag memory access control unit 35 permits access to both the memory bank corresponding to the way 0 and the memory bank corresponding to the way 1 with respect to the way valid bit WV “11”. In response to an access from the instruction cache control unit 32, the cache tag RAM 31 activates both the memory bank corresponding to the way 0 and the memory bank corresponding to the way 1, and reads the tag information from both memory banks.

  Next, it is assumed that the valid bit WV stored in the valid bit storage unit 34 for a certain index is “10”. The way valid bit WV “10” indicates that the way 0 is a valid way and the way 1 is an invalid way. For the way valid bit WV “10”, the tag memory access control unit 35 permits access to the memory bank corresponding to the way 0 and blocks access to the memory bank corresponding to the way 1. In this manner, the tag memory access control unit 35 suppresses access to the memory bank corresponding to the invalid way. In response to an access from the instruction cache control unit 32, the cache tag RAM 31 activates only the memory bank corresponding to the way 0 and reads the tag information from only the memory bank corresponding to the way 0.

  In the present embodiment, a way-valid bit storage unit 34 is provided in the way-valid bit control unit 33 in order to block unnecessary access to the cache tag RAM 31 by the tag memory access control unit 35 based on the way-valid bit WV. It is desirable. The cache system according to the present embodiment activates only the memory bank in which the valid way specified by the way valid bit WV is present, thereby comparing the tag information as compared with the case where the entire cache tag RAM 31 is activated. To reduce power consumption when reading. Thereby, there exists an effect that power consumption can be reduced further.

  When each memory bank corresponds to one way, the instruction cache data RAM 30 and the cache tag RAM 31 are divided into m memory banks for m ways. The cache system according to the present embodiment is not limited to the case where the number of original ways matches the number of memory banks. Each memory bank may correspond to a plurality of ways, and the number of memory banks may be smaller than the number of ways. For example, when a 4-way set associative method including way 0, way 1, way 2, and way 3 is adopted, the instruction cache data RAM 30 and the cache tag RAM 31 may be divided into two memory banks. In this case, one memory bank corresponds to two ways, way 0 and way 1, and the other memory bank corresponds to two ways, way 2 and way 3. Thus, even when each memory bank is associated with a plurality of ways, an effect of reducing power consumption can be obtained.

The block diagram which shows the structure of the cache system which concerns on 1st Embodiment. The figure explaining the structure of instruction cache data RAM. The figure explaining the structure of a cache tag RAM, and a way bit. The figure explaining integration of the way in cash tag RAM. The figure explaining integration of the way in instruction cache data RAM. The figure explaining the structure for updating a way valid bit by a 1st system. The figure explaining the structure for updating a way valid bit by a 2nd system. The figure which shows the example of the memory map defined by the address decoder. The figure explaining the structure for updating a way bit according to a 3rd system. The figure explaining the integration of the way beyond the index boundary in cash tag RAM. The figure explaining the integration of the way beyond the index boundary in instruction cache data RAM. The block diagram which shows the structure of the cache system which concerns on 2nd Embodiment.

Explanation of symbols

  10, 30 Instruction cache data RAM, 11, 31 Cache tag RAM, 16, 33 Way valid bit control unit, 21 Access counter, 23 Address decoder, 25 Way valid bit update instruction path, 35 Tag memory access control unit.

Claims (5)

A cache data storage unit configured to store cache data in a plurality of ways for each index; and
A valid way which is a way capable of storing cache data whose address is discontinuous with respect to other cache data stored in the cache data storage unit, and a cache whose address is discontinuous with respect to the other cache data A way information control unit that controls which way information represents each way for each index, which corresponds to an invalid way that is a way for which data storage is restricted, and
The cache data storage unit is configured to be able to integrate the invalid way into the valid way having the same or different index as the invalid way. An access counter that counts at least one of the number of sequential requests that are accesses to consecutive addresses and the number of branch requests that are accesses to discontinuous addresses;
The cache according to claim 1, wherein the way information control unit updates the way information based on at least one of the number of sequential requests and the number of branch requests counted by the access counter. system. Having an address decoder for decoding the accessed address;
The cache system according to claim 1, wherein the way information control unit updates the way information based on a definition by the address decoder.   2. The cache system according to claim 1, further comprising a way information update instruction path for transmitting a way information update instruction signal for instructing update of the way information to the way information control unit. A cache tag storage unit that is divided into a plurality of memory banks corresponding to one or a plurality of the ways and stores cache tag information;
A tag memory access control unit that controls access to the memory bank based on the way information controlled by the way information control unit;
The cache system according to claim 1, wherein the tag memory access control unit suppresses access to the memory bank corresponding to the invalid way.

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