JP2009247091A - Apparatus and method for charge/discharge control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably supply power when batteries are changed and change batteries in safety even when of multiple batteries, one other than a discharged one is charged with a solar battery or a charge circuit, such as an external power supply. <P>SOLUTION: A power supply and three or more chargeable/dischargeable batteries are provided. On receipt of the results of voltage level comparison at a comparison circuit, a selection circuit appropriately selects a battery highest in voltage level. In conjunction therewith, a charge/discharge controlling means changes the on/off state of each discharge and charge switch. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a charge / discharge control device and a charge / discharge control method for driving a connected electronic device while switching a plurality of batteries.

  Patent Document 1 (Japanese Patent Laid-Open No. 5-111169) discloses a conventional battery discharge control method in which a plurality of batteries are switched to drive an electronic device for a long time, and a plurality of batteries are switched periodically or aperiodically. A battery discharge control method for driving an electronic device for a long time is described.

  However, there is a risk that the power supply may be interrupted momentarily when the battery is switched, and there is a problem that an electronic device driven by the battery may malfunction.

  Further, in Patent Document 2 (Japanese Patent No. 2539971), in order to supply power stably at the time of battery switching, the switches connecting a plurality of batteries and the load circuit are all turned on and then the voltage of each battery is turned on. Is described, and a device configuration for connecting a battery with a normal voltage to a load circuit is described.

Japanese Patent Laid-Open No. 5-111169 Japanese Patent No. 2539971

  In the above conventional technology, in the case of a charging / discharging device having a plurality of batteries and charging a battery other than a discharging battery with a charging circuit such as a solar cell or an external power source, the battery and the load circuit are arranged. When all the switches to be connected are in the ON state, an excessive current exceeding the power supply capability of the charging circuit such as the connected solar cell or external power source flows, which may damage them.

  The present invention provides a charging / discharging control device and a charging / discharging control device that can supply a stable power supply when switching batteries and can safely switch a battery even when charged by a charging circuit such as a solar battery or an external power supply. An object is to provide a control method.

  In order to solve the above problems, the present invention provides a charge / discharge control device connected to a power supply device connected to a power supply and an electronic device having a load circuit, and is capable of charging and discharging three or more connected to the load circuit of the electronic device. A battery, a charging circuit for connecting to and charging each battery, a charging switch for connecting and disconnecting each charging circuit and each battery, and connecting each battery and the load circuit And a discharge switch to be disconnected, a comparison circuit connected to each of the batteries and comparing a voltage level of each of the batteries, and connected to the comparison circuit and receiving a comparison result of the voltage level in the comparison circuit, the most voltage A selection circuit that sequentially selects a battery having a high level and a trigger signal that detects that the voltage of the load circuit has dropped below a predetermined voltage level. Is connected to the selection circuit, receives a battery selection result from the selection circuit, and holds the selection result in response to the trigger signal in the first storage means. A second storage means for connecting and receiving and holding the output signal of the selection result held by the first storage means; and an output signal of the contents held by the first storage means and the second storage means And a charge / discharge control means for controlling switching between the discharge switches and the charge switches.

  Further, the invention described in claim 2 is characterized in that the charging circuit is connected to a solar battery.

  Furthermore, the invention described in claim 3 is characterized in that a D-type flip-flop is used for the first storage means and the second storage means.

  Furthermore, in the invention according to claim 4, the charge / discharge control means sets each of the charge switches to a switch ON state, and the voltage of the load circuit is set to a first voltage level after the switch ON state of each of the charge switches. When the selection circuit selects one of the batteries with the highest voltage level, the first storage means receives the first output signal from the selection circuit and the first trigger from the detection means. Receiving a signal, sending an output signal from the first storage means based on the reception of the first output signal and the first trigger signal to the second storage means, and the second storage means An output signal from the first storage means based on the first trigger signal and an output signal from the first storage means is sent to the charge / discharge control means, and the charge / discharge control means Voltage level The discharge switch connected to the battery with a high battery level is turned on, the charge switch is turned off, and the discharge switches other than those connected to the battery with the highest voltage level are turned off, the charge switch When the voltage of the load circuit drops to the second voltage level, the first storage means receives the second output signal from the selection circuit and the detection means. Receiving a second trigger signal, sending an output signal from the second storage means based on the reception of the second output signal and the second trigger signal to the second storage means; The storage means includes a second output signal from the second storage means based on the second trigger signal and an output signal from the second first storage means. By sending to the power control means, the charge / discharge control means turns on the discharge switch connected to the battery having the highest voltage level and the battery having the second highest voltage level, and turns the charge switch off. It is characterized by controlling to the state.

  According to the present invention, it is possible to supply a stable power supply at the time of battery switching, and it is possible to safely switch the battery even during charging by the charging circuit.

  Examples will be described below. It should be noted that ￣ above the symbol in the drawing indicates inversion.

  FIG. 5 is a block diagram showing a connection relationship between apparatuses. The power supply device 101 is connected to the AC power supply 100 or disconnected. Further, the power supply apparatus 101 converts an alternating current from the AC power supply 100 into a direct current. Furthermore, the power supply apparatus 101 is connected to the charge / discharge control apparatus 102 of the present invention. The charge / discharge control device 102 uses the DC power source Vcc generated by the power source device 101 as a power source. The charge / discharge control device 102 is connected to the solar cell 4 and a load circuit (not shown) in the electronic device 103.

  FIG. 1 shows a circuit configuration of a charge / discharge control apparatus 102 of the present invention. First, the configuration will be described using this.

  In this embodiment, when connected to the AC power supply 100, the load circuit is operated by Vcc generated by the power supply apparatus 101 connected to the AC power supply, and the power supply apparatus 101 is not connected to the AC power supply 100. In this case, the electronic device 103 is operated using a battery as a power source.

  There are three batteries used in the present embodiment: battery a36, battery b37, and battery c38. Each battery is connected to a load circuit via FETa33, FETb34 and FETc35 which are discharge switches.

  Vcc generated by the power supply device 101 connected to the AC power supply 100 is connected to the load circuit via the diode 45 for preventing backflow.

  In the present invention, the DC power supply of the power supply device applied to the load circuit of the electronic device 103 is referred to as V_BACK. V_BACK is a DC voltage applied to the load circuit, and the voltage level of V_BACK is substantially the same as Vcc when the power supply apparatus 101 is connected to the AC power supply 100. On the other hand, when the power supply apparatus 101 is not connected to the AC power supply 100, the voltage level of V_BACK is substantially the same as any one of the voltages Va, Vb, and Vc of the connected battery. Here, the voltage of the battery a36 is Va, the voltage of the battery b37 is Vb, and the voltage of the battery c38 is Vc.

  Also, charge switches FETd39, FETe40, and FETf41 are connected to the battery a36, the battery b37, and the battery c38, respectively. In order to charge each battery by the power supply device 101 through these charging switches, a battery charging circuit a1 is connected to the battery a36, a battery charging circuit b2 is connected to the battery b37, and a battery charging circuit c3 is connected to the battery c38. Yes.

  Each battery has a diode a5 for the battery a36, a diode b6 for the battery b37, and a diode c7 for the battery c38 so that the batteries can be charged even when the power supply device 101 is not connected to the AC power supply 100. Are connected, and the solar cell 4 is connected through these diodes. Note that a charging circuit may be provided outside the charging / discharging circuit instead of the solar battery 4.

  Furthermore, in order to compare the voltage Va of the battery a36, the voltage Vb of the battery b37, and the voltage Vc of the battery c38, the battery a36 has a comparator a9 and a comparator c11, the battery b37 has a comparator a9 and a comparator b10, and the battery c38 has a comparator. b10 and the comparator c11 are connected. In addition, the battery voltage comparison circuit 8 is comprised by the comparator a9, the comparator b10, and the comparator c11.

  These comparators are generally used. When the voltage at the + terminal is higher than the voltage at the-terminal, a signal of "H" level (power supply voltage) is output. When the voltage is higher than the voltage at the + terminal, a signal of “L” level (0 V) is output.

  The battery voltage comparison circuit 8 compares the voltage level relationship among the three batteries. The comparator a9 outputs an AB comparison result signal as a result of comparing Va and Vb, the comparator b10 outputs a comparison result of Vb and Vc, a BC comparison result signal, and the comparator c11 outputs Vc and Vc. As a result of comparing Va, a CA comparison result signal is output to the battery selection circuit 12.

  Based on the comparison result of the battery voltage comparison circuit 8, the battery selection circuit 12 for selecting the battery with the highest voltage, and the selection result of the battery selection circuit 12 are latched and held using the D-FF / CLK signal as a trigger. A latch circuit A13 and a latch circuit B17 that latches and holds the output of the latch circuit A13 in response to the D-FF / CLK signal are provided.

  The battery selection circuit 12 includes an AND gate a136, an AND gate b137, an AND gate c138, an inverter gate a236 connected to the AND gate a136, an inverter gate b237 connected to the AND gate b137, and an inverter gate c238 connected to the AND gate c138. And has operating characteristics corresponding to the truth table of FIG. 2 described later.

  The AND gate a136 outputs an Out_a signal, the AND gate b137 outputs an Out_b signal, and the AND gate c138 outputs an Out_c signal.

  The latch circuit a13 latches and holds an Out_a signal indicating that the battery a36 output from the battery selection circuit 12 has been selected, and an Out_b signal that indicates that the battery selection circuit 12 has selected the battery b37. The D-FF A15 latches and holds the Out_c signal indicating that the battery selection circuit 12 has selected the battery c38.

  The latch circuit B17 latches and holds the signal from the output terminal Q of the D-FF • A15 and the D-FF • B18 that latches and holds the signal from the output terminal Q of the D-FF • A14 of the latch circuit A13. The D-FF · B19 for holding and the D-FF · B20 for latching and holding the signal from the output terminal Q of the D-FF · A16. D-FF • A14-16 and D-FF • B18-20 are D-type flip-flops that are generally used.

  The output terminals Q of the D-FF 14 · A and the D-FF · B 18 are connected to an OR gate a21 and a NOR gate d23, respectively. The output terminal of the OR gate a21 is connected to the transistor a22, and the OR gate a21 controls ON / OFF of the FET a33 that is a discharge switch of the battery a36 via the transistor a22.

  The output terminal of the NOR gate d23 is connected to the transistor d24, and the NOR gate d23 controls ON / OFF of the FET d39 which is a charge switch of the battery a36 via the transistor d24.

  The output terminals Q of D-FF · A15 and D-FF · B19 are connected to an OR gate b25 and a NOR gate e27, respectively. The output terminal of the OR gate b25 is connected to the transistor b26, and the OR gate b25 controls ON / OFF of the FET b34 which is a discharge switch of the battery b37 via the transistor b26.

  The output terminal of the NOR gate e27 is connected to the transistor e28, and the NOR gate e27 controls the FETe40, which is a charge switch for the battery b37, via the transistor e28.

  The output terminals Q of the D-FF 16 · A and the D-FF · B 20 are connected to an OR gate c29 and a NOR gate f31, respectively. An output terminal of the OR gate c29 is connected to the transistor c30, and the OR gate c29 controls ON / OFF of the FET c35 that is a discharge switch of the battery c38 via the transistor c30.

  The output terminal of the NOR gate f31 is connected to the transistor f32, and the NOR gate f31 controls the FET f41, which is a charge switch for the battery c38, via the transistor f32.

  Further, the battery voltage comparison circuit 8, the battery selection circuit 12, the latch circuit A13, the latch circuit B17, the power sources of the OR gates and the NOR gates are connected to a load circuit.

  The load circuit is connected to the Vcc terminals of the reset ICa42 and the reset ICb44. The reset ICa42 and the reset ICb44 are commonly used reset ICs. When the voltage of V_BACK connected to the Vcc terminal of each reset IC becomes lower than the set voltage of each reset IC, the output terminal RESET1 And an output signal of a pulse of “L” level (0 V) for a predetermined time.

  When the voltage of the load circuit is equal to or higher than the set voltage of each reset IC, an output signal of “H” level (power supply voltage) is output to the output terminals RESET1 and RESET2.

  The RESET1 signal from the reset ICa 42 is inverted by the inverter 43 to become a D-FF · CLK signal. The inverter 43 is connected to the CLK terminals of the D-FF · A14 to 16 and D-FF · B18 to 20, and each D-FF receives the D-FF · CLK signal. The data signal input to the D ″ terminal is latched and held and output to the Q terminal or the inverted Q terminal.

  The reset ICb 44 is connected to the CLR terminal of each of the D-FF • A14 to 16 and the D-FF • B18 to 20. When the RESET2 signal of “L” level (0 V) is sent from the reset ICb 44 to the D-FF • A14-16 and D-FF • B18-20, the D-FF • A14-16 and D-FF • B18-20 are latched.・ Clear the stored data and output the output signal of “L” level (0V) to the Q terminal and “H” level (power supply voltage) to the inverted Q terminal. Normally, the set voltage of the reset ICa42 is set to V_RESET1, and the set voltage of the reset ICb44 is set to V_RESET2. The relationship between V_RESET1 and V_RESET2 is set as V_RESET1> V_RESET2.

  FIG. 2 is a truth table showing the relationship between the comparison result of the battery voltage comparison circuit 8 and the output of the battery selection circuit 12. This truth table will be described.

  There are six patterns of voltage level relationships among the battery voltages Va, Vb, and Vc. For example, when Va = Vb, control is performed as H. Further, the comparison result of the battery voltage comparison circuit 8 and the output signal output from the battery selection circuit 12 are determined from the relationship between the voltage levels. The battery voltage comparison circuit 8 compares the relationship between the voltage levels of the three batteries, the comparison result of Va and Vb is an AB comparison result, the comparison result of Vb and Vc is a BC comparison result, and , Vc and Va are output to the battery selection circuit 12 as a C-A comparison result output signal.

  The battery selection circuit 12 selects the battery with the highest voltage based on the output comparison result.

  For example, when Va> Vb> Vc, the AB comparison result and the BC comparison result are H, and the CA comparison result is L. At this time, since Va has the highest voltage, the battery a36 is selected, and the Out_a signal, which is an output signal from the AND gate a136, becomes the “H” level.

  FIG. 3 shows a truth table of D-FFs 14 to 20 which are D-type flip-flops, which will be described. In addition, the top of the character in drawing shows inversion.

  This D-type flip-flop has six terminals of inverted PRE, inverted CLR, CLK, D, Q, and inverted Q, and signals of various levels are input or output thereto.

  For H, the input or output signal is at the H level. In L, an input or output signal is L level. X is an H level signal or an L level signal that is input or output. ↑ indicates a rising edge that changes from L to H. ↓ indicates the fall from H to L. Q0 indicates the Q level immediately before the input condition shown in the truth table is satisfied, and inverted Q0 indicates the Q level immediately before ↑ or ↓ is input.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 4 is an operation timing chart of the circuit. The operation timing chart starts from a state in which the load circuit is operating when the power supply apparatus 101 is connected to the AC power supply 100 and is supplied with power through the charge / discharge control apparatus 102.

  Each battery is assumed to be fully charged after being completely discharged once when the power supply apparatus 101 is not connected to the AC power supply 100. While the power supply device 101 is not connected to the AC power supply 100, the battery voltages Va, Vb, and Vc are lower than the set voltage V_RESET2 of the reset ICb44, so that D-FF • A14-16 and D-FF • B18− 20 is cleared by the RESET2 signal.

  The initial state shown in this operation timing chart is a state in which an output signal of “L” level (0 V) is output from the output Q terminal and an output signal of “H” level (power supply voltage) is output from the inverted Q terminal. It has become.

  Since all output signals from the output terminals Q of the D-FF · A14 to 16 and D-FF · B18 to 20 are “L” level (0V) output signals, the OR gates a21, The output signals from the gate b25 and the OR gate c29 are at the “L” level (0 V). As a result, the discharge switches FETa33, FETb34, and FETc35 are in the OFF state, and at this time, each battery is not connected to the load circuit.

  Further, the output signals of the NOR gate d23, NOR gate e27 and NOR gate f31, which are negative logical sums, become “H” level, and the charging switches FETd39, FETe40 and FETf41 are in the ON state, and each battery is It is charged by either the battery charging circuits 1 to 3 or the solar battery 4.

  In the first state shown in the operation timing chart of FIG. 4, the voltage Va of the battery a36 is the highest, then the voltage Vb of the battery b37, and the lowest is the voltage Vc of the battery c38, that is, the relationship between the voltage levels is Va> Vb> Vc.

  Voltages Va, Vb, and Vc change according to the situation.

  The battery voltage comparison circuit 8 compares the relationship between the voltage levels of the three batteries, the comparison result of Va and Vb is an AB comparison result, the comparison result of Vb and Vc is a BC comparison result, and , Vc and Va are output to the battery selection circuit 12 as a C-A comparison result output signal.

  The battery selection circuit 12 selects the battery with the highest voltage based on the output comparison result, and when the battery a36 is selected, from the AND gate a136, when the battery b37 is selected, from the AND gate b137, the battery c38. Is selected, an output signal of “H” level (power supply voltage) is output from the AND gate c138.

  That is, in the first state shown in the operation timing chart of FIG. 4, since the voltage Va of the battery a36 is the highest, the battery selection circuit 12 outputs an output signal of “H” level (power supply voltage) from the AND gate a136. select.

  Such comparison of voltage levels among the three batteries and selection by comparison are always performed. The battery selection circuit 12 sequentially selects the battery with the highest voltage.

  Then, when the power supply device 101 is not connected to the AC power supply 100 and the voltage of Vcc generated from the power supply device 101 starts to decrease, V_BACK (shaded portion in FIG. 4) also starts to decrease (A in FIG. 4). point). At this time, the discharge switches FETa33, FETb34 and FETc35 remain in the switch OFF state.

  After that, V_BACK further decreases (points A to J in FIG. 4), and at the moment when the voltage drops below the V_RESET1 voltage (point J in FIG. 4), the reset ICa 42 operates and remains at the “L” level (0V) for a certain time. RESET1 signal, which is an output signal of).

  Then, the RESET1 signal is output from the reset ICa42, inverted by the inverter 43, becomes a D-FF / CLK signal as a rising pulse, and is supplied to the CLK terminals of the D-FF / A14-16 and D-FF / B18-20. The The D-FF · A14 to 16 and D-FF · B18 to 20 latch the signal level of the “D” terminal and output it to the output terminal Q, and hold the state.

  At this time, since the battery selection circuit 12 outputs the “H” level output signal from the AND gate a136, the “H” level output signal is output only from the output terminal Q of the D-FF • A14. As a result, the output signal from the NOR gate d23 which is a negative logical sum connected to the D-FF · A14 and the D-FF · B18 becomes the “L” level. Further, the NOR gate d23 outputs the output signal to the transistor d24 to be connected, whereby the FET d39 which is a charging switch of the battery a36 is turned off, and the battery a36 is disconnected from the charging circuit.

  Further, the output signal from the output of the OR gate a21 which is a logical sum connected to the D-FF · A14 and the D-FF · B18 becomes “H” level. Further, the OR gate a21 outputs the output signal to the transistor a22 to be connected, whereby the FETa33 which is a discharge switch of the battery a36 is turned on, and the battery a36 is connected to the load circuit.

  Thereby, the voltage of V_BACK rises to the voltage Va of the battery a36, and power from the battery a36 is supplied to the load circuit (point B in FIG. 4).

  In addition, the minimum power supply voltage value at which the load circuit operates is smaller than the V_RESET2 voltage value, so that the load circuit operates stably even when the power supplied to the load circuit is switched to the battery.

  On the other hand, the operation of D-FF • A15, D-FF • A16, D-FF • B19 and D-FF • B20 will be described. Output signals of “L” level (0 V) are output from the output terminals Q of D-FF • A15, D-FF • A16, D-FF • B19 and D-FF • B20.

  The NOR gate e27, which is a negative OR connected to the D-FF · A15 and D-FF · B19, outputs an “H” level output signal. The charging switch FETe40 connected to the NOR gate e27 is in the switch ON state, and the battery b37 is charged from the solar cell 4.

  Further, an OR signal b25 connected to D-FF • A15 and D-FF • B19 outputs an “L” level (0 V) output signal. The discharge switch FETb34 of the battery b37 connected to the OR gate b25 is in the switch OFF state, and the battery b37 is not connected to the load circuit.

  Furthermore, an output signal of “H” level is output from the NOR gate f31 which is a negative OR connected to the D-FF • A16 and the D-FF • B20. The charge switch FETf41 connected to the NOR gate f31 is in the switch ON state, and the battery c38 is charged from the solar cell 4.

  Further, an output signal of “L” level (0 V) is output from the OR gate c29 which is connected to D-FF • A16 and D-FF • B20. The discharge switch FETb34 of the battery c38 connected to the OR gate c29 is in the switch OFF state and is not connected to the load circuit with the battery c38.

  Thereafter, while power is supplied from the battery a36 to the load circuit, the power supplied from the battery a36 decreases and Va decreases, so that the relationship between the three battery voltage levels is Va> Vb> Vc to Vb> Va>. Suppose that the relationship is Vc. Then, the battery selection circuit 12 outputs an output signal of “L” level (0 V) from the AND gate a136 and “H” level from the AND gate b137.

  Further, at the instant when the voltage Va decreases and the relationship between the three battery voltage levels becomes Vb> Vc> Va and decreases to the V_RESET1 voltage or lower, the reset ICa 42 operates again to maintain the “L” level ( 0V) is output as a RESET1 signal.

  Then, a rising pulse is supplied to the CLK terminals of D-FF • A14 to 16 and D-FF • B18 to 20 connected to the reset ICa42, and D-FF • A14 to 16 and D-FF18 to 20 • B are “D”. "Latch the signal level of the terminal.

  At this time, since the battery selection circuit 12 outputs an “H” level output signal from the AND gate b137, the latch circuit A13 outputs an “H” level output signal only from the Q terminal of the D-FF • A15. Is done. In the latch circuit B17, when the relationship between the three battery voltage levels is Va> Vb> Vc, only the Q terminal of the D-FF • A14 latches the output signal of “H” level. The latch outputs an output signal of “H” level only to D-FF · B18.

  Since an “H” level output signal is output from the Q terminal of the D-FF · B15, an “L” level (0 V) output signal is output from the NOR gate e27. Then, the NOR gate e27 outputs an output signal to the transistor e28 to be connected, whereby the charge switch FETe40 of the battery b37 is turned off, and the battery b37 is disconnected from the charging circuit.

  The OR gate b25 outputs an “H” level output signal, the discharge switch FETb34 of the battery b37 is turned on via the connected transistor b26, and the battery b37 is connected to the load circuit to supply power. Start.

  Further, since an “H” level output signal is output from the Q terminal of the D-FF • B 18, the OR gate a 21 also outputs an “H” level output signal. That is, the discharge switch FETa33 of the battery a36 remains in the ON state, and the battery a36 is continuously connected to the load circuit (point C in FIG. 4).

  However, at this time, the voltage Va of the battery a36 is significantly lower than the voltage Vb of the battery b37. Therefore, the discharge switch FETa33 connected to the battery a36 is reverse-biased, and the battery a36 supplies power to the load circuit. The voltage Va gradually increases (points C to D in FIG. 4).

  Eventually, the voltage Va of the battery a36 and the voltage Vb of the battery b37 become the same (point D in FIG. 4).

  The battery a36 and the battery b37 are connected to the load circuit in parallel, and supply power to the load circuit (points D to E in FIG. 4).

  When the power supply of the battery a36 and the battery b37 decreases and the voltage Vb + Va, which is the sum of the voltages of both batteries, drops below the V_RESET1 voltage, the battery c38 having the highest voltage in this state is selected by the battery selection circuit 12 this time. (Point E in FIG. 4).

  Note that Va and Vb at this time are of a lower voltage level than the initial Va and Vb.

  On the other hand, the battery b37 continues to be connected to the load circuit, the battery c38 and the battery b37 are connected to the load circuit in parallel, and both batteries supply power to the load circuit (points E to F in FIG. 4).

  When Vc> Vb> Va, the output signals at the Q terminals of D-FF • A14 and D-FF • B18 are both “L” level, so that the discharge switch FETa33 is in the OFF state and the charge switch FETd39 is It becomes an ON state (points E to G in FIG. 4). Therefore, the battery a36 can be charged from the solar battery 4, and can be discharged after charging.

  In this way, by charging a battery that has not been discharged with the solar battery 4 or the like, even when the power supply apparatus 101 is not connected to the AC power supply 100, power can be supplied from the charge / discharge control apparatus 102 to the electronic device 103. Can be used for a long time.

  If the solar cell 4 or the like is not connected, the switching between the batteries is repeated until the voltage of each battery becomes equal to or lower than the V_RESET1 voltage. When all the battery voltages become equal to or lower than the V_RESET1 voltage, the battery is switched. Operation stops and any two batteries remain connected to the load circuit.

  In this state, the battery voltage decreases, and the reset ICb 44 operates when the voltage becomes equal to or lower than the V_RESET2 voltage. Then, the reset ICb 44 outputs a RESET2 signal, which is a clear signal, to all D-FFs connected thereto, so that all D-FFs are in a reset state. Thus, an output signal of “L” level (0 V) is output from the Q terminals of all D-FFs.

  Further, an output signal of “H” level is output from the inversion Q of D-FF. As a result, the discharge switches FETa33, FETb34, and FETc35 are turned off, and each battery is disconnected from the load circuit, whereby the operation of the load circuit is stopped.

  In FIG. 4, Va, which is the voltage of the battery a36 among the three batteries, has been described as being the highest at first, but the present invention is not limited to this.

  In the embodiment of the present invention, three batteries are given as an example, but four or more batteries can be applied.

  As described above, the present invention provides the latch circuit A13 that latches and holds the result of the battery comparison selection circuit when the voltage of the load circuit drops below a certain level, and further latches the previous selection result. A latch circuit B17 for holding is provided, and each discharge switch is controlled to be switched ON / OFF by a value obtained by logically summing the outputs of the two latch circuits. As a result, even when the battery is switched, the connected battery is continuously connected to the load circuit, so that it is possible to switch the battery stably without instantaneous power interruption.

  In addition, by controlling each charging switch to the switch ON / OFF state with a negative logical sum of the outputs of the two latch circuits, the charging circuit is disconnected at the time of discharging, thereby preventing deterioration and breakage of the charging circuit. .

  In addition, when the battery is not discharged, the battery can be charged by an external charging circuit or solar cell, and the electronic devices not connected to the AC power source can be driven for a long time while switching between charging and discharging with multiple batteries. Is possible.

The circuit structure of the charging / discharging control apparatus of this invention. A truth table showing the relationship between each battery voltage level, the comparison result of the battery comparison circuit and the output of the battery selection circuit. Truth table for D-type flip-flops. The operation | movement timing chart of this invention. The block diagram which showed the connection relation between apparatuses.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Battery charging circuit a, 2 ... Battery charging circuit b, 3 ... Battery charging circuit c, 4 ... Solar cell, 5 ... Diode a, 6 ... Diode b, 7 ... Diode c, 8 ... Battery voltage comparison circuit, 9 ... Comparator a, 10 ... Comparator b, 11 ... Comparator c, 12 ... Battery selection circuit, 13 ... Latch circuit A, 14, 15, 16 ... D-FF • A, 17 Latch circuit B, 18, 19, 20 ... D- FF · B, 21 ... OR gate a, 22 ... transistor a, 23 ... NOR gate d, 24 ... transistor d, 25 ... OR gate b, 26 ... transistor b, 27 ... NOR gate e, 28 ... transistor e, 29 ... OR gate c, 30 ... transistor c, 31 ... NOR gate f, 32 ... transistor f, 33 ... FETa, 34 ... FETb 35 ... FETc, 36 ... battery a, 37 ... battery b, 38 ... battery c, 39 ... FETd, 40 ... FETe, 41 ... FETf, 42 ... reset ICa, 43 ... inverter, 44 ... reset ICb, 45 ... diode, 100 ... AC power supply 101 ... Power supply apparatus 102 ... Charge / discharge control apparatus 103 ... Electronic equipment 136 ... AND gate a 137 ... AND gate b 138 ... AND gate c 236 ... Inverter gate a 237 ... Inverter gate b 238 ... Inverter gate c.

Claims (4)

In a charge / discharge control device connected to a power supply device connected to a power supply and an electronic device having a load circuit,
Three or more chargeable / dischargeable batteries connected to a load circuit of the electronic device, a charging circuit connected to each battery and charging each battery, and connecting each charging circuit and each battery; A charge switch for disconnecting, a discharge switch for connecting and disconnecting each battery and the load circuit, a comparison circuit for connecting to each battery and comparing the voltage level of each battery, and connecting to the comparison circuit, And, according to the comparison result of the voltage level in the comparison circuit, a selection circuit that sequentially selects the battery having the highest voltage level, and detects that the voltage of the load circuit has dropped below a predetermined voltage level, and generates a trigger signal Connected to the detection means for outputting and the selection circuit, receives the battery selection result from the selection circuit, and selects by the trigger signal. A first storage means for holding a result; a second storage means connected to the first storage means for receiving and holding an output signal of the selection result held by the first storage means; A charge / discharge control means for controlling switching of each discharge switch and each charge switch based on an output signal of contents held in the first storage means and the second storage means is provided. Charge / discharge control device.   The charge / discharge control device according to claim 1, wherein the charging circuit is connected to a solar battery.   2. A charge / discharge control apparatus according to claim 1, wherein a D-type flip-flop is used for said first storage means and said second storage means.   The charging / discharging control means is configured so that each charging switch is in a switch ON state, and after the charging switch is in a switch ON state, the voltage of the load circuit decreases to a first voltage level or less, and the selection circuit is the most When one battery having a high voltage level is selected, the first storage means receives the first output signal from the selection circuit and the first trigger signal from the detection means, and the first output signal And an output signal from the first storage means based on the reception of the first trigger signal is sent to the second storage means, and the second storage means is connected to the first trigger signal and the first trigger signal. The output signal from the first storage means based on the output signal from the first storage means is sent to the charge / discharge control means, and the charge / discharge control means is connected to the battery having the highest voltage level. The discharge switch is turned on, the charge switch is turned off, the discharge switches other than those connected to the battery having the highest voltage level are turned off, the charge switch is turned on, Thereafter, when the voltage of the load circuit drops to the second voltage level, the first storage means receives the second output signal from the selection circuit and the second trigger signal from the detection means. The second output means and the second storage means based on the reception of the second output signal and the second trigger signal are sent to the second storage means, and the second storage means The second trigger signal and the second output signal from the second storage means based on the second output signal from the first storage means to the charge / discharge control means, The charge / discharge control means controls the discharge switch connected to the battery having the highest voltage level and the battery having the second highest voltage level to an ON state and a charge switch to an OFF state. A charge / discharge control method using the charge / discharge control apparatus according to claim 1.

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