JP2009246189A - Method of manufacturing semiconductor substrate, semiconductor substrate, and piezoelectric device using semiconductor substrate - Google Patents

Method of manufacturing semiconductor substrate, semiconductor substrate, and piezoelectric device using semiconductor substrate Download PDF

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JP2009246189A
JP2009246189A JP2008092121A JP2008092121A JP2009246189A JP 2009246189 A JP2009246189 A JP 2009246189A JP 2008092121 A JP2008092121 A JP 2008092121A JP 2008092121 A JP2008092121 A JP 2008092121A JP 2009246189 A JP2009246189 A JP 2009246189A
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semiconductor substrate
forming
insulating layer
electrode
microhole
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Taichi Tsuchiya
太一 土屋
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Citizen Finetech Miyota Co Ltd
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Citizen Finetech Miyota Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a through electrode forming process of reducing floating capacitance between a through electrode portion and a semiconductor substrate since the floating capacitance is in inverse proportion to the thickness of an insulating layer with respect to a method of manufacturing a semiconductor substrate having a through electrode, the semiconductor substrate, and a piezoelectric device using the semiconductor substrate. <P>SOLUTION: In a stage of forming a through microhole 4 by dry etching along a sacrificial layer 3 formed on the semiconductor substrate 1, at least one annular hole 5 is formed outside the through microhole 4. In a stage of forming an insulating layer into the through microhole 4 by the thermal oxidation, the insulating layer is formed which includes, in one body, an oxide film on a surface of the through microhole 4 and an oxide film filling the annular hole 5, and an oxide film filling a thin portion of the semiconductor substrate 1 between the through microhole 4 and annular hole 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、浮遊容量を低減した貫通電極を有する半導体基板の製造方法、半導体基板、及び半導体基板を用いた圧電デバイスに関するものである。   The present invention relates to a method for manufacturing a semiconductor substrate having a through electrode with reduced stray capacitance, a semiconductor substrate, and a piezoelectric device using the semiconductor substrate.

一般的に、半導体基板の配線技術として、貫通電極が用いられ、多様な形成方法や、形状が開示されている。例えば特許文献1参照。
特開2007−294821号公報
Generally, a through electrode is used as a wiring technique for a semiconductor substrate, and various forming methods and shapes are disclosed. For example, see Patent Document 1.
JP 2007-294821 A

図6−1、および図6−2は、従来の貫通電極形成プロセスを説明する要部断面図である。以下、図6−1、図6−2を用いて、従来の貫通電極形成プロセスについて説明する。   FIGS. 6A and 6B are main part cross-sectional views illustrating a conventional through electrode forming process. Hereinafter, a conventional through electrode forming process will be described with reference to FIGS. 6A and 6B.

まず、(a)Si半導体基板1上にSiO膜2を熱酸化により形成後、(b)表側のSiO膜2をエッチングにより除去した後、感光性樹脂などのレジスト材料で貫通微細孔を形成するための犠牲層3を形成する。 First, (a) after forming the SiO 2 film 2 on the Si semiconductor substrate 1 by thermal oxidation, (b) removing the SiO 2 film 2 on the front side by etching, and then forming through-holes with a resist material such as a photosensitive resin. A sacrificial layer 3 for forming is formed.

次に、(c)ドライエッチングにより、Si半導体基板1を加工し、貫通微細孔4を形成する。   Next, (c) the Si semiconductor substrate 1 is processed by dry etching to form through-holes 4.

次に、(d)犠牲層3をOアッシングで除去し、(e)熱酸化を行い、Si半導体基板1の表面、裏面、及び、貫通微細孔4に絶縁層(SiO膜)6を形成する。この時、Si半導体基板1の裏面のSiO膜2と絶縁層(SiO膜)6は一体化する。 Next, (d) the sacrificial layer 3 is removed by O 2 ashing, (e) thermal oxidation is performed, and an insulating layer (SiO 2 film) 6 is formed on the front and back surfaces of the Si semiconductor substrate 1 and the through-holes 4. Form. At this time, the SiO 2 film 2 and the insulating layer (SiO 2 film) 6 on the back surface of the Si semiconductor substrate 1 are integrated.

次に、(f)Si半導体基板1の表側にスパッタにより金属膜を形成し、フォトリソを行った後、Au等のメッキを行い、貫通微細孔4内に電極部を形成し、前記金属膜の不要部分を除去し、貫通電極7を形成する。   Next, (f) a metal film is formed on the front side of the Si semiconductor substrate 1 by sputtering, photolithography is performed, then Au or the like is plated, an electrode portion is formed in the through microhole 4, and the metal film Unnecessary portions are removed, and through electrodes 7 are formed.

次に、(g)Si半導体基板1の裏側にフォトリソを行い、貫通電極7に対向するSi半導体基板1の裏側のSiO膜2と絶縁層(SiO膜)6をエッチングにより除去する。 Next, (g) photolithography is performed on the back side of the Si semiconductor substrate 1 to remove the SiO 2 film 2 and the insulating layer (SiO 2 film) 6 on the back side of the Si semiconductor substrate 1 facing the through electrode 7 by etching.

次に、(h)スパッタにより裏面に金属膜を形成し、フォトリソ、エッチングを行い、裏側に裏面電極8を設け、貫通電極7と導通させる。   Next, (h) a metal film is formed on the back surface by sputtering, photolithography and etching are performed, the back electrode 8 is provided on the back side, and the through electrode 7 is conducted.

貫通電極を有する半導体基板を用いた圧電デバイスにおいて、貫通電極と半導体基板間の浮遊容量は絶縁層の厚みに反比例する。前記浮遊容量は、半導体基板に搭載される圧電素子の特性に影響を与える。   In a piezoelectric device using a semiconductor substrate having a through electrode, the stray capacitance between the through electrode and the semiconductor substrate is inversely proportional to the thickness of the insulating layer. The stray capacitance affects the characteristics of the piezoelectric element mounted on the semiconductor substrate.

半導体基板に貫通電極を形成する製造方法において、半導体基板上にフォトリソグラフィにより貫通微細孔を形成するための犠牲層をレジストで形成する工程と、前記犠牲層に沿ってドライエッチングにより貫通微細孔を形成する工程により、貫通微細孔を形成した後、熱酸化で絶縁層を形成する方法では、貫通電極の絶縁層の厚さを、浮遊容量を低減するほど厚くできない。又、CVDによる絶縁層を形成する方法の場合、Si基板表面の絶縁層の厚さは、貫通電極の絶縁層の厚さより厚くなるため、貫通電極の絶縁層を、所望の厚さ形成した場合、絶縁層の応力によるSi半導体基板の変形が大きくなる。   In a manufacturing method for forming a through electrode on a semiconductor substrate, a step of forming a sacrificial layer for forming a through micro hole on the semiconductor substrate by photolithography using a resist, and forming the through micro hole by dry etching along the sacrificial layer In the method of forming an insulating layer by thermal oxidation after forming through-holes in the forming step, the thickness of the insulating layer of the through-electrode cannot be increased so as to reduce the stray capacitance. Also, in the case of the method of forming an insulating layer by CVD, the thickness of the insulating layer on the Si substrate surface is thicker than the thickness of the insulating layer of the through electrode, so that the insulating layer of the through electrode is formed to a desired thickness The deformation of the Si semiconductor substrate due to the stress of the insulating layer becomes large.

本発明は、貫通孔電極を有する半導体基板の製造方法において、貫通電極内に所望の厚さの絶縁層を形成することが出来、それにより、浮遊容量が低減可能で、且つ貫通電極以外の絶縁層の厚さを抑えられるため、絶縁層の応力により半導体基板が変形してしまうことを抑えることが可能な、半導体基板の製造方法、半導体基板、および半導体基板を用いた圧電デバイスを提供することを課題とする。   The present invention provides a method for manufacturing a semiconductor substrate having a through-hole electrode, whereby an insulating layer having a desired thickness can be formed in the through-electrode, whereby the stray capacitance can be reduced and insulation other than the through-electrode can be formed. To provide a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a piezoelectric device using the semiconductor substrate, which can suppress the deformation of the semiconductor substrate due to the stress of the insulating layer because the thickness of the layer can be suppressed. Is an issue.

上記目的を達成するため、本発明の半導体基板の製造方法は、半導体基板上にフォトリソグラフィにより貫通微細孔を形成するための犠牲層をレジストで形成する工程と、前記犠牲層に沿ってドライエッチングにより貫通微細孔を形成する工程と、前記貫通微細孔を形成した後、前記貫通微細孔を含む、半導体基板表面に熱酸化により絶縁層を形成する工程と、前記貫通微細孔に金属を充填して貫通電極を形成する工程とを有する半導体基板の製造方法であって、前記犠牲層に沿ってドライエッチングにより貫通微細孔を形成する工程にて、貫通微細孔の外側に、少なくとも1つの環状孔を形成し、前記貫通微細孔に熱酸化により絶縁層を形成する工程にて、貫通微細孔表面の酸化膜と環状孔を埋める酸化膜、及び、貫通微細孔と環状孔との間の半導体基板の薄肉部に埋めこまれた酸化膜とを一体化した、絶縁層を形成することを特徴とする。   In order to achieve the above object, a method of manufacturing a semiconductor substrate according to the present invention includes a step of forming a sacrificial layer on a semiconductor substrate by photolithography using a resist, and dry etching along the sacrificial layer. Forming a through microhole, forming the through microhole, forming an insulating layer on the surface of the semiconductor substrate including the through microhole by thermal oxidation, and filling the through microhole with metal. And forming a through-hole electrode, wherein at least one annular hole is formed outside the through-microhole in the step of forming the through-hole hole by dry etching along the sacrificial layer. In the step of forming an insulating layer by thermal oxidation in the through-microholes, an oxide film on the surface of the through-microholes and an oxide film filling the annular holes, and the through-microholes and the annular holes Of integrating the oxide film embedded in the thin portion of the semiconductor substrate, and forming an insulating layer.

上記目的を達成するため、本発明の半導体基板の製造方法は、半導体基板上にフォトリソグラフィにより微細溝を形成するための犠牲層をレジストで形成する工程と、前記犠牲層に沿ってドライエッチングにより微細溝を形成する工程と、前記微細溝を形成した後、前記微細溝を含む、半導体基板表面に熱酸化により絶縁層を形成する工程と、前記微細溝に金属を充填して貫通電極を形成する工程と、前記半導体基板裏面を研磨加工する工程と、前記半導体基板裏面に絶縁層を形成する工程と、裏面に金属膜を形成し、前記電極と接続する工程を有する半導体基板の製造方法であって、前記犠牲層に沿ってドライエッチングにより微細溝を形成する工程にて、貫通微細溝の外側に、少なくとも1つの環状溝を形成し、前記微細溝に熱酸化により絶縁層を形成する工程にて、微細溝表面の酸化膜と環状溝を埋める酸化膜、及び、微細溝と環状溝との間の半導体基板の薄肉部に埋めこまれた酸化膜とを一体化した、絶縁層を形成することを特徴とする。   In order to achieve the above object, a method of manufacturing a semiconductor substrate according to the present invention includes a step of forming a sacrificial layer for forming a fine groove on a semiconductor substrate by photolithography using a resist, and dry etching along the sacrificial layer. Forming a fine groove; forming the fine groove and then forming an insulating layer on the surface of the semiconductor substrate including the fine groove by thermal oxidation; and filling the fine groove with metal to form a through electrode A method of manufacturing a semiconductor substrate, comprising: a step of polishing the back surface of the semiconductor substrate; a step of forming an insulating layer on the back surface of the semiconductor substrate; and a step of forming a metal film on the back surface and connecting to the electrodes. In the step of forming the fine groove by dry etching along the sacrificial layer, at least one annular groove is formed outside the through fine groove, and the fine groove is thermally oxidized. In the process of forming the insulating layer, the oxide film on the surface of the fine groove and the oxide film filling the annular groove and the oxide film buried in the thin part of the semiconductor substrate between the fine groove and the annular groove are integrated. An insulating layer is formed.

本発明の半導体基板の製造方法は、前記半導体基板表面の絶縁層の厚さは、前記貫通電極の絶縁層の厚さより薄く形成することができる。   In the method for manufacturing a semiconductor substrate of the present invention, the thickness of the insulating layer on the surface of the semiconductor substrate can be formed thinner than the thickness of the insulating layer of the through electrode.

本発明の半導体基板は、上記製造方法によって製造したことを特徴とする。   The semiconductor substrate of the present invention is manufactured by the above manufacturing method.

本発明の圧電デバイスは、上記半導体基板表面に圧電素子を搭載し、半導体基板に別の基板を接合することにより、圧電素子が真空封止されることを特徴とする。   The piezoelectric device of the present invention is characterized in that the piezoelectric element is vacuum-sealed by mounting the piezoelectric element on the surface of the semiconductor substrate and bonding another substrate to the semiconductor substrate.

本発明の半導体基板の製造方法により、半導体基板の浮遊容量と、半導体基板の変形を抑えた貫通電極の形成が可能な、半導体基板の製造方法、半導体基板、及び半導体基板を用いた圧電デバイスを提供することができる。   According to the semiconductor substrate manufacturing method of the present invention, a semiconductor substrate manufacturing method, a semiconductor substrate, and a piezoelectric device using the semiconductor substrate, which can form a floating electrode of the semiconductor substrate and a through electrode that suppresses deformation of the semiconductor substrate. Can be provided.

本発明の最良の実施形態について図を用いて説明する。   The best embodiment of the present invention will be described with reference to the drawings.

図1−1、および図1−2は、実施例1における貫通電極形成プロセスを説明する要部断面図である。図2は、実施例1における貫通微細孔と環状孔とを説明する斜視図である。以下、図1−1、図1−2を用いて、本実施例の半導体基板の製造方法について説明する。   FIGS. 1-1 and 1-2 are cross-sectional views of relevant parts for explaining a through electrode forming process in the first embodiment. FIG. 2 is a perspective view for explaining through fine holes and annular holes in the first embodiment. Hereinafter, the manufacturing method of the semiconductor substrate of the present embodiment will be described with reference to FIGS. 1-1 and 1-2.

まず、(a)Si半導体基板1上に、SiO膜2を熱酸化により形成後、(b)Si半導体基板1の表側のSiO膜2をエッチングにより除去した後、感光性樹脂などのレジスト材料で犠牲層3を形成する。 First, (a) the SiO 2 film 2 is formed on the Si semiconductor substrate 1 by thermal oxidation, and (b) the SiO 2 film 2 on the front side of the Si semiconductor substrate 1 is removed by etching, followed by a resist such as a photosensitive resin. The sacrificial layer 3 is formed of a material.

次に、(c)ドライエッチングにより、Si半導体基板1を加工し、貫通微細孔4と環状孔5とを形成する。貫通微細孔4と環状孔5との間には、Si半導体基板1の薄肉部9が形成される。図2参照。   Next, (c) the Si semiconductor substrate 1 is processed by dry etching to form through-holes 4 and annular holes 5. A thin portion 9 of the Si semiconductor substrate 1 is formed between the through minute hole 4 and the annular hole 5. See FIG.

次に、(d)犠牲層3をOアッシングで除去し、(e)熱酸化によって、貫通微細孔4と環状孔5の表面を含むSi半導体基板1の表面が膨張しながら酸化膜に変化し、絶縁層(SiO膜)6が形成される。この時、Si半導体基板1の裏面のSiO膜2と絶縁層(SiO膜)6は一体化する。さらに貫通微細孔4と環状孔5との間のSi半導体基板の薄肉部9には酸化膜が埋めこまれ、貫通微細孔4表面の酸化膜と、環状孔5を埋める酸化膜と、一体化し絶縁層(SiO膜)6となる。 Next, (d) the sacrificial layer 3 is removed by O 2 ashing, and (e) the surface of the Si semiconductor substrate 1 including the surfaces of the through-holes 4 and the annular holes 5 is expanded to an oxide film by thermal oxidation. Then, an insulating layer (SiO 2 film) 6 is formed. At this time, the SiO 2 film 2 and the insulating layer (SiO 2 film) 6 on the back surface of the Si semiconductor substrate 1 are integrated. Further, an oxide film is embedded in the thin portion 9 of the Si semiconductor substrate between the through microhole 4 and the annular hole 5, and the oxide film on the surface of the through microhole 4 and the oxide film filling the annular hole 5 are integrated. The insulating layer (SiO 2 film) 6 is formed.

次に、(f)Si半導体基板1の表側にスパッタにより金属膜を形成し、フォトリソを行った後、Au等のメッキを行い、前記メッキ後は、不用個所のスパッタにより形成した金属膜を除去し、貫通電極7を形成する。   Next, (f) a metal film is formed on the front side of the Si semiconductor substrate 1 by sputtering, and after photolithography, Au or the like is plated. After the plating, the metal film formed by sputtering at an unnecessary place is removed. Then, the through electrode 7 is formed.

次に、(g)Si半導体基板1の裏側にフォトリソを行い、貫通電極7に対向するSiO膜2と絶縁層(SiO膜)6をエッチングにより除去する。 Next, (g) photolithography is performed on the back side of the Si semiconductor substrate 1, and the SiO 2 film 2 and the insulating layer (SiO 2 film) 6 facing the through electrode 7 are removed by etching.

次に、(h)スパッタにより裏面に金属膜を形成し、フォトリソ、エッチングを行い、Si半導体基板1の裏側に裏面電極8を設け、貫通電極7と導通させる。   Next, (h) a metal film is formed on the back surface by sputtering, photolithography and etching are performed, the back electrode 8 is provided on the back side of the Si semiconductor substrate 1, and the through electrode 7 is made conductive.

図4−1、および図4−2は、実施例2における貫通電極形成プロセスを説明する要部断面図である。以下、図4−1、図4−2を用いて、本実施例の半導体基板の製造方法について説明する。   FIGS. 4-1 and FIGS. 4-2 are principal part sectional drawings explaining the penetration electrode formation process in Example 2. FIGS. Hereinafter, the manufacturing method of the semiconductor substrate of the present embodiment will be described with reference to FIGS.

まず、(a)Si半導体基板11の表側に、感光性樹脂などのレジスト材料で犠牲層13を形成する。   First, (a) a sacrificial layer 13 is formed on the front side of the Si semiconductor substrate 11 with a resist material such as a photosensitive resin.

次に、(b)ドライエッチングにより、Si半導体基板11を加工し、微細溝14と環状溝15とを形成する。微細溝14と環状溝15との間には、Si半導体基板11の薄肉部19が形成される。   Next, (b) the Si semiconductor substrate 11 is processed by dry etching to form the fine grooves 14 and the annular grooves 15. A thin portion 19 of the Si semiconductor substrate 11 is formed between the fine groove 14 and the annular groove 15.

次に、(c)犠牲層をOアッシングで除去し、(d)熱酸化によって、微細溝14と環状溝15の表面を含むSi半導体基板11の表面が膨張しながら酸化膜に変化し、絶縁層(SiO膜)16が形成される。さらに微細溝14と環状溝15との間のSi半導体基板11の薄肉部19には酸化膜が埋めこまれ、微細溝14表面の酸化膜と、環状溝15を埋める酸化膜と、一体化し絶縁層(SiO膜)16となる。 Next, (c) the sacrificial layer is removed by O 2 ashing, and (d) by thermal oxidation, the surface of the Si semiconductor substrate 11 including the surfaces of the fine grooves 14 and the annular grooves 15 is expanded and changed into an oxide film, An insulating layer (SiO 2 film) 16 is formed. Further, an oxide film is buried in the thin portion 19 of the Si semiconductor substrate 11 between the fine groove 14 and the annular groove 15, and the oxide film on the surface of the fine groove 14 and the oxide film filling the annular groove 15 are integrated and insulated. A layer (SiO 2 film) 16 is formed.

次に、(e)Si半導体基板11の表側にスパッタにより金属膜を形成し、フォトリソを行った後、Au等のメッキを行い、前記メッキ後は、不用個所のスパッタにより形成した金属膜を除去し、貫通電極17を形成する。   Next, (e) a metal film is formed on the front side of the Si semiconductor substrate 11 by sputtering, photolithography is performed, and Au or the like is then plated. After the plating, the metal film formed by sputtering at an unnecessary place is removed. Then, the through electrode 17 is formed.

次に、(f)Si半導体基板11の裏面を研磨し、貫通電極17を露出させる。   Next, (f) the back surface of the Si semiconductor substrate 11 is polished to expose the through electrodes 17.

次に、(g)CVDなどにより、Si半導体基板11の裏側に絶縁層(SiO膜)12を形成する。 Next, (g) an insulating layer (SiO 2 film) 12 is formed on the back side of the Si semiconductor substrate 11 by CVD or the like.

次に、(h)Si半導体基板11の裏側にフォトリソを行い、貫通電極17に対向する絶縁層(SiO膜)12を除去する。 Next, (h) photolithography is performed on the back side of the Si semiconductor substrate 11 to remove the insulating layer (SiO 2 film) 12 facing the through electrode 17.

次に、(i)スパッタにより裏面に金属膜を形成し、フォトリソ、エッチングを行い、Si半導体基板11の裏側に裏面電極18を設け、貫通電極17と導通させる。   Next, (i) a metal film is formed on the back surface by sputtering, photolithography and etching are performed, a back electrode 18 is provided on the back side of the Si semiconductor substrate 11, and the through electrode 17 is made conductive.

尚、実施例1、実施例2では、環状孔、または環状溝を1つ形成した実施例を示したが、図3に示すように、貫通孔4を囲む複数の環状孔5(あるいは環状溝)を形成してもよい。複数の環状孔を形成することによって、貫通電極の絶縁層をより厚く形成することが可能となり、貫通電極と半導体基板間の浮遊容量をさらに低減させることができる。図3は、貫通微細孔の外側に環状孔を2つ形成した要部断面図である。   In the first embodiment and the second embodiment, an example in which one annular hole or annular groove is formed is shown. However, as shown in FIG. 3, a plurality of annular holes 5 (or annular grooves) surrounding the through hole 4 are shown. ) May be formed. By forming the plurality of annular holes, the insulating layer of the through electrode can be formed thicker, and the stray capacitance between the through electrode and the semiconductor substrate can be further reduced. FIG. 3 is a cross-sectional view of a main part in which two annular holes are formed outside the through-holes.

図5は、実施例3における圧電デバイスの断面図である。ここでは、圧電素子を気密封止した圧電デバイスを例に説明する。   FIG. 5 is a cross-sectional view of the piezoelectric device according to the third embodiment. Here, a piezoelectric device in which a piezoelectric element is hermetically sealed will be described as an example.

圧電デバイス50を構成するSi半導体基板20の片側には、フォトリソ、ドライエッチングにより凹部21が形成され、凹部21には、上述したような半導体基板の製造方法によって貫通電極22の絶縁層を約6μmの厚さに形成した貫通電極22が形成され、Si半導体基板20の表面には、貫通電極22の絶縁層の厚さよりも薄い2〜3μm程度の絶縁層が形成されている。   A recess 21 is formed on one side of the Si semiconductor substrate 20 constituting the piezoelectric device 50 by photolithography and dry etching, and the insulating layer of the through electrode 22 is formed in the recess 21 by the semiconductor substrate manufacturing method as described above. A through electrode 22 having a thickness of about 2 to 3 μm is formed on the surface of the Si semiconductor substrate 20, which is thinner than the insulating layer of the through electrode 22.

Si半導体基板20の凹部21を形成した側の電極部に、導電性接着剤等により、圧電素子30を搭載した後、前記Si半導体基板20に、蓋40となる基板を接合する。この際、接合は真空チャンバー内で行い、圧電素子30を搭載した空間は、真空状態になるようにする。   A piezoelectric element 30 is mounted on the electrode portion of the Si semiconductor substrate 20 on which the concave portion 21 is formed by using a conductive adhesive or the like, and then a substrate to be the lid 40 is joined to the Si semiconductor substrate 20. At this time, bonding is performed in a vacuum chamber so that the space in which the piezoelectric element 30 is mounted is in a vacuum state.

貫通電極22の浮遊容量低減により、圧電素子30は、安定した発振特性を保持する。さらにSi半導体基板20の表面の絶縁層の応力による変形を抑えることができる。   Due to the reduction of the stray capacitance of the through electrode 22, the piezoelectric element 30 maintains stable oscillation characteristics. Furthermore, deformation due to stress of the insulating layer on the surface of the Si semiconductor substrate 20 can be suppressed.

実施例1における貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a through electrode forming process in Example 1 実施例1における貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a through electrode forming process in Example 1 実施例1における貫通微細孔と環状孔とを説明する斜視図The perspective view explaining the penetration fine hole and the annular hole in Example 1 貫通微細孔の外側に環状孔を2つ形成した要部断面図Cross-sectional view of the main part in which two annular holes are formed outside the through-holes 実施例2における貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a through electrode forming process in Example 2 実施例2における貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a through electrode forming process in Example 2 実施例3における圧電デバイスの断面図Sectional drawing of the piezoelectric device in Example 3 従来の貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a conventional through electrode forming process 従来の貫通電極形成プロセスを説明する要部断面図Cross-sectional view of relevant parts for explaining a conventional through electrode forming process

符号の説明Explanation of symbols

1 Si半導体基板
2 SiO
3 犠牲層
4 貫通微細孔
5 環状孔
6 絶縁層(SiO膜)
7 貫通電極
8 裏面電極
9 薄肉部
11 Si半導体基板
12 絶縁層(SiO膜)
13 犠牲層
14 微細溝
15 環状溝
16 絶縁層(SiO膜)
17 貫通電極
18 裏面電極
19 薄肉部
20 Si半導体基板
21 凹部
22 貫通電極
30 圧電素子
40 蓋
50 圧電デバイス
1 Si semiconductor substrate 2 SiO 2 film 3 sacrificial layer 4 through micropores 5 annular hole 6 insulating layer (SiO 2 film)
7 Through electrode 8 Back electrode 9 Thin portion 11 Si semiconductor substrate 12 Insulating layer (SiO 2 film)
13 Sacrificial layer 14 Fine groove 15 Annular groove 16 Insulating layer (SiO 2 film)
17 Through electrode 18 Back electrode 19 Thin portion 20 Si semiconductor substrate 21 Recess 22 Through electrode 30 Piezoelectric element 40 Lid 50 Piezoelectric device

Claims (5)

半導体基板上にフォトリソグラフィにより貫通微細孔を形成するための犠牲層をレジストで形成する工程と、
前記犠牲層に沿ってドライエッチングにより貫通微細孔を形成する工程と、
前記貫通微細孔を形成した後、前記貫通微細孔を含む、半導体基板表面に熱酸化により絶縁層を形成する工程と、
前記貫通微細孔に金属を充填して貫通電極を形成する工程とを有する半導体基板の製造方法において、
前記犠牲層に沿ってドライエッチングにより貫通微細孔を形成する工程にて、貫通微細孔の外側に、少なくとも1つの環状孔を形成し、
前記貫通微細孔に熱酸化により絶縁層を形成する工程にて、貫通微細孔表面の酸化膜と環状孔を埋める酸化膜、及び、貫通微細孔と環状孔との間の半導体基板の薄肉部に埋めこまれた酸化膜とを一体化した、絶縁層を形成することを特徴とする半導体基板の製造方法。
Forming a sacrificial layer for forming through-holes by photolithography on a semiconductor substrate with a resist;
Forming a through microhole by dry etching along the sacrificial layer;
Forming an insulating layer by thermal oxidation on the surface of the semiconductor substrate including the through micropores after forming the through micropores;
In the method of manufacturing a semiconductor substrate, including a step of forming a through electrode by filling the through fine hole with a metal,
Forming at least one annular hole outside the through microhole in the step of forming the through microhole by dry etching along the sacrificial layer;
In the step of forming an insulating layer by thermal oxidation in the through-microhole, an oxide film on the surface of the through-microhole and an oxide film filling the annular hole, and a thin portion of the semiconductor substrate between the through-microhole and the annular hole A method of manufacturing a semiconductor substrate, comprising forming an insulating layer integrated with an embedded oxide film.
半導体基板上にフォトリソグラフィにより微細溝を形成するための犠牲層をレジストで形成する工程と、
前記犠牲層に沿ってドライエッチングにより微細溝を形成する工程と、
前記微細溝を形成した後、前記微細溝を含む、半導体基板表面に熱酸化により絶縁層を形成する工程と、
前記微細溝に金属を充填して貫通電極を形成する工程と、前記半導体基板裏面を研磨加工する工程と、前記半導体基板裏面に絶縁層を形成する工程と、裏面に金属膜を形成し、前記電極と接続する工程を有する半導体基板の製造方法において、
前記犠牲層に沿ってドライエッチングにより微細溝を形成する工程にて、貫通微細溝の外側に、少なくとも1つの環状溝を形成し、
前記微細溝に熱酸化により絶縁層を形成する工程にて、微細溝表面の酸化膜と環状溝を埋める酸化膜、及び、微細溝と環状溝との間の半導体基板の薄肉部に埋めこまれた酸化膜とを一体化した、絶縁層を形成することを特徴とする半導体基板の製造方法。
Forming a sacrificial layer for forming a fine groove by photolithography on a semiconductor substrate with a resist;
Forming a fine groove by dry etching along the sacrificial layer;
Forming the insulating layer by thermal oxidation on the surface of the semiconductor substrate including the fine groove after forming the fine groove;
Filling the fine groove with metal to form a through electrode, polishing the back surface of the semiconductor substrate, forming an insulating layer on the back surface of the semiconductor substrate, forming a metal film on the back surface, In a method of manufacturing a semiconductor substrate having a step of connecting to an electrode,
Forming a fine groove by dry etching along the sacrificial layer, forming at least one annular groove outside the through fine groove;
In the step of forming an insulating layer by thermal oxidation in the fine groove, the oxide film on the surface of the fine groove and the oxide film filling the annular groove, and the thin portion of the semiconductor substrate between the fine groove and the annular groove are buried. A method of manufacturing a semiconductor substrate, comprising forming an insulating layer integrated with an oxide film.
前記半導体基板表面の絶縁層の厚さは、前記貫通電極の絶縁層の厚さより薄く形成されることを特徴とする請求項1または2に記載の半導体基板の製造方法。   The method for manufacturing a semiconductor substrate according to claim 1, wherein a thickness of the insulating layer on the surface of the semiconductor substrate is formed to be thinner than a thickness of the insulating layer of the through electrode. 請求項1から3のいずれか1つに記載の半導体基板の製造方法によって製造したことを特徴とする半導体基板。   A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1. 請求項4に記載の半導体基板を用いた圧電デバイスであって、
前記半導体基板表面には圧電素子が搭載され、前記半導体基板に別の基板を接合することにより、圧電素子が真空封止されることを特徴とする圧電デバイス。
A piezoelectric device using the semiconductor substrate according to claim 4,
A piezoelectric device, wherein a piezoelectric element is mounted on the surface of the semiconductor substrate, and the piezoelectric element is vacuum-sealed by bonding another substrate to the semiconductor substrate.
JP2008092121A 2008-03-31 2008-03-31 Method of manufacturing semiconductor substrate, semiconductor substrate, and piezoelectric device using semiconductor substrate Pending JP2009246189A (en)

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