JP2009245323A - System and method for reducing latency - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plurality of directories for managing a cache state in one node and to guarantee coherency. <P>SOLUTION: A system for reducing latency includes a first processor, a memory, a first directory, a second directory, a first directory control unit, and a second directory control unit. The memory is shared by the first processor belonging to one node and a second processor belonging to the other node. The first directory manages the cache state of the one node. The second directory manages the cache state of the other node. The first directory control unit processes a request issued in the one node, and searches the first directory. The second directory control unit processes a request issued from the other node, searches the second directory, and performs predetermined control for guaranteeing coherency. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a latency shortening method and method.

  In a related technique, in order to simplify control for ensuring coherency, cache management related to memory addresses is performed in one directory, and requests are processed in the order received. However, if the cache is managed by one directory as in this related technique, there is the following problem. That is, when the directory is placed at the memory controller, the distance from other nodes is increased, and when the directory is placed at the global switch, the distance from the processor in the own node is increased. Therefore, there is a problem that the latency of request processing from the own node or other nodes deteriorates depending on the directory position.

  The request processing path will be described with reference to FIGS. 1A and 1B which are explanatory diagrams of the related technology 1 and FIGS. 2A and 2B which are explanatory diagrams of the related technology 2. FIG. Related Art 1 is a configuration in which a directory is connected only to a memory controller. Related technology 2 is a configuration in which a directory is connected only to a global switch.

  FIG. 1A and FIG. 2A are explanatory diagrams of a case where there is valid data in the cache of the processor 302 when a request is issued from the processor 202 to the memory 140. FIG. 1A shows a path from request issuance to data reception in the related technique 1, and FIG. 2A shows a path from request issuance to data reception in the related technique 2.

  A route in the related technique 1 of FIG. 1A will be described. When a request is issued from the processor 202, the request passes from the local switch 210 in the node 200a through the global switch 270, through the global switch 170 of the node 100a in which the memory 140 exists, through the local switch 110, and into the memory. Enter the directory control unit 120. The memory / directory control unit 120 indexes the directory 130 simultaneously with making a request to the memory 140 and issues a snoop (SNOOP: request for cache control) to the processor 302 having valid data in the cache. . This snoop passes through the local switch 110 and the global switch 170, and enters the processor 302 through the global switch 370 and the local switch 310 of the node 300a where the processor 302 exists.

  If the processor 302 that receives the snoop actually holds valid cache data, the cache data is transferred to the issuing processor 202 and a response to the snoop is returned to the memory / directory control unit 120. The cache data is transferred to the processor 202 through the local switch 310, the global switch 370, the request source global switch 270, and the local switch 210. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 302 are not displayed on the route because they do not appear as latency.

  The route in the related technique 2 of FIG. 2A will be described. When a request is issued from the processor 202, the request passes from the local switch 210 in the node 200b through the global switch / directory control unit 290 and enters the global switch / directory control unit 190 of the node 100a in which the memory 140 exists. The global switch / directory control unit 190 indexes the directory 160 simultaneously with issuing a request to the memory 140, and issues a snoop to the processor 302 that holds valid data in the cache. This snoop enters the processor 302 through the global switch / directory control unit 390 and the local switch 310 of the node 300b to which the processor 302 belongs.

  When the processor 302 that receives the snoop actually holds valid cache data, the cache data is transferred to the issuing processor 202, and a response to the snoop is returned to the global switch / directory control unit 190. The cache data is transferred to the processor 202 through the local switch 310, the global switch / directory control unit 390, the request source global switch / directory control unit 290, and the local switch 210. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 302 are not displayed on the route because they do not appear to be a latency.

  FIGS. 1B and 2B are explanatory diagrams of a case where there is valid data in the cache of the processor 101 when a request is issued from the processor 102 to the memory 140. FIG. 1B shows a path from request issuance to data reception in the related technique 1, and FIG. 2B shows a path from request issuance to data reception in the related technique 2.

  The route in the related technique 1 of FIG. 1B will be described. When a request is issued from the processor 102, the request enters the memory / directory control unit 120 from the local switch 110 in the node 100a. The memory / directory control unit 120 indexes the directory 130 simultaneously with issuing a request to the memory 140, and issues a snoop to the processor 101 holding valid data in the cache. This snoop enters the processor 101 through the local switch 110. If the processor 101 that receives the snoop actually holds valid cache data, the cache data is transferred to the processor 102 that issued the snoop, and a response to the swoop is returned to the memory / directory control unit 120. . The cache data is transferred to the processor 102 through the local switch 110. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 101 do not appear as a latency because they do not appear as a latency.

  The route in the related technique 2 in FIG. 2B will be described. When a request is issued from the processor 102, the request enters the memory control unit 180 from the local switch 110 in the node 100a. The memory control unit 180 issues a snoop to the global switch / directory control unit 190 that controls the directory 160 simultaneously with issuing a request to the memory 140. The snoop passes through the local switch 110 and enters the global switch / directory control unit 190. When the snoop is received, the global switch / directory control unit 190 indexes the directory 160 and issues the snoop to the processor 101 holding the valid data in the cache. This snoop enters the processor 101 through the local switch 110. If the processor 101 that receives the snoop actually holds the valid cache data, the cache data is transferred to the issuing processor 102 and a response to the snoop is returned to the global switch / directory control unit 190. The cache data is transferred to the processor 102 through the local switch 110. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 101 are not displayed on the route because they do not appear as latency.

  As is clear from the comparison between FIG. 1A and FIG. 2A, with regard to requests from other nodes, the latency of the related technology 2 is shorter than that of the related technology 1 because the distance to the directory is shorter. On the other hand, as is clear from the comparison between FIG. 1B and FIG. 2B, regarding the request in the own node, the related technology 2 has a longer distance to the directory than the related technology 1, and thus the latency deteriorates.

  Thus, it is conceivable to provide directories at two locations to prevent deterioration in latency that may occur in either request processing within the own node or request processing from another node.

  FIG. 3 is an explanatory diagram of request processing and snoop processing in the related technique 3 in which two directories are placed. Although only one node 100c is shown in FIG. 3, this node 100c is connected to other nodes having the same configuration via the global switch / directory control unit 190. In FIG. 3, the node 100 c includes a plurality of processors 101 and 102, a directory 130 that manages the cache state in the node, a memory 140, a memory / directory control unit 120 that controls the directory 130 and the memory 140, It has a directory 160 that manages the cache state of other nodes, a global switch / directory control unit 190 that performs routing between the nodes and controls the directory 160, and a local switch 110 that connects them within the node.

  When a request is issued from the processor 102 to the memory 140, consider a case where there is valid data in the cache of the processor existing in another node. A request (solid arrow) issued from the processor 102 in the own node reaches the memory / directory control unit 120 via the local switch 110. At the same time as issuing a request to the memory 140, the memory / directory control unit 120 indexes the directory 130 and issues a snoop to the processor of another node whose cache state is valid (solid line circle).

  On the other hand, when a request is issued from a processor belonging to another node to the memory 140, consider a case where there is valid data in the cache of a processor belonging to another node. A request (dotted arrow) from another node is received by the global switch / directory control unit 190 that controls a cache other than the own node. At the same time that the global switch / directory control unit 190 issues a request to the memory 140, the directory 160 is indexed, and a snoop is issued to a processor belonging to another node whose cache state is valid (dotted circle). .

  The problem of the related technique 3 is demonstrated using FIG. Consider the case where there is valid data in the cache of a processor residing on another node. Assume that for this data, a request issuance (solid arrow) from the processor 102 in the own node 100c and a request reception (dotted arrow) from another node occur at the same timing.

  At this time, the memory / directory control unit 120 receives and processes requests in the order of a request from the processor 102 (solid arrow) and a request from another node (dotted arrow). First, the memory / directory control unit 120 starts processing a request (solid arrow) from the processor 102 and waits for a snoop (solid line circle) response to the request from the processor 102. During this time, processing of requests (dotted arrows) from other nodes is awaited.

  On the other hand, the global switch / directory control unit 190 receives and processes snoops in the order of snoops for requests from other nodes (dotted circles), and snoops for requests in the own node (solid line circles). First, the global switch / directory control unit 190 starts a snoop (dotted circle) process for a request from another node, and issues a snoop (dotted circle) to another node. Thereafter, a response to the snoop (dotted line circle) is received from another node, but the response of the request issued to the memory 140 (dotted line arrow) is waited for, and the snoop (dotted line circle) process is terminated. During this time, the snoop (solid circle) process for the request in the own node is awaited.

  As described above, the memory / directory control unit 120 cannot receive a response of a snoop (solid circle) that is in a waiting state at the global switch / directory control unit 190, and the global switch / directory control unit 190 cannot receive a reply to a request (dotted arrow) that is in a waiting state at the memory / directory control unit 120.

  Technologies related to hierarchical memory coherency are described in the patent literature. Japanese Patent Laying-Open No. 8-16474 (see Patent Document 1) describes an invention of a multiprocessor system. The multiprocessor system includes a plurality of clusters each including a plurality of processors each having a cache memory, a local memory connected to each of the plurality of processors, and a plurality of processors and a communication control device connected to the local memory. The plurality of clusters are connected to each other via a communication control device. The communication control apparatus includes a storage unit and a cache memory content matching range determination unit. The storage means stores information related to data registered in the cache memory of the other cluster among the data of the local memory of the own cluster. The cache memory content matching range determination means determines a range in which the cache memory contents should be matched based on the storage means.

  Japanese Patent Laid-Open No. 11-13412 (see Patent Document 2) describes an invention of a distributed shared memory multiprocessor system. The distributed shared memory multiprocessor system includes a plurality of processor nodes and a ring bus. The plurality of processor nodes are arranged in a ring form, and any one of the plurality of processor nodes generates a request signal for one data block, the remaining processor nodes snoop their own internal elements, and the remaining processor nodes Any one of them generates a data block. The ring bus connects a plurality of processor nodes into a ring form, broadcasts a request signal to each of the other processor nodes, and provides a path for a single communication of data blocks to the processor node that generated the request signal.

  Japanese Patent Laying-Open No. 2006-277762 (see Patent Document 3) describes an invention of a data processing system. The data processing system includes a plurality of processors, a plurality of caches, a directory, and a control device. A plurality of caches are provided corresponding to each of the plurality of processors, and are constructed to store a plurality of cache line entries. The directory holds state information for grasping cache line entry states in a plurality of caches. The control device reads and writes status information included in the directory. The first portion of the directory holds temporary state information regarding a first subset of the plurality of cache line entries. The second part of the directory. Maintain non-primary state for the second subset of the plurality of cache line entries.

JP-A-8-16474 Japanese Patent Laid-Open No. 11-13412 JP 2006-277762 A

  An object of the present invention is to provide a plurality of directories for managing the cache state in one node, and a latency shortening method and a latency shortening method capable of ensuring coherency even when the request processing order and the snoop processing order are different Is to provide.

  The latency reduction method according to the first aspect of the present invention includes a first processor, a memory, a first directory, a second directory, a first directory control unit, and a second directory control unit. It comprises. The first processor belongs to its own node. The memory is shared by the first processor and the second processor belonging to another node. The first directory manages the cache state of the own node. The second directory manages the cache state of other nodes. The first directory control unit processes a request issued in its own node, and when receiving a first request designating a memory address, the first directory control unit indexes the first directory. When the second directory control unit processes a request issued from another node and receives a second request for specifying a memory address, the second directory control unit indexes the second directory and sends the second request. In the case of processing, when another request or snoop is received, predetermined control for ensuring coherency is performed by checking whether or not the address conflicts.

  The latency reduction method according to the second aspect of the present invention includes providing a first directory, providing a second directory, providing a first directory control unit, and providing a second directory control unit. Providing, processing the first request, and processing the third request. In providing the first directory, a first directory for managing the cache state of the own node is provided. In providing the second directory, a second directory for managing the cache state of another node is provided. In providing the first directory control unit, a first directory control unit for indexing the first directory is provided. In providing the second directory control unit, a second directory control unit for indexing the second directory is provided. In processing the first request, the first request specifying the address of the memory shared by the first processor belonging to the own node and the second processor belonging to the other node is in the own node. The first directory control unit issues a second request to the memory, indexes the first directory, and processes the first request. In processing the third request, when the third request specifying the memory address is issued from another node, the second directory control unit issues the fourth request to the memory, When the second directory is indexed and another request or snoop is received, the third request is processed by performing predetermined control to ensure coherency by checking whether the address conflicts or not. To do.

  According to the present invention, there are provided a plurality of directories for managing the cache state in one node, and a latency reduction method and a latency reduction method capable of ensuring coherency even when the request processing order and the snoop processing order are different. Can be provided.

  One of the best modes for carrying out the present invention will be described in detail with reference to the drawings. Referring to the configuration diagram of FIG. 4, in one embodiment according to the present invention, a multiplicity of multiprocessor nodes 100, 200, 300 including a shared memory are connected via global switches 150, 250, 350. Each node 100, 200, 300 includes processors 101, 102, 201, 202, 301, 302, local switches 110, 210, 310, memory / directory control units 120, 220, 320, and memories 140, 240, 340. And directories 130, 160, 230, 260, 330, and 360, and global switch / directory control units 150, 250, and 350, respectively.

  In FIG. 4, since the configurations in the three nodes 100, 200, and 300 are the same, the function of each block will be described with respect to one node 100. In the node 100, the local switch 110 is connected to the processors 101 and 102, the memory / directory control unit 120, and the global switch / directory control unit 150. The local switch 110 routes a request, a snoop, a response to the snoop (referred to as a response in this application), and a response to the request (referred to as a reply in this application) according to the destination data included in these.

  The memory / directory control unit 120 receives all requests for the memory 140. Upon receipt of the request, the memory / directory control unit 120 issues a request to the memory 140 and indexes the directory 130, and if there is a valid cache, the processor 101, 102 in the target own node or A snoop is issued to the global switch / directory control unit 150 in the own node. Thereafter, when the response to the snoop and the reply to the request issued to the memory 140 are completed, the memory / directory control unit 120 returns a reply to the request to the processor that issued the request. The request processing is terminated by returning the reply.

  In addition, the memory / directory control unit 120 receives a cancel notification from the global switch / directory control unit 150 as control for ensuring coherency. When the cancellation notification is received, the memory / directory control unit 120 compares the request stored in the buffer with the identifier ID of the cancellation target request sent together. If it matches, cancel the request.

  The directories 130 and 160 manage the cache state. The directory 130 connected to the memory / directory control unit 120 manages the cache state in the node 100. The directory 160 connected to the global switch / directory control unit 150 manages the cache state of the other nodes 200, 300, that is, the cache state of the processors 201, 202, 301, 302 belonging to the other nodes 200, 300. ing. The cache state in the node 100 includes the cache state of the processors 101 and 102 in the node 100 and the cache state of the global switch / directory control unit 150 in the node 100, that is, the processors 201, 202, There are 301 and 302 cache states.

  The global switch / directory control unit 150 is connected to the global switch / directory control units 250 and 350 of the other nodes 200 and 300, and routes requests, snoops, responses, and replies according to destination data included therein. When the global switch / directory control unit 150 receives the snoop from the memory / directory control unit 120, the global switch / directory control unit 150 indexes the directory 160. If there is a valid cache according to the index of the directory 160, a snoop is issued to the target processor. Thereafter, when the cache data is transferred to the target processor, a response to the snoop is returned to the memory / directory control unit 120.

  Similarly, when the global switch / directory control unit 150 receives a request from the global switch / directory control units 250 and 350 of the other nodes 200 and 300, it indexes the directory 160. If there is a valid cache according to the index of the directory 160, a snoop is issued to the target processor. Thereafter, when the response to the snoop and the reply to the request issued to the memory 140 are completed, the reply to the request is returned to the processor of the other node that issued the request. Further, the global switch / directory control unit 150 realizes coherency guarantee in the case where the request processing order and the snoop processing order described in the background section of the invention are different.

  Next, a detailed configuration of a part that performs control for ensuring coherency of the global switch / directory control unit 150 will be described. FIG. 5 is an explanatory diagram of the configuration of the global switch / directory control unit 150 in this embodiment. In FIG. 5, the global switch / directory control unit 150 includes an arbitration circuit 151, 158, an address matching circuit 152, a cancel determination circuit 153, a control register 154, a message storage buffer 155, a retransmission buffer 156, and a message issuance. A generation circuit 157 is included.

  The arbitration circuit 151 arbitrates messages from the local switch 110 and messages from the other nodes 200 and 300 to one. Here, the message is a generic term for request, reply, snoop, and response. The reply to the request is stored in the same entry as the corresponding request, and the response to the snoop is stored in the same entry as the corresponding snoop.

  The address matching circuit 152 performs address matching comparison with the request or snoop currently being processed stored in the message storage buffer 155 for the message narrowed down to one by the arbitration circuit 151. The address matching circuit 152 notifies the cancellation determination circuit 153 of the result of the matching comparison. The address is an address of the shared memory 140, and when a request or snoop having a matching address is found, control is performed to ensure coherency.

  The cancel determination circuit 153 receives the address comparison result from the address matching circuit 152. If there is no match, the control register 154 is updated and stored in the message storage buffer 155. If there is a match and the message is a response or reply, the control register 154 is updated and stored in the message storage buffer 155 in the same manner.

  If there is a match and the message is a request, the request is stored in the retransmission buffer 156. This is because even if a subsequent request with a matching address is registered in the message storage buffer 155, in order to maintain coherency, processing cannot be started in parallel with the preceding request. If so, the address matching request is not registered in the message storage buffer 155, but the address mismatch request following the address matching request is preferentially registered in the message storage buffer 155, and the processing of the preceding request is completed. This is because it is better in performance to start the processing of the address mismatch request without waiting until it is done. When the retransmission buffer 156 stores the address match request, it notifies the request issuer to reissue the request.

  If there is a match and the message is a snoop, the control register 154 is updated and the snoop is stored in the message storage buffer 155. For the entry of the preceding request whose address matches the snoop, the conflict flag of the control register 154 is turned on, and the entry number of the succeeding snoop is registered in the address matching entry. In this case, as described in the background section of the invention, the request processing order in the memory / directory control unit 120 and the snoop processing order in the global switch / directory control unit 190 are different. If the memory / directory control unit 120 issues a snoop for the currently processed request and does not return a response to the snoop, the memory / directory control unit 120 waits for a response to be returned and is deadlocked. Therefore, the global switch / directory control unit 150 according to the present embodiment registers the subsequent snoop in the message storage buffer 155 even if the subsequent snoop has an address match with the preceding request. Then, after a response to the snoop of the preceding request arrives, the subsequent snoop process is started.

  In the control register 154, flag information and the like necessary for processing each request or snoop stored in the message storage buffer 155 are prepared for each entry. The flag information and the like include an entry valid flag, an issue request flag, a message issued flag, a response reception flag, a reply reception flag, a data transfer flag, a conflict flag, and an address match entry.

  The message storage buffer 155 is a buffer divided into a large number of entries. A request and a snoop are stored in each entry, a response to the snoop is stored in the entry storing the snoop, and a reply to the request is stored in the entry storing the request.

  The retransmission buffer 156 stores the request when there is an address match and the message is a request. The retransmission buffer 156 also has a function of giving a request retransmission instruction to the request issuer.

  The message issue / generation circuit 157 refers to the issue request flag in the control register 154 and searches for an entry in which the issue request flag is on. Then, for the entry for which the issue request flag is on, the flag information of the control register 154 and the entry data of the message storage buffer 155 are read. Further, the directory 160 is indexed and updated, and a message to be issued next is specified as a request, snoop, response, or reply based on the flag information of the control register 154, and the message is generated.

  The arbitration circuit 158 arbitrates between a normal message sent from the message issuing / generating circuit 157 and destined for the other nodes 200 and 300 and a retransmission instruction message sent from the retransmission buffer 156 to one.

  Next, the operation of the global switch / directory control unit of FIG. 5 will be described with reference to the flowcharts of FIGS. FIG. 6 is an operation explanatory diagram when a request is received from the other nodes 200 and 300. In FIG. 6, when the global switch / directory control unit 150 receives a request from the other nodes 200 and 300, the address matching circuit 152 performs address comparison (S1 in FIG. 6). If there is no address match, the request is registered in the message storage buffer 155, and the entry valid flag and issue request flag of the control register 154 are turned on (S2 in FIG. 6).

  The message issuing / generating circuit 157 refers to the control register 154 and searches for an entry in which the issue request flag is turned on. For each entry for which the issue request flag is on, the flag information and the like are read from the control register 154, the entry data is read from the message storage buffer 155, the request is generated and issued, and the directory 160 is indexed ( S3 in FIG. Here, at the time of generating a request to the memory 140, the request issuing source is the global switch / directory control unit 150. The message issuance / generation circuit 157 shows all requests issued from the other nodes 200 and 300 to the memory / directory control unit 120 as requests issued from the global switch / directory control unit 150. In this way, snoops for requests issued from the other nodes 200 and 300 are prevented from returning to the global switch / directory control unit 150.

  The message issuing / generating circuit 157 refers to the index result of the directory 160 (S4 in FIG. 6), and if there is a valid cache, issues a snoop to the processor of the other node that holds the cache data. (S5 in FIG. 6). When the snoop is issued, the issue request flag of the control register 154 is turned off and the message issued flag is turned on. The reply to the request issued to the memory 140 and the response to the snoop issued to the other nodes 200 and 300 are returned asynchronously. When the global switch / directory control unit 150 receives a reply to the request issued to the memory 140, the global switch / directory control unit 150 instructs to update the directory 160 and turns on the reply reception flag of the control register 154. Similarly, when a response to the snoop issued to another node is received, the directory 160 is instructed to be updated, and the response reception flag of the control register 154 is turned on.

  After issuing the snoop, the message issuing / generating circuit 157 refers to the response reception flag in the control register 154, and waits until it is turned on while it is off (S6 in FIG. 6). After waiting for a while, a response to the snoop is sent from the processors of the other nodes 200 and 300 to the global switch / directory control unit 150, and the response reception flag is turned on. When the response reception flag is turned on, the contention flag in the control register 154 is referred to (S7 in FIG. 6), and the reply reception flag is referred to (S8 in FIG. 6). In parallel with the request processing described in FIG. 6, a snoop has arrived from the memory / directory control unit 120 in the own node 100 to the global switch / directory control unit 150 as indicated by a solid circle in FIG. If this is the case, the conflict flag is on.

  When the contention flag is off (S7 in FIG. 6: no) and the reply reception flag is on, the issue request flag is turned on. The message issuance / generation circuit 157 reads the flag information of the control register 154 and the entry data of the message storage buffer 155 for the entry for which the issue request flag is on, and generates and issues a reply to the request. The directory 160 is updated. When a series of request processing is completed, the entry valid flag in the control register 154 is turned off (S9 in FIG. 6).

  If there is a conflict (S7 in FIG. 6: yes), the data transfer flag in the control register 154 is referred to (S10 in FIG. 6). When a response is received (S6 in FIG. 6: Yes), this response includes information indicating whether valid cache data actually exists (with data transfer) or not (without data transfer). If there is data transfer (S10 in FIG. 6: yes), the request processing shown in the flowchart of FIG. 6 needs to be completed before the competing snoop processing, so the global switch / directory control unit The request issued by the memory 150 to the memory 140 is canceled, and the processing of the request shown in the flowchart of FIG. 6 is terminated without waiting for the response and reply to be completed. By this cancellation, the request waiting for processing registered in the memory / directory control unit 120 is canceled.

  Therefore, the global switch / directory control unit 150 turns on the issue request flag of the control register 154. The message issuance / generation circuit 157 reads the flag information of the control register 154 and the entry data of the message storage buffer 155 for the entry for which the issue request flag is turned on, and sends a request cancellation notification to the memory / directory control unit 120. The directory 160 is also updated (S11 in FIG. 6). When a cancel notification is sent, a start instruction is given to another entry storing a competing snoop. The contention snoop process will be described with reference to the flowchart of FIG. When a series of request processing is completed, the entry valid flag in the control register 154 is turned off (S12 in FIG. 6).

  If there is no data transfer (S10 in FIG. 6: No), a start instruction is given to another entry storing the competing snoop (S13 in FIG. 6). The global switch / directory control unit 150 preferentially executes the snoop process as shown by the solid line circle in FIG. 3, terminates it, returns a response to the memory / directory control unit 120, and resolves the conflict. During this time, a request to the memory 140 issued by the global switch / directory control unit 150 is put into a waiting state in the memory / directory control unit 120.

  When there is no valid cache as a result of indexing the directory 160 (S4 in FIG. 6: No), the contention flag of the control register 154 is referred to (S14 in FIG. 6), and the reply reception flag (S15 in FIG. 6). Refer to When the conflict flag is off and the reply reception flag is on, the issue request flag is turned on. The message issuance / generation circuit 157 reads the flag information of the control register 154 and the entry data of the message storage buffer 155 for the entry for which the issue request flag is on, returns a reply, and updates the directory 160. Do. When a series of request processing is completed, the entry valid flag in the control register 154 is turned off (S16 in FIG. 6).

  If the conflict flag is on (S14 in FIG. 6: yes), a start instruction is given to another entry storing the conflicting snoop (S17 in FIG. 6). The global switch / directory control unit 150 preferentially executes the snoop process as shown by the solid line circle in FIG. 3, terminates it, returns a response to the memory / directory control unit 120, and resolves the conflict. During this time, a request to the memory 140 issued by the global switch / directory control unit 150 is put into a waiting state in the memory / directory control unit 120.

  If there is an address match (S1: Yes in FIG. 6), the request is registered in the retransmission buffer 156 (S18 in FIG. 6), and a retransmission instruction is issued to the request issuer (S19 in FIG. 6).

  FIG. 7 is an explanatory diagram of an operation when a snoop is received from the memory / directory control unit 120 of the own node 100. When the global switch / directory control unit 150 receives the snoop from the memory / directory control unit 120 of the own node 100, the address matching circuit 152 performs address comparison (S31 in FIG. 7).

  If there is no address match (S31 in FIG. 7: No), it is registered in the message storage buffer 155, and the entry valid flag and issue request flag in the control register 154 are turned on (S32 in FIG. 7). The message issuing / generating circuit 157 reads the flag information of the control register 154 and the entry data of the message storage buffer 155 for the entry for which the issue request flag is on, and indexes the directory 160 (FIG. 7). S33).

  If there is valid cache data as a result of indexing the directory 160 (S34 in FIG. 7: Yes), a snoop is issued to the processors of the other nodes 200 and 300 holding the cache data (S35 in FIG. 7). ). At that time, the issue request flag of the control register 154 is turned off, and the message issued flag is turned on. When a response is received from the processors of the other nodes 200 and 300, the issue request flag and the response reception flag of the control register 154 are turned on (S36 in FIG. 7). The message issuance / generation circuit 157 reads the flag information of the control register 154 and the entry data of the message storage buffer 155 for the entry for which the issuance request flag is turned on, and the memory / directory control unit 120 of the own node 100. A response is generated and issued, and the directory 160 is updated (S37 in FIG. 7). When a series of snoop processing is completed, the entry valid flag of the control register 154 is turned off.

  If there is no valid cache (S34 in FIG. 7: No), a response is generated and issued to the memory / directory control unit 120 of the own node 100 (S38 in FIG. 7). When a series of snoop processing is completed, the entry valid flag of the control register 154 is turned off.

  Even when there is an address match (S31 in FIG. 7: Yes), the global switch / directory control unit 150 registers the snoop received from the memory / directory control unit 120 in the message storage buffer 155. Then, the global switch / directory control unit 150 turns on the entry valid flag of the control register 154, turns on the conflict flag of the control register 154 for another entry in which the address match request is stored, and also matches the address match. The entry number storing the snoop with address match is registered in the entry (S39 in FIG. 7).

  The global switch / directory control unit 150 processes the preceding request as described in the flowchart of FIG. As shown in FIG. 6, when an issuance instruction is received from a preceding request (S12, S13, S17 in FIG. 6), a snoop issuance request flag with an address match is turned on (S40 in FIG. 7). The subsequent operations (S33 to S38 in FIG. 7) are the same as those in the case where there is no address match (S31 in FIG. 7: No).

  In the present embodiment, in a large-scale system (SMP) in which a large number of multiprocessor nodes including a shared memory are connected to each other via a global switch, a directory for managing a cache state in the own node located near the memory controller, The directory that manages the cache state of other nodes in the vicinity of the global switch guarantees cache coherency and shortens the latency.

  In the present embodiment, the global switch / directory control unit 150 determines whether to cancel if the address matches with the address matching circuit 152 for confirming whether there is a preceding request or snoop having the same address. The data is read from the cancel determination circuit 153, the control register 154 that stores the flag issuance request for issuing a message, the conflicting snoop start instruction, and the like, and the message is read A message issuing / generating circuit 157 for issuing and generating is provided. As a result, the coherency of the two directories is maintained.

  As described above, the present embodiment has the following effects. The first effect is that the latency in the case where the processor that issues the request and the processor that holds the valid cache data are in different nodes is compared with the case where the directory is managed only at one location near the memory / directory control unit. It can be shortened. This is because a directory is also provided at the global switch so that a snoop for a request from another node can be issued from the global switch / directory control unit.

  As an example of the first effect, FIG. 8A shows a path from issuing a request to receiving data in a case where a request for the memory 140 is issued from the processor 202 and there is valid data in the cache of the processor 302. In the present embodiment, when a request is issued from the processor 202, the request passes from the local switch 210 in the node 200 through the global switch directory control unit 250, and the global directory of the node 100 in which the memory 140 exists. The controller 150 is entered. The global switch / directory control unit 150 indexes the directory 160 at the same time as making a request to the memory 140 (this request is canceled under a certain condition (S11 in FIG. 6)), and holds valid data in the cache. A snoop is issued to the processor 302 that is running. The snoop enters the processor 302 through the global switch / directory control unit 350 and the local switch 310 of the node 300 to which the processor 302 belongs.

  If the processor 302 that receives the snoop actually holds the valid cache data, the cache data is transferred to the issuing processor 202 and a response is returned to the global switch / directory control unit 150. The cache data is returned to the processor 202 through the local switch 310, the global switch / directory control unit 350, the request source global switch / directory control unit 250, and the local switch 210. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 302 are not displayed on the route because they do not appear to be latency.

  Compared with the path in the related technique 1 shown in FIG. 1A, in this embodiment, the round trip latency from the global switch / directory control unit 150 to the memory / directory control unit 120 is shortened.

  The second effect is that, compared with the case where the directory is managed by only one place of the global switch / directory control unit, the processor that issues the request is in its own node and the processor that holds the valid cache data is It is possible to shorten the latency when the node is not present or within the own node. This is because the directory is also provided in the memory so that the snoop process for the request issued from the processor in the own node can be performed without using the global switch / directory control unit.

  As an example of the second effect, FIG. 8B shows a path from issuing a request to receiving data in a case where a request for the memory 140 is issued from the processor 102 and there is valid data in the cache of the processor 101. When a request is issued from the processor 102, the request enters the memory directory control unit 120 from the local switch 110 in the node 100. The memory / directory control unit 120 indexes the directory 130 simultaneously with issuing a request to the memory 140, and issues a snoop to the processor 101 holding valid data in the cache. The snoop enters the processor 101 through the local switch 110.

  If the processor 101 that receives the snoop actually holds valid cache data, the cache data is transferred to the processor 102 that issued the request, and a response is returned to the memory / directory control unit 120. . The cache data is transferred to the processor 102 through the local switch 110. The latency is from the request issuance to the data reception, and the request to the memory 140 and the response from the processor 101 do not appear to be a latency and are not displayed on the route.

  Compared with the path in the related technology 2 shown in FIG. 2B, in this embodiment, the round trip latency from the local switch 110 to the global switch / directory control unit 150 is shortened.

It is a figure explaining the path | route of the request processing from the other node in related technology 1. It is a figure explaining the path | route of the request process in the own node in related technology 1. FIG. It is a figure explaining the path | route of the request process from the other node in related technology 2. It is a figure explaining the path | route of the request processing in the own node in related technology 2. FIG. It is explanatory drawing of the problem in the related technology 3. FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention. FIG. It is a block diagram of the global switch directory control part in this Embodiment. It is a 1st flowchart explaining operation | movement of the global switch directory control part in this Embodiment. It is a 2nd flowchart explaining operation | movement of the global switch directory control part in this Embodiment. It is a figure explaining the path | route of the request process from the other node in this Embodiment. It is a figure explaining the path | route of the request processing in the own node in this Embodiment.

Explanation of symbols

100, 100a, 100b, 100c, 200, 200a, 200b, 300, 300a, 300b Nodes 101, 102, 201, 202, 301, 302 Processors 110, 210, 310 Local switches 120, 220, 320 Memory directory control unit 130 , 160, 230, 260, 330, 360 Directory 140, 240, 340 Memory 150, 190, 250, 290, 350, 390 Global switch / directory control unit 151, 158 Arbitration circuit 152 Address match circuit 153 Cancel determination circuit 154 Control register 155 Message storage buffer 156 Retransmission buffer 157 Message issuing / generating circuit 170, 270, 370 Global switch 180, 280, 380 Memory control unit

Claims (15)

A first processor belonging to its own node;
A memory shared by the first processor and a second processor belonging to another node;
A first directory for managing the cache state of the node;
A second directory for managing the cache state of the other node;
A first directory control unit that processes the request issued in the own node and receives the first request designating the address of the memory, and indexes the first directory;
When processing a request issued from the other node and receiving a second request specifying the address of the memory, when indexing the second directory and processing the second request A latency shortening method comprising: a second directory control unit that performs predetermined control to ensure coherency by checking whether or not there is an address conflict when another request or snoop is received. The second directory control unit
Belongs to the own node,
The first directory is
The latency shortening method according to claim 1, wherein the cache state of the second directory control unit is managed as one of the cache states of the own node. The first directory control unit
When processing the first request, the first directory is indexed, and if the cache of the second directory control unit is valid, a first snoop is issued to the second directory control unit And
The second directory control unit
When processing the second request, when issuing the third request to the first directory control unit, and after issuing the third request, the first snoop is received. When the address of the third request and the address of the first snoop are in conflict, the first snoop process is started and terminated before receiving a reply to the third request. The latency shortening method according to claim 2. The second directory control unit
When starting the processing of the first snoop, when the second directory is indexed, the cache is valid, and the second snoop is issued to the other node, the third request is issued. The latency shortening method according to claim 3, wherein a cancellation notification for canceling is issued to the first directory control unit. The second directory control unit
When starting the first snoop process, if the second snoop has been issued, it waits to receive a response to the second snoop, and then the first snoop process The latency shortening method according to claim 4, wherein the cancel notification is issued only when a response to the second snoop indicates that the cache data has actually been transferred. The second directory control unit
The latency shortening method according to claim 5, wherein the third request is issued with the issuer as oneself. The second directory control unit
When processing the second request, if another request with an address conflict is received, the request is resent to the issuer of the other request without processing the other request. The latency shortening method according to claim 6. The first directory control unit
A memory control unit for controlling access to the memory;
The second directory control unit
The latency shortening method according to claim 7, further comprising a global switch that transmits and receives a message including a request, a reply, a snoop, and a response to and from the other node. Providing a first directory for managing the cache state of the own node;
Providing a second directory for managing the cache state of other nodes;
Providing a first directory control for indexing the first directory;
Providing a second directory control for indexing the second directory;
When a first request specifying an address of a memory shared by a first processor belonging to the own node and a second processor belonging to the other node is issued in the own node, the Issuing a second request to the memory by the first directory control unit, indexing the first directory, and processing the first request;
When a third request specifying the address of the memory is issued from the other node, the second directory control unit issues a fourth request to the memory and indexes the second directory. In addition, when another request or snoop is received, the third request is processed by performing predetermined control for ensuring coherency by checking whether or not the address conflicts. Yes Latency reduction method. Setting up the first directory
The latency shortening method according to claim 9, further comprising providing a first directory for managing a cache state of the second directory control unit as one of the cache states of the own node. Processing the first request includes
Indexing the first directory and, if the cache of the second directory control is valid, issuing a first snoop to the second directory control;
Processing the third request includes
After issuing the fourth request, when the first snoop is received by the second directory control unit, the address of the fourth request conflicts with the address of the first snoop. The latency shortening method according to claim 10, further comprising: starting and ending the first snoop process before receiving a reply to the fourth request. Processing the third request includes
When starting the processing of the first snoop, when the second directory is indexed for the third request, the cache is valid, and the second snoop is issued to the other node The latency shortening method according to claim 11, further comprising: issuing a cancel notification for canceling the fourth request. Processing the third request includes
When starting the first snoop process, if the second snoop has been issued, it waits to receive a response to the second snoop, and then the first snoop process The latency shortening method according to claim 12, further comprising issuing the cancellation notification only when a response to the second snoop indicates that the cache data has actually been transferred. Processing the third request includes
The latency shortening method according to claim 13, comprising rewriting the issuer from another node to the own node and issuing the fourth request. Processing the third request includes
The latency shortening method according to claim 14, further comprising: instructing a re-transmission of the request to an issuer of the other request without processing the other request when receiving another request having an address conflict. .

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