JP2009245025A - Key detection device and key detection method, and portable electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly perform key detection. <P>SOLUTION: A key detection device includes voltage holding circuits (RC11 to RC33) for holding a prescribed voltage for a detection line which is charged from an output line for each combination of output lines and detection lines; and a plurality of key switches (S11 to S33) connected to the voltage holding circuits for permitting charging to the voltage holding circuit in such a state that any key switch operation is not performed, and for inhibiting charging to the voltage holding circuit in such a state that any key switch operation is performed. When the voltage holding state of the voltage holding circuit varies due to presence/no presence of the operation of the key switch, a control circuit 10 detects variation of the voltage in the detection line to detect whether the operation of the key switch is performed or not. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a key detection device, a key detection method, and a portable electronic device.

  FIG. 7 is a diagram showing a configuration of a conventional key detection device.

  As shown in FIG. 7, the key detection device is connected to the key matrix 3 in addition to the microcomputer (microcomputer, CPU 20), and the input / output port 1 that performs key scanning under the control of the CPU 20, and the input / output port 1 is provided with an input port 8 for acquiring each scan result, and a pull-down resistor 2 for fixing the input / output port 1 to the “Low” level when the key is not pressed.

The input / output port 1 includes a plurality of unit circuits composed of two buffers whose outputs are the outputs of each other, and these buffers are controlled so that only one buffer operates in accordance with input / output.
In addition, here, a 4 × 4 key matrix 3 is illustrated, and in order to detect a total of 16 keys 31, the CPU 20 has four ports on the output side (input / output port 1) and ports on the input side. (Input port 8) Scanning is performed using a total of four ports, four, and the pressed key 31 is detected.
As described above, when the key detection device is configured to detect N keys, the CPU 20 needs to allocate 2 × √N ports, which is a major cause of squeezing the number of ports of the CPU 20. .

  In order to reduce the number of ports described above, conventionally, for example, as shown in FIG. 8, there is known a key matrix device that reduces the total number of ports by sharing an output side port and an input side port. (For example, refer to Patent Document 1).

According to this example, when a total of 16 keys (key matrix 3) are to be detected in the same manner as described above, four ports on the output side and four ports on the input side are shared, so a total of four keys. It can be realized with the port. In this way, the same number of keys can be detected by half of the ports.
In FIG. 8, the capacitor 10 is controlled by one output port, and is used for storing the potential of the key matrix 3. Reference numerals 6 and 9 denote diodes for preventing reverse current.
Japanese Patent Laid-Open No. 7-152468 (paragraph [0014], FIG. 3)

  However, according to the technique disclosed in Patent Document 1 described above, the capacitor 10 is required, and the discharge time of the capacitor described above is indispensable for determining the operation key. Therefore, key detection cannot be performed at high speed. .

  An object of the present invention is to provide a key detection device, a key detection method, and a portable electronic device that can perform key detection at high speed.

  A key detection device according to a first aspect of the present invention includes a key matrix including a plurality of output lines, a plurality of detection lines, and a plurality of key switches connected to the intersections of the output lines and the detection lines. A control circuit for determining an operation state of the key switch based on a voltage state of each detection line in a voltage application state to the output line; and for each combination of the output line and the detection line, from the output line A voltage holding circuit for holding a predetermined voltage with respect to the detection line to be charged, and the plurality of key switches permit charging the voltage holding circuit in a state where the key switch is not operated, Each of the voltage holding circuits is connected to each of the voltage holding circuits so that the voltage holding circuit cannot be charged when the key switch is operated. The voltage change of the voltage holding state in the voltage holding circuit with and without the operation of the key switch, by detecting for each of the detection line, detects the presence or absence of an operation of each of the key switches.

  Preferably, the output line is connected to each of the plurality of output ports of the control circuit, and a detection voltage is sequentially applied from each of the output ports in a first period, and the detection line changes the voltage state to the first state. The control circuit is connected to a plurality of input ports that are sequentially determined in a second cycle within one cycle, and the control circuit detects each voltage state of the detection line every time a voltage is applied to one of the output lines. Then, it is determined whether or not each key switch is operated.

  Preferably, a line switching circuit is provided between each output line and the output port, and switches a line that opens another output line from the output port when a voltage is applied to one of the plurality of output lines. including.

  Preferably, when the voltage is applied to one output line, the control circuit opens the connection to the output port by the line switching circuit except for the output line to which the voltage is applied, and charging is performed by the output line. After completion, the voltage state in each detection line is determined while maintaining the state of the line switching circuit.

  Preferably, the output line and the detection line are connected to ports that can switch between output and detection, respectively, and one output line is charged until the voltage holding circuit is charged within the first period. The voltage is applied, and the control circuit releases the voltage application after the charging is completed, and then detects a voltage fluctuation in the detection line.

  Preferably, the voltage holding by the voltage holding circuit has a time constant sufficient to hold the second period.

  Preferably, the voltage holding circuit includes a resistor and a capacitor. One end of the resistor is connected to the output line, the other end is connected to the capacitor, the other end of the capacitor is grounded, and the key switch is connected to the capacitor. This is a switch that bypasses and grounds.

  According to a second aspect of the present invention, there is provided a plurality of output lines, a plurality of detection lines, a plurality of key switches provided at locations where the output lines and the detection lines intersect, and a voltage applied to the output lines. A key detection method in a key matrix circuit comprising a chargeable voltage holding circuit, comprising a key detection step for performing key detection determination for each output line, wherein the key detection step in the nth output line includes: Applying voltage to the nth output line and charging the voltage holding circuit, stopping voltage application to the nth output line, and determining the voltage state in each detection line A determination step for determining.

  A display device according to a third aspect of the present invention includes an operation unit, a display unit, and a control unit, and the operation unit includes a plurality of output lines, a plurality of detection lines, the output lines, and the detection. A key matrix circuit including a plurality of key switches provided at the intersections of the lines and a voltage holding circuit that can be charged by a voltage applied to the output line, and the control unit includes n (an arbitrary integer) ) During the key detection process in the nth output line, the voltage holding circuit is charged by applying a voltage to the nth output line, the voltage application to the nth output line is stopped, and each detection line is stopped. The operation of the key switch is recognized and the operation of the key switch is recognized, and the type of the recognized key switch is displayed on the display unit.

  According to the present invention, key detection can be performed at high speed.

FIG. 1 is a diagram illustrating an example of a circuit configuration of a key detection device according to an embodiment of the present invention.
Here, a 3 × 3 key matrix 30 is illustrated.

The key matrix 30 includes a plurality of output lines Row1 to Row3, a plurality of detection lines P1 to P3, and a plurality of key switches S11 to S33 connected at the intersections of the output lines Row1 to Row3 and the detection lines P1 to P3. It is comprised by.
Further, the control circuit 100 (CPU) connected to the key matrix 30 is based on the voltage states of the detection lines P1 to P3 in the voltage application state to the output lines Row1 to Row3 via the input / output ports 11 to 13, respectively. The operation state of the key switches S11 to S33 is determined.

  A feature is that voltage detection circuits RC11 to RC33 and key switches S11 to S33 are provided for each combination of the output lines Row1 to Row3 and the detection lines P1 to P3 constituting the key matrix 30.

The voltage detection circuits RC11 to RC33 are configured by time constant circuits each including a resistor R and a capacitor C, which hold predetermined voltages for the detection lines P1 to P3 charged from the output lines Row1 to Row3. Each of key switches S11-S33 is connected in parallel.
The key switches S11 to S33 permit charging of the voltage holding circuits RC11 to RC33 when the key switches S11 to S33 are not operated, and to the voltage holding circuits RC11 to RC33 when the key switches S11 to S33 are operated. Disable charging. When the voltage holding state of the voltage holding circuits RC11 to RC33 fluctuates depending on whether or not the key switches S11 to S33 are operated, the control circuit 100 detects the voltage fluctuations in the detection lines P1 to P3, thereby detecting the key switches S11 to S33. Detect the presence or absence of operation.

  The voltage holding circuits RC11 to RC13 are connected to the detection line P1 through the resistor R1 and the backflow prevention diodes D11 to D13, respectively. The voltage holding circuits RC21 to RC23 are connected to the detection line P2 via the resistor R2 and the backflow prevention diodes D21 to D23, respectively. The voltage holding circuits RC31 to RC33 are connected to the detection line P3 via the resistor R3 and the backflow prevention diodes D31 to D33.

  A further feature is that a line switching circuit 40 (Srow) is added. The line switching circuit 40 is provided between each of the output lines Row1 to Row3 and the detection lines P1 to P3. When a voltage is applied to one of the plurality of output lines Row1 to Row3, the other output line is connected to the output port ( Release from detection lines P1-P3).

  When a voltage is applied to one output line, the control circuit 100 (CPU) opens the connection with the output ports (detection lines P1 to P3) by the line switching circuit 40 except for the output line to which the voltage is applied. After the charging is completed by Row1 to Row3, the voltage state in each of the detection lines P1 to P3 is determined while the state of the line switching circuit 40 is maintained.

With the above configuration, it is possible to detect all key pressing patterns without erroneous detection of the keys S11 to S33.
In addition, the pull-down resistor is not required, and the capacitors constituting the voltage holding circuits RC11 to RC33 are charged and discharged through the resistors connected to the key switches S11 to S33. Further, since the current with respect to the ground flows only when the key switches S11 to S33 are pressed, the resistance value can be reduced. Therefore, the time constant due to the capacitor and the resistance can be reduced, and the key matrix detection with quick response is performed.

  FIG. 2 is a timing chart showing a key scan operation of the key detection apparatus according to the embodiment of the present invention.

Here, the control (Cont) signal generated by the control circuit 100 (CPU) and the signal waveforms of the ports P1 to P3 are shown in the scan order of Row1, Row2, and Row3.
Hereinafter, the operation of the key detection apparatus according to the embodiment of the present invention shown in FIG. 1 will be described in detail with reference to the timing chart of FIG.

The input / output ports 11 to 13 and the line switching circuit 40 (Srow) are all controlled by the Cont signal generated by the control circuit 40 (CPU), and the output port is set when the Cont signal is at the “Low” level. Further, the line switching circuit 40 (Srow) that performs scanning is turned on.
Before the key scan is started, the outputs P1 to P3 of all the input / output ports 11 to 13 are at the “Low” level. Now, in order to scan Row1, only the input / output port 11 is set to "High" level and only the detection line P1 is enabled. At this time, the control circuit 100 (CPU) continuously outputs the output level “High” to the input / output port 11 until the charging voltages of the capacitors of the voltage holding circuits RC11, RC21, and RC31 are substantially saturated (FIG. 2, A: charging cycle). Thereafter, the Cont signal is switched to the “High” level, and the input / output ports 11 to 13 are switched to the input setting. In this state, the control circuit 100 (CPU) sequentially reads the states of the input / output ports P1 to P3 (B: detection cycle in FIG. 5), and detects ON / OFF of the key switches S11, S21, and S31.

  Next, the control circuit 100 (CPU) scans Row 2 by setting the input / output port 12 to “High” level and enabling only the detection line P 2. At this time, the control circuit 100 (CPU) outputs “High” level output to the input / output port 12 until the charging voltage of each capacitor of the voltage holding circuits RC12, RC22, and RC32 is almost saturated as in the case of the scan of Row1. Then, the Cont signal is switched to the “High” level, and the input / output ports 11 to 13 are switched to the input setting. In this state, the control circuit 100 (CPU) sequentially reads the states of the detection lines P1 to P3 and detects ON / OFF of the key switches S12, S22, and S32.

Next, the control circuit 100 (CPU) scans Row 3 by setting the input / output port 13 to “High” level and enabling only the detection line P 3.
At this time, the control circuit 100 (CPU) continues the “High” level output to the input / output port 13 until the charging voltages of the capacitors of the voltage holding circuits RC13, RC23, and RC33 are almost saturated, and then outputs the Cont signal. The input / output ports 11 to 13 are switched to the input setting by switching to the “High” level. In this state, the control circuit 100 (CPU) reads the states of the detection lines P1 to P3 and detects ON / OFF of the key switches S13, S23, and S33.
Then, the scan operation is continued by returning to the Row 1 scan.

That is, when the control circuit 100 (CPU) applies a voltage to one output line (Row 1 to Row 3), the line switching circuit 40 connects to the ports (detection lines P1 to P3) except for the output line to which the voltage is applied. After the charging is completed by the output lines Row1 to Row3, the voltage state in each of the detection lines P1 to P3 is determined while maintaining the state of the line switching circuit 40.
At this time, the output lines Row1 to Row3 and the detection lines P1 to P3 are connected to the input / output ports 11 to 13 that can switch the detection of the outputs, respectively, and within the first period (A: charging period), the voltage holding circuit. A voltage is applied to one output port until the RC11 to RC33 (capacitors thereof) are charged, the voltage application is released after completion of the application for a time to complete charging, and the detection line at that time A voltage state is determined. At this time, voltage holding by the voltage holding circuits RC11 to RC33 has a time constant that can sufficiently hold the second cycle (B: open cycle).

  As described above, according to the key detection device according to the embodiment of the present invention, the capacitors (voltage holding circuits RC11 to RC33) for holding the voltage are provided for each of the key switches S11 to S33, so that each output line is provided. A common capacitor is not provided. As a result, even if the output port is switched, it is not necessary to wait for the time until the capacitor discharge is completed, so that the key response is accelerated. Further, when the applied voltage for each output line is switched, the line is physically separated from the output port, thereby making it possible to cope with erroneous recognition due to multiple pressing of the key switch.

  Hereinafter, the reason why the key detection device according to the embodiment of the present invention described above can cope with misrecognition due to multiple pressing of the key switch and the key response is accelerated will be described.

In the key detection device shown in FIG. 3, for example, when a key indicated by three circles is pressed, it is erroneously detected that the key indicated by a square is pressed. This is a problem common to a key detection device using 2 × √N ports as shown in FIG. 6 as a conventional example, and in order to avoid this problem, it is enlarged and shown in a circle. Such a diode 32 for preventing reverse current inserted in series with the key 31 is required.
However, since the diode 32 needs to be inserted in series with the key 31, it is arranged in the immediate vicinity of each key. Therefore, the degree of freedom is hindered in arranging and wiring the key matrix 3. It becomes a big factor.

  In the key detection device shown in FIG. 4, for example, when one of the upper left circle and one of the three keys indicated by other oval frames are pressed, It is erroneously detected that the key indicated by is pressed. This occurs because the input side of the key matrix 3 and the output side of the key matrix 3 are connected in the forward direction of the diode, and can be said to be a false detection characteristic of this key detection device.

Further, as in the key detection device shown in FIG. 5, when any key indicated by a circle is pressed, the capacitor 10 indicated by the circle is charged and the voltage is taken into the input port 1. Is detected. The electric charge charged in the capacitor 10 is discharged according to the time constant with the pull-up resistor 2 indicated by a circle.
Therefore, it is necessary to discharge the capacitor 10 after scanning one column and before scanning the next column, and it is difficult to detect a key with good responsiveness. On the other hand, if the value of the pull-up resistor 2 is reduced in order to reduce this time constant, the current consumption when “High” is output from the output port increases.

  Compared with the examples shown in FIGS. 3 to 5, according to the state of implementation of the present invention, the key detection circuit described above improves the key response while reducing the number of ports. A remarkable effect can be obtained when used in a portable electronic device.

  FIG. 6 is a block diagram showing an example of the internal configuration of the mobile phone described above. In FIG. 6, the mobile phone uses the control unit 27 as a control center, and each of the communication unit 21, the operation unit 22, the voice input / output unit 23, the display unit 24, the imaging unit 25, the storage unit 26, and the control unit 27 has an address. , Data and control lines are commonly connected to a system bus 30 composed of a plurality of lines.

The communication unit 21 captures a wireless communication system, performs wireless communication with a base station (not shown) connected to the communication network, and transmits and receives various data.
The various data includes voice data at the time of voice call, mail data at the time of mail transmission / reception, web page data at the time of browsing the web, and the like.

The operation unit 22 includes a key switch to which various functions are assigned such as a power key, a call key, a numeric key, a character key, a direction key (left / right / up / down), a determination key, a call key, and a function key. . When these key switches are operated by the operator, the operation unit 22 generates a signal corresponding to the operation content and outputs the signal to the control unit 27 as an instruction from the operator.
The operation unit 22 includes the key detection device shown in FIG. 1. When a key press is detected here, the operation unit 22 is converted into a key code under the control of the control unit 27, and the recognized data is a display unit described later. 24.

  The audio input / output unit 23 performs input / output processing of an audio signal output from a speaker or an audio signal input from a microphone. That is, the sound input from the microphone is amplified, subjected to analog-to-digital conversion, further subjected to signal processing such as encoding, converted into digital sound data, and output to the control unit 27. In addition, the audio data generated by the control unit 27 is subjected to signal processing such as decoding, digital-analog conversion, amplification, and the like, converted into an analog audio signal, and output to a speaker.

The display unit 24 is configured by arranging a large number of pixels (a combination of light emitting elements of a plurality of colors) vertically and horizontally, for example, an LCD (Liquid Crystal Display Device) or an organic EL (Electro-Luminescence).
And displays an image corresponding to the display data generated by the control unit 27 and written in a predetermined area (VRAM area) of the storage unit 26.

  The imaging unit 25 is a camera configured by a photoelectric conversion element such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a control circuit thereof, and the like.

The storage unit 26 stores various data used for various processes of the mobile phone.
The storage unit 26 is, for example, a computer program (OS (Operating System) or application program) executed by the control unit 27, an image file captured by the imaging unit 15, an external unit (not shown) via the communication unit 21. A download file acquired from the connection server is stored.
The storage unit 26 also has an address book for managing personal information such as the telephone number and e-mail address of the communication partner, a voice file for playing ringtones and alarm sounds, an image file for a standby screen, and various settings. Data, temporary data used in the process of the program, and the like are also stored.
The storage unit 26 includes, for example, a nonvolatile storage device (nonvolatile semiconductor memory, hard disk device, optical disk device, etc.), a random accessible storage device (eg, SRAM, DRAM), or the like.

The control unit 27 comprehensively controls the overall operation of the mobile phone.
That is, the control unit 27 performs various operations of the mobile phone (voice calls performed via a circuit switching network, creation and transmission / reception of e-mail, browsing of the Internet Web (World Wide Web) site, etc.). The operation of each block described above (transmission / reception of signals in the communication unit 21, audio input / output in the audio input / output unit 23, image display in the display unit 24, Control the imaging process).
And the control part 27 has the control part 100 of the key detection apparatus shown in FIG. That is, it is possible to detect the operation of all the key switches by the method shown in FIG. Further, the control unit 27 performs arithmetic processing in accordance with the detected key operation and outputs the result to the display unit 24.
The control unit 27 includes a computer (microprocessor) that executes processing based on a program stored in the storage unit 27, and executes the above-described control according to a procedure instructed in this program. That is, the control unit 27 sequentially reads instruction codes from programs such as the OS and application programs stored in the storage unit 26 and executes processing.
In the example of “B: detection cycle” in FIG. 2, the reading of the input / output ports P1 to P3 is sequentially performed. However, if the configuration is such that the states of all the input / output ports can be read at a time, ˜P3 may not be read sequentially.

In the above-described mobile phone, scanning of the key matrix assigned to the operation unit 22 and determination of the key switch are performed by the CPU included in the control unit 27. Alternatively, the load is distributed and incorporated in the operation unit 22. The detection result may be received by the CPU, and the control unit 27 may receive the detection result.
Further, although only a mobile phone is illustrated as a portable electronic device, the present invention is not limited to a mobile phone, and can be similarly applied to a PDA (Personal Digital Assistants), a game machine, and the like.

As described above, according to the key detection device of the embodiment of the present invention, by sharing the output side port and the input side port, it is possible to press the key multiple times while maintaining the reduction in the total number of ports used. Can be detected.
Further, by providing each key with a voltage holding circuit, it becomes possible to detect all combinations of key presses. Further, in order to avoid erroneous detection due to multiple pressing of the key, conventionally, a reverse current prevention diode inserted in series is required, and a reverse current prevention diode is inserted in series with the key, and the key matrix. This is a major factor that hinders the degree of freedom in placing and wiring, but it is unnecessary here, so it contributes to a reduction in the number of parts and can improve key response at low cost. .

  Also, conventionally, the charge charged in the capacitor is discharged only by the pull-down resistor, and since the resistance value cannot be reduced from the viewpoint of current consumption, it has a large time constant, and after scanning one column, the next column The key detection device according to the embodiment of the present invention has a pull-down resistor, whereas it is difficult to detect the key with good responsiveness. The capacitor is charged and discharged through a resistor connected to the key switch, and the current to the ground flows only when the key switch is pressed, so that the resistance value can be reduced. The time constant due to the resistance can be reduced, and key matrix detection with a quick response is possible. In this way, the number of parts can be reduced, and the key response can be improved at a low cost, so that a remarkable effect can be obtained when used for portable electronic devices such as a mobile phone aiming at a reduction in thickness and cost.

It is a figure which shows an example of the circuit structure of the key detection apparatus which concerns on embodiment of this invention. It is a timing chart which shows the key scan operation | movement of the key detection apparatus which concerns on embodiment of this invention. It is the figure shown in order to demonstrate operation | movement (1) of a key detection apparatus. It is the figure shown in order to demonstrate operation | movement (2) of a key detection apparatus. It is the figure shown in order to demonstrate operation | movement (3) of a key detection apparatus. It is a block diagram which shows an example of the internal structure of the portable electronic device which concerns on embodiment of this invention. It is a figure which shows an example of the circuit structure of the conventional key detection apparatus. It is a figure which shows an example of the other circuit structure of the conventional key detection apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11-13 ... Input / output port, 30 ... Key matrix (Voltage holding circuit RC11-33, Key switch S11-S33), 40 ... Line switching circuit, 100 ... Control circuit (CPU), 22 ... Operation part, 27 ... Control part .

Claims (9)

A key matrix including a plurality of output lines, a plurality of detection lines, and a plurality of key switches connected to the intersections of the output lines and the detection lines;
A control circuit for determining an operation state of the key switch based on a voltage state of each detection line in a voltage application state to the output line;
A voltage holding circuit for holding a predetermined voltage for the detection line charged from the output line for each combination of the output line and the detection line;
The plurality of key switches are
When the key switch is not operated, charging to the voltage holding circuit is permitted, and when the key switch is operated, charging to the voltage holding circuit is disabled. And
The control circuit includes:
A key detection device that detects whether or not each key switch is operated by detecting, for each detection line, voltage fluctuation in a voltage holding state in the voltage holding circuit depending on whether or not the key switch is operated. . The output lines are respectively connected to a plurality of output ports of the control circuit, and a detection voltage is sequentially applied from each of the output ports in a first period,
The detection lines are respectively connected to a plurality of input ports that sequentially determine the voltage state in a second period within the first period,
The control circuit includes:
2. The key detection device according to claim 1, wherein each time a voltage is applied to one of the output lines, the voltage state of the detection line is detected to determine whether or not each of the key switches is operated. . A line switching circuit that is provided between each output line and the output port, and switches a line that opens another output line from the output port when a voltage is applied to one of the plurality of output lines. The key detection device according to claim 2, wherein the key detection device is a key detection device. The control circuit includes:
When a voltage is applied to one output line, the line switching circuit opens the connection to the output port except for the output line to which the voltage is applied, and the state of the line switching circuit after charging is completed by the output line The key detection device according to claim 3, wherein the voltage state in each of the detection lines is determined while maintaining the key. The output line and the detection line are connected to ports that can switch between output and detection, respectively, and a voltage is applied to one output line until the voltage holding circuit is charged within the first period. And
The control circuit includes:
The key detection device according to any one of claims 1 to 4, wherein the voltage application is released after the charging is completed, and then a voltage fluctuation in the detection line is detected. The key detection apparatus according to claim 2, wherein the voltage holding by the voltage holding circuit has a time constant sufficient to hold the second period. The voltage holding circuit includes a resistor and a capacitor,
One end of the resistor is connected to the output line, the other end is connected to a capacitor, the other end of the capacitor is grounded,
The key detection device according to any one of claims 1 to 6, wherein the key switch is a switch that bypasses the capacitor and grounds the capacitor. A plurality of output lines; a plurality of detection lines; a plurality of key switches provided at locations where the output lines and the detection lines intersect; and a voltage holding circuit that can be charged by a voltage applied to the output lines. In the key detection method in the key matrix circuit,
A key detection step for performing key detection determination for each output line;
The key detection step in the nth output line includes applying a voltage to the nth output line and charging the voltage holding circuit;
A key detection method comprising: determining a voltage state in each detection line by stopping voltage application to the nth output line. An operation unit;
A display unit;
A control unit,
The operation unit is
A plurality of output lines; a plurality of detection lines; a plurality of key switches provided at locations where the output lines and the detection lines intersect; and a voltage holding circuit that can be charged by a voltage applied to the output lines. A key matrix circuit,
The controller is
During key detection processing on the nth (any integer) output line, the voltage holding circuit is charged by applying a voltage to the nth output line, and the voltage application to the nth output line is stopped. A portable electronic device characterized by determining a voltage state in each detection line, recognizing an operation of a key switch, and displaying the type of the recognized key switch on the display unit.

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