JP2009238935A - Optical detecting circuit and optical detector, device and system using the same, and control method for bias power source - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: an optical detecting circuit and an optical detector which control an afterpulse of an APD afterward and detect photons in high repetitive cycles; a device and a system using the same; and a control method for a bias power source. <P>SOLUTION: The optical detecting circuit includes the APD 101, a DC bias power circuit 107 which outputs a DC supply voltage VB1, a gate pulse driver circuit 106 which generates a gate pulse GP1, a superposing circuit 181 which superposes the gate pulse GP1 on the DC supply voltage, an afterpulse control circuit 104 which generates an afterpulse suppression signal AC1 lowering a bias voltage applied to the APD 1 for a predetermined time, and a superposing circuit 182 which superposes the afterpulse suppression signal AC1 on a DC supply voltage VB2. In the APD 1, a DC supply voltage VB3 generated by superposing the gate pulse GP1 and afterpulse suppression signal AC1 one over the other is applied to one electrode and an optical detection signal S2 is output from the other electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a single photon detector, a weak light detector, and a control circuit thereof, and more particularly, to a blanking control circuit for reducing afterpulses and a control system thereof.

  Single photon detectors are indispensable devices in quantum information technology including quantum cryptography. In particular, a photon detector using an avalanche photo diode (APD) can be operated with Peltier cooling, and is implemented from the viewpoint of relatively low bias voltage, high detection efficiency, and a miniaturizable structure. Is considered the best.

  In a photon detector using an APD, by applying a bias voltage exceeding the breakdown voltage to the APD for a short time and increasing the avalanche multiplication factor, an external circuit triggers only one carrier generated from a single photon. It is amplified until it can be detected (see Non-Patent Document 1).

  A method of receiving a signal by applying a bias voltage exceeding the breakdown voltage to the APD is called a “Geiger mode”, and in particular, generating a short Geiger mode by a pulse in the APD is called a “gate mode”. . For example, the avalanche multiplication factor in the gate mode is a value exceeding 1000 to 100,000 times.

  When single-photon transmission is performed in the 1.55 μm band where the transmission loss of the optical fiber is minimum, it is common to use an InGaAs-based APD having reception sensitivity in the 1.55 μm band. In photon detection using such InGaAs-APD (hereinafter simply referred to as APD), continuous Geiger mode cannot be maintained due to the high dark current level of APD. It has become.

  Note that a state where the multiplication factor is about 10 to 100 in a bias state equal to or lower than a breakdown voltage used in normal optical communication or the like with respect to the Geiger mode is referred to as a “normal mode” in the following description.

  FIG. 18 is a time chart showing the principle of the gate mode. In the gate mode, the APD bias is set to the Geiger mode for a very short time in synchronization with the photon signal. At the same time, if a photon is incident, the photon is detected, and if no photon is incident, the normal mode is restored.

For example, in the gate mode with a gate time of several nsec or less, the dark current carriers generated during that time can be considered very small, so photons can be detected with a sufficient signal-to-noise ratio. Is possible. Noise generated by dark current carriers is called “dark count” and is generated with a constant probability with respect to the gate time (almost constant probability regardless of the gate time).
Since the dark count originates from the dark current of the APD, it can be suppressed by cooling the APD element to reduce the dark current. In general, in photon detection with APD, a Peltier device or a refrigerator is used as a cooling means.

  When the gate mode is used, the differential component of the gate pulse is output from the APD. This is called “charge pulse” and needs to be removed. The removal of the charge pulse is disclosed in Patent Documents 1, 2, and 3.

  When the photon detector is applied to an information communication device such as a quantum cryptography system, the generation of noise is directly linked to a decrease in the amount of information, so that reduction is required. The noise generated from the APD photon detector in the gate mode is composed of two components, the dark count and the after pulse.

  FIG. 19 shows an example of APD noise characteristics. The horizontal axis represents the gate pulse interval, and the vertical axis represents the noise generation probability per gate pulse. The after pulse probability (Probability of After Pulse: PAP) is the probability of occurrence of breakdown in the next gate pulse following the broken gate pulse. The dark count probability (Probability of DarK count: PDK) is a constant occurrence probability regardless of the blanking time, whereas the after pulse probability decreases as the gate pulse interval increases.

The after pulse is a noise phenomenon in which when an APD breaks down in a certain gate pulse, breakdown occurs with a certain probability even though no photon is incident on the subsequent gate pulse.
APD breakdown that causes afterpulses can occur either by photon detection or by dark count. This after-pulse is a phenomenon in which a large amount of carriers generated by breakdown continue to remain inside the crystal constituting the APD element and are re-multiplied by application of the next gate pulse (see Non-Patent Document 2).

In order to suppress the after pulse, as shown in the time chart of FIG. 20, after the breakdown, it is necessary to stop the application of the gate pulse for a certain time and perform control to reduce the after pulse probability (Non-Patent Document 3). reference). Or, the after-pulse probability is always 1 or less, and even if repeated after-pulses occur, it is necessary to mask the APD output signal for a certain period of time and ignore the signal detection by using the fact that it stops in a finite time. Yes (see Non-Patent Document 4).
This gate pulse stop time and mask time are called “blanking time”. The blanking time is set to 100 nsec to several tens of μsec depending on APD varieties and individual differences (see Non-Patent Documents 4 and 5).

During blanking, since the gate pulse stops and photons cannot be detected, shortening of the blanking time is required to avoid a decrease in the amount of information received by photon detection. The blanking time is determined by the carrier lifetime remaining inside the APD, and its value strongly depends on the physical properties of the device material. Therefore, in order to shorten the blanking time, a method of improving the APD element itself or a method of selecting a short blanking time by using a difference in blanking time due to a variety or individual difference was used. .
JP 2006-284202 A (FIGS. 4 and 5, paragraphs 0051 to 0062) JP 2003-243691 A (FIGS. 1 and 2, claim 1, paragraph 0011) JP-A-2005-114712 (FIGS. 1 and 2, claim 3, paragraph 0021) BFLevine and CGBethea JCCampbell, Near room temperature 1.3um single photon counting with a InGaAs avalanche photodiode, Eectronics Letters, vol.20 No.14, 1984, pp596, 1st column lines 18-27 Sergio Cova, Senior, A. Lacaita, and G. Ripamonti, Trapping Phenomena in Avalanche Photodiodes on Nanosecond Scale, ELECTRON DEVICE LETTERS, 1991, VOL. 12, NO. 12, pp685-687 A high-performance integrated single-photon detector for telecom wavelengths, DONALD S. BETHUNE, WILLIAM P. RISK and GARY W. PABST, Journal of modern optics, 15 june-10 july 2004 vol.51, no.9-10, 1359 -1368, 1360 Photon counting for quantum key distribution with Peltier cooled InGaAs / InP APD's, Damien Stucki, Gregoire Ribordy, Andre Stefanov, Hugo Zbinden, John G. Rarity, Tom Wall, http://arxiv.org/PS_cache/quant-ph/pdf/ 0106 / 0106007v1.pdf Accurate Evaluation of APD Noise Characteristics for Quantum Cryptosystems, Seigo Takahashi, Takeshi Nakata, Akio Tajima and Akihisa Tomita, The 11th Optoelectronics & Communications Conf (OECC2006) 4B2-6, Figure 4

  However, the above method for shortening the blanking time has the following problems.

  The first problem is that the blanking time is determined in the APD element manufacturing stage and cannot be controlled afterwards. This means that the reduction rate of the after-pulse probability depends on the APD crystal and device structure and cannot be controlled by an external circuit. That is, in the photon detection circuit as shown in FIG. 21, since the blanking time could not be shortened systematically, a high-performance (short blanking time) APD element is needed to shorten the blanking time. There was no choice but to use.

  The second problem is that the effect of improving the gate repetition frequency is not sufficiently reflected in the amount of information obtained by photon detection. This is because the time to stop the photon detection operation becomes dominant due to the blanking for a long time, and the generation time of the quantum key decreases when the photon detection circuit is applied to the quantum cryptosystem, that is, This means that the system performance is degraded. In particular, the effective repetition period of photon detection is limited by the blanking time in spite of the gate mode that can speed up the photon detection operation. The problem is that it cannot be obtained sufficiently.

  The present invention has been made in view of such problems, and controls the after pulse of the APD after the fact and detects a photon with a high repetition period, and a photodetector and a measuring instrument using the same. It is an object of the present invention to provide a quantum cryptography device, a quantum communication device, a quantum computer, a system using them, and a bias power supply control method.

  In order to achieve the above object, the present invention provides, as a first aspect, an avalanche photodiode, a DC power supply circuit that outputs a DC power supply voltage, and a gate pulse that generates a gate pulse according to a timing clock input from the outside. A driver circuit; a first superimposing circuit that superimposes a gate pulse on a DC power supply voltage; an afterpulse suppression circuit that generates an afterpulse suppression signal that reduces a bias voltage applied to the avalanche photodiode for a predetermined time; and a DC power supply. A second superposition circuit for superposing the after-pulse suppression signal on the voltage, and the avalanche photodiode is configured such that the DC power supply voltage on which the gate pulse and the after-pulse suppression signal are superimposed is applied to one electrode and the other electrode Providing a photodetection circuit characterized by outputting a photodetection signal from A.

  In order to achieve the above object, as a second aspect, the present invention superimposes a gate pulse on a DC component of a bias voltage applied to an avalanche photodiode of a photodetection circuit using a gate mode avalanche photodiode, A bias voltage control method for generating a blanking time for stopping a gate pulse after photon detection, wherein at least part of the blanking time, a bias voltage applied to an avalanche photodiode is more than a voltage defined by its DC component. Further, the present invention provides a method for controlling a bias voltage, characterized by applying an after-pulse suppression signal that further lowers the voltage.

  In order to achieve the above object, the present invention provides, as a third aspect, a photodetector using the photodetector circuit according to the first aspect of the present invention.

  Moreover, in order to achieve the said objective, this invention provides the measuring device using the photodetector which concerns on the said 3rd aspect of this invention as a 4th aspect.

  Moreover, in order to achieve the said objective, this invention provides the quantum cryptography apparatus using the photodetector which concerns on the said 3rd aspect of this invention as a 5th aspect.

  In order to achieve the above object, the present invention provides, as a sixth aspect, a quantum communication device using the photodetector according to the third aspect of the present invention.

  In order to achieve the above object, the present invention provides, as a seventh aspect, a quantum computer using the photodetector according to the third aspect of the present invention.

  Moreover, in order to achieve the said objective, this invention provides the measuring system using the measuring device which concerns on the said 4th aspect of this invention as an 8th aspect.

  In order to achieve the above object, the present invention provides, as a ninth aspect, a quantum cryptography apparatus according to the fifth aspect of the present invention, a quantum communication apparatus according to the sixth aspect of the present invention, and the present invention. An information communication system comprising at least one of the quantum computers according to the seventh aspect of the present invention is provided.

  According to the present invention, a photodetection circuit that can control an afterpulse of an APD after the fact and can detect photons at a high repetition period, and a photodetector, a measuring instrument, a quantum cryptography device, a quantum communication device, a quantum using the same It is possible to provide a computer, a system using these, and a control method of a bias power source.

  In the present invention, by changing the bias voltage applied to the APD during blanking, the residual carriers that are the source of the after pulse can be efficiently reduced, and the blanking time can be shortened.

  As shown in FIG. 1, the photodetection circuit according to the present invention generates an APD 101, a DC bias power supply circuit 107 that outputs a DC power supply voltage VB1, and a gate pulse GP1 according to a timing clock C1 that is input from the outside. A gate pulse driver circuit 106; a superposition circuit 181 that superimposes the gate pulse GP1 on the DC power supply voltage VB1; an afterpulse suppression circuit 104 that generates an afterpulse suppression signal AC1 that reduces the bias voltage applied to the APD1 for a predetermined time; And a superimposing circuit 182 that superimposes the after-pulse suppression signal AC1 on the DC power source voltage VB2, and the APD 1 has a DC power source voltage VB3 in which the gate pulse GP1 and the after-pulse suppression signal AC1 are superimposed applied to one electrode. The light detection signal S2 is output from the other electrode.

  Alternatively, as shown in FIG. 2, the photodetection circuit according to the present invention generates an APD 101, a DC bias power supply circuit 107 that outputs a DC power supply voltage, and a gate pulse GP1 according to a timing clock C1 that is input from the outside. A gate pulse driver circuit 106 for superimposing, a superposition circuit 181 for superimposing the gate pulse GP1 on the DC power supply voltage VB1, and an after-pulse suppression circuit 104 for generating an after-pulse suppression signal AC1 for reducing the bias voltage applied to the APD 1 for a predetermined time. The DC power supply voltage VB3 on which the gate pulse GP1 is superimposed is applied to one electrode of the APD1, and the other electrode of the APD1 is after-saved via a resistor having a finite resistance value including zero. A pulse suppression circuit 104 is connected, and the electric power of other electrodes is determined by an after pulse suppression signal AC1. The is raised to reduce the potential difference between both electrodes of APD1.

  An APD adopting the configuration shown in FIGS. 1 and 2 operates as follows.

  As shown in FIG. 3, the bias voltage applied to the APD is lowered during the blanking time, or the bias current is oscillated at a voltage not exceeding the breakdown voltage. As a result, the effective bias voltage applied during the blanking time is reduced as compared with the case where such control is not performed.

First, APD multiplication during the blanking time will be described.
FIG. 4 shows the relationship between the change in bias voltage during blanking and the number of residual carriers. The upper part of FIG. 4 shows the multiplication factor of the APD with respect to the bias voltage applied to the APD, the middle part shows the IV (current-voltage) characteristics of the APD, and the lower part shows the time (vertical length) of the voltage applied to the APD in the gate mode. Direction) and the IV characteristic.

  The bias voltage applied to the APD in the gate mode corresponds to a shaded region in the drawing around 70 V on the static IV characteristic. The bias voltage applied to the APD is repeated in two states: a normal mode state of 70V or less and a Geiger mode state in which the bias voltage exceeds 70V by the gate pulse.

  Since the normal mode state is lower than the breakdown voltage, a current corresponding to the dark current is generated if no light is incident on the APD. However, in the normal mode, it is a bias condition that enables a several tens of times avalanche multiplication, and it is considered that some carriers are repeatedly multiplied inside the APD multiplication layer.

Even when the gate pulse ends, the bias voltage returns to the normal mode, and the avalanche multiplication factor decreases, there are carriers that are regenerated while being attenuated. When breakdown occurs at the previous gate, it is in the state immediately after a huge carrier of about 1 × 10 ⁶ is generated and filled in the APD, so avalanche multiplication is started at the next gate pulse application. A sufficient number of carriers will remain in the multiplication layer.

  In the above model, in order to suppress the regeneration of carriers during blanking, as shown in FIG. 3, the bias voltage is temporarily lowered during the blanking time. By controlling the bias voltage in this way, residual carriers are effectively suppressed and the blanking time is shortened without increasing the gate pulse amplitude.

The relationship between bias voltage control and gain is shown in FIG. The multiplication factor is temporarily lowered by lowering the bias voltage than the normal mode during the blanking time. In FIG. 5, with respect to the avalanche multiplication factor of 10 in the normal mode region, the multiplication factor is temporarily reduced to 2 times by further reducing the bias current during the blanking time.
Specifically, in general, the multiplication factor of APD1 at the peak of the gate pulse is 10 ⁴ to 10 ⁶ times, and the increase of APD1 by the voltage specified by the DC component of the bias voltage during the blanking time is performed. Since the magnification is 10 to several hundred times, the after pulse suppression signal AC1 is applied so that the multiplication factor of APD1 when the after pulse suppression signal AC1 is applied is several times to 10 times.

  Thus, in the present invention, by controlling the bias voltage during the time when the APD is in the normal mode state, the APD multiplication factor is lowered, and as a result, the afterpulse probability is lowered. Probability can be controlled. That is, the after-pulse probability can be reduced without depending on the characteristics of the APD element itself. For this reason, if the after-pulse probability is reduced by improving the device performance in parallel, the after-pulse reduction can be reduced to the same extent in a shorter development period compared to reducing the after-pulse probability only by improving the device performance. An effect can be obtained.

  In the present invention, the dead time of the photon detection circuit is also shortened by shortening the blanking time, so that the photon detection opportunities can be increased. In the methods described in the above documents, the substantial photon detection rate is limited by the blanking time. However, in the present invention, the repetition frequency of the photon detection operation is increased due to the effect of shortening the blanking time. It becomes easy to reflect.

  Furthermore, this effect also makes it possible to suppress the after-pulse probability that increases when the APD is cooled, and it is possible to achieve both dark count suppression and after-pulse suppression.

  Such a light detection circuit can be applied to a light detector, a measuring device, a quantum cryptography device, a quantum communication device, a quantum computer, and a measurement system and an information communication system using these.

  Hereinafter, preferred embodiments of the present invention will be described.

[First Embodiment]
A first embodiment in which the present invention is suitably implemented will be described.
FIG. 6 shows the configuration of the photon detector according to this embodiment. The photon detector includes an APD 1, a charge pulse cancel circuit 21, an identification circuit 22, a DC bias power supply circuit 7, a blanking control circuit 5, a gate pulse driver circuit 6, a delay circuit 3, and an after pulse suppression circuit 4. As a signal input / output, a single photon signal S1 and a gate clock generation timing clock signal C1 are input, and a photon detection signal S3 is output.

  In the following description, a positive voltage is used as the DC bias voltage, a bias voltage is applied to the cathode of the APD, and a photon detection signal output is obtained from the anode. In the case of using a negative voltage as the DC bias voltage, the polarity of the APD is only reversed, and the basic functional configuration is not changed, and thus description thereof is omitted.

  A DC component VB1 of a bias voltage is constantly applied from the DC bias power supply circuit 7 to the cathode of the APD1. The DC component VB1 of the bias voltage is a voltage lower than the breakdown voltage of APD1.

  The gate pulse driver circuit 6 generates a gate pulse GP1 from the timing clock signal C1 synchronized with the incidence of the single photon signal S1 on the APD1. The gate pulse GP1 is superimposed on the bias voltage VB1 by the adding circuit 81.

  A signal S2 output from the anode of the APD 1 when a photon is detected is input to the charge pulse cancel circuit 21. The charge pulse cancel circuit 21 generates a charge pulse cancel signal S 21 based on the input signal S 2 and outputs the charge pulse cancel signal S 21 to the identification circuit 22. The identification circuit 22 generates a photon detection signal S3 based on the input charge pulse cancel signal S21 and outputs it to an external circuit. The photon detection signal S3 is also input to the blanking circuit 5, and based on this, the blanking circuit 5 outputs a blanking signal S5. The blanking signal S5 is input to the gate pulse driver circuit 6 and stops the generation of the gate pulse for a certain time. The photon detection signal S3 is also input to the delay circuit 3, and is input to the after-pulse suppression circuit 4 after being delayed for a predetermined time. The after pulse suppression circuit 4 generates an after pulse suppression signal AC1 based on the input signal (delayed photon detection signal S3), and outputs it to the subtraction circuit 82. The after-pulse suppression signal AC1 is superimposed by the subtraction circuit 82 on the bias voltage VB2 on which the gate pulse is superimposed. Here, assuming that the after-pulse suppression signal AC1 is a positive voltage signal, a configuration in which the after-pulse suppression signal AC1 is superimposed on VB2 by subtracting from the bias voltage VB2 by the subtraction circuit 82 is shown. However, when the after-pulse suppression signal AC1 is generated as a negative voltage signal, the after-pulse suppression signal AC1 may be superimposed by adding the bias voltage VB2 and the after-pulse suppression signal AC1.

  The addition circuit 81 and the subtraction circuit 82 that superimpose the gate pulse GP1 and the after-pulse suppression signal AC1 on the DC bias voltages VB1 and VB2 can be configured by a high-frequency filter circuit such as a bias T. The configurations of the adding circuit 81 and the subtracting circuit 82 will be described in detail later.

  In response to the input of the photon detection signal S3, the blanking circuit 5 generates the blanking control signal S5 for an arbitrarily set time. The gate pulse driver circuit 6 stops the output in response to the input of the blanking control signal S5, and realizes blanking by stopping the application of the gate pulse GP1 to the APD1.

  The after pulse suppression circuit 4 generates the after pulse suppression signal AC1 during the output of the blanking signal S5 in response to the input of the delayed photon detection signal S3, thereby applying a bias voltage applied to the APD 1 Reduce. The output timing of the after pulse control signal AC1 is adjusted by the delay circuit 3 to an appropriate time for the blanking time.

FIG. 7 shows an example of the operation of the photon detector. For simplification of explanation, it is assumed here that no circuit delay or wiring delay occurs.
The gate pulse GP1 is generated as a short pulse in response to the rising transition of the timing clock C1. In the second clock of the timing clock C1 in the figure, the blanking signal S5 is subsequently generated because the APD 1 detects the photon. With the blanking signal S5 generated at the second clock, the timing clock C1 is masked between the third clock and the fifth clock of the timing clock C1, and the generation of the gate pulse GP1 is stopped.

  The gate voltage VB3 applied to the APD1 has a waveform obtained by subtracting the after pulse suppression signal AC1 from the gate pulse GP1. In FIG. 7, the absolute value of the DC component VB1 is omitted.

  Assuming that photons do not necessarily occur in all time slots, only three times (second clock, fifth clock, and seventh clock of timing clock C1) are used. It is assumed that no photons are incident that are not synchronized with the timing of the gate pulse GP1. Among these photon incidents, the photon incident at the fifth clock of the timing clock C1 is discarded without being detected because no gate pulse is applied during the blanking time.

  The output signal S2 of APD1, the charge pulse cancel signal S21 that is the output of the charge pulse cancel circuit 21, and the photon detection signal S3 are converted from analog to digital in the process of the detection circuit, but the information as photon detection is unchanged. Therefore, the description of each is omitted. Since the photon detection signal S3 is output to a circuit outside the photon detector, it is a digital signal having a clock cycle width.

  The blanking control circuit 5 generates a blanking signal S5 based on the photon detection signal S3. The blanking signal S5 is generated according to a time width set in advance for the blanking control circuit 5. Here, it is assumed that the time width is equivalent to three clocks of the timing clock C1.

  The photon detection signal S3 is also input to the after-pulse suppression circuit 4, and the after-pulse suppression signal AC1 is output from the after-pulse suppression circuit 4 accordingly. The after-pulse suppression signal AC1 is generated according to the photon detection signal S3 delayed by the delay circuit 3 so that it can be generated at an arbitrary timing during the blanking time. Here, the one-clock spectroscopic detection signal S3 of the timing clock C1 is delayed, and the bias voltage is lowered by the width of one clock.

  The number of residual carriers is sufficiently small until just before the APD 1 breaks down due to photon detection. When the APD 1 breaks down at the second clock of the timing clock C1, the number of carriers rapidly increases. Thereafter, during the blanking time, the residual carrier gradually decreases with a predetermined time constant. In the absence of the afterpulse suppression circuit 4, it is assumed that the number of residual carriers decreases linearly as shown by the dotted line in the figure. On the other hand, by providing the after-pulse suppressing circuit 4, the after-pulse suppressing signal AC1 is superimposed on the bias voltage VB2 at the fourth clock of the timing clock C1, and the number of residual carriers is rapidly reduced as indicated by a solid line in the figure. .

In the absence of the after-pulse suppression circuit 4, after the blanking time for 3 clocks after breakdown, the number of remaining carriers indicated by the dotted line is obtained at the sixth clock of the timing clock C1. In this case, when the gate pulse is applied at the sixth clock of the timing clock C1, there is a high probability that the APD 1 will cause a breakdown as an after pulse even though there is no photon input. As a result, since the blanking state starts again from the seventh clock of the timing clock C1, the photons incident at the seventh clock cannot be detected.
Further, in the absence of the after-pulse suppression circuit 4, a longer blanking time is required to bring the gradually decreasing residual carrier number closer to the baseline, and similarly, a photon incident at the seventh clock cannot be detected.

<Configuration Example 1 of Adder Circuit and Subtractor Circuit>
A configuration of an addition circuit and a subtraction circuit regarding application of a bias voltage to the APD 1 will be described.
The basic operation of the bias voltage applied to the APD 1 in the gate mode is that a gate pulse having a time width of about several hundred psec to several nsec is repeated at a constant cycle of several nsec to several tens of nsec. The gate pulse stops for a specified time of 10 nsec to several μsec or more. For such an operation, the adder circuit 81 and the subtractor circuit 82 require an electronic circuit that requires transmission characteristics in a wide frequency band.

  Here, in general, the blanking time is 10 times longer than the gate pulse GP1. Further, the after-pulse suppression signal AC1 does not need to be a rectangular wave as long as a desired bias voltage drop occurs during the blanking time. For these reasons, the after-pulse suppression circuit 4 can be configured with a low-speed circuit as compared with the gate pulse driver circuit 6. Therefore, the subtracting circuit 82 can be realized while maintaining the characteristic impedance of 50 ohm required for the nsec class high frequency circuit.

FIG. 8 shows the configuration of an adder circuit 81 and a subtractor circuit 82 that generate a bias voltage VB3 to be applied to the cathode terminal of the APD1.
The adder circuit 81 includes a low pass filter (Low Pass Filter: LPF) 81a and a high pass filter (High Pass Filter: HPF) 81b. The DC bias power supply circuit 7 is connected to the gate pulse driver circuit 6 via the low-pass filter 81a and the high-pass filter 81b, and the DC component VB1 and the gate pulse GP1 are added.
The subtracting circuit 82 includes a band pass filter (BPF) 82b. The bias voltage VB2 that is the addition result of the DC component VB1 and the gate pulse GP1 is added with the afterpulse suppression signal AC1 that is the output of the afterpulse suppression circuit 4 via the bandpass filter 82b, and is supplied to the cathode terminal of the APD1. Applied. Further, a termination resistor 91 for impedance matching of the transmission line and a capacitor 92 for blocking the DC component are connected to the cathode terminal of the APD 1.

  FIG. 9 shows the relationship of the transmission band spectra of LPF 81a, HPF 81b, and BPF 82b. Since the high-voltage DC bias VB1 is applied, the HPF 81b and the BPF 82b block the DC component with a capacitor (not shown) in order to prevent the DC component from flowing into the termination resistor 91 and each circuit.

Here, when the outputs of the gate pulse driver circuit 6 and the after-pulse suppression circuit 4 are connected in parallel to the same high-pass filter circuit, the characteristic impedance of a series of high-frequency circuits following the cathode of the APD 1 is lowered, and the gate pulse Decrease in amplitude and waveform deterioration occur. In order to prevent this drop in impedance, the BPF 82 is used as the subtraction circuit 82 for the after-pulse suppression signal AC1 to separate the frequency band from the gate pulse, thereby avoiding a drop in characteristic impedance.
As shown in the spectral component of FIG. 9, the spectral component of the after-pulse suppression signal AC1 is selected to have a lower frequency component than the frequency component of the gate pulse GP1, so that an appropriate filter transmission characteristic can be designed. This makes it possible to avoid the waveform deterioration of the gate pulse GP1.

<Configuration Example 2 of Adder Circuit and Subtractor Circuit>
FIG. 10 shows another configuration of the addition circuit 81 and the subtraction circuit 82 that generate the bias voltage VB3 to be applied to the cathode terminal of the APD1.
The adder circuit 81 is realized by a bias T circuit. The subtraction circuit 82 superimposes the after-pulse suppression signal AC1 through a high impedance circuit instead of a filter. Here, a drop in the specific impedance of the transmission line is reduced by inserting a resistor 82c in series and increasing the output impedance of the after-pulse suppressing circuit 4 viewed from the transmission line of the bias voltage VB3.

<Configuration Example 3 of Adder Circuit and Subtractor Circuit>
FIG. 11 shows another configuration of the addition circuit 81 and the subtraction circuit 82 that generate the bias voltage VB3 to be applied to the cathode terminal of the APD1.
By controlling the ON / OFF state of the switch element 41 provided in the after-pulse suppression circuit 4 with the photon detection signal S3, the after-pulse suppression signal AC1 is added due to the voltage drop due to the charge drawing through the capacitor 82d. . The amount of voltage decrease and the time width are adjusted by the circuit constants of the resistance values and capacitances of the resistor 82c and capacitor 82d. The time constant determined by the inductance of the adding circuit 81 as the bias T and the internal resistance of the DC bias power supply circuit 7 needs to be sufficiently larger than the CR time constant. By using a transistor or a field effect transistor (FET) as the switch element 41 of the after-pulse suppressing circuit 4, a high-speed switching operation can be performed.

<Configuration Example 4 of Adder Circuit and Subtractor Circuit>
FIG. 12 shows another configuration of the addition circuit 81 and the subtraction circuit 82 related to the bias voltage VB3 applied to the cathode terminal of the APD1.
In the illustrated configuration, by using the circulators 81c and 82e, it is possible to add the gate pulse GP1 and the after-pulse suppression signal AC1 and to maintain the characteristic impedance of the transmission path.

  Specifically, the gate pulse signal GP1 output from the gate pulse driver circuit 6 passes through the circulator 81c, is superimposed on the bias voltage VB1 at the bias T, and is applied to the APD1. Subsequently, the component of the gate pulse GP1 passes through the capacitor 92 and is terminated by the termination resistor 91 via the circulator 82e.

  Subsequently, transmission of the after-pulse suppression signal will be described. The after pulse suppression signal AC1 is output from the after pulse suppression circuit 4 independently of the gate pulse GP1, is applied to the APD 1 via the circulator 82e and the capacitor 92, and is supplied to the high frequency port of the bias T in the adder circuit 81. The output is terminated by a termination resistor 93 via the circulator 81c.

In the illustrated configuration, by using the circulators 81c and 82e, the gate pulse GP1 and the after-pulse suppression signal AC1 are independently transmitted in the reverse direction on the transmission path. As a result, the characteristic impedance of the transmission line and the output impedances of the gate pulse driver circuit 6 and the after pulse suppression circuit 4 are matched even in the high frequency region. Therefore, the high frequency components of the gate pulse GP1 and the after pulse suppression signal AC1 can be transmitted without being deteriorated in waveform and applied to the APD1. Thereby, the design of the BPF as described in FIG. 9 can be omitted.
Furthermore, since the after pulse suppression signal due to the band limitation of the filter can be applied to the APD 1, the restriction on the blanking time is eliminated. As a result, the effective frequency of photon detection can be further increased by a synergistic effect of shortening the blanking time and shortening the pulse width of the after-pulse suppression signal AC1.

  In the above configuration, the transmission path (mainly the region of the bias voltage VB3) including the two circulators 81c and 82e, the bias T, the capacitor 92, and the APD1 is required to have a uniform characteristic impedance in terms of high frequency. . For this reason, for example, when an output impedance circuit of 50 ohm is used, avoid a stub structure as much as possible on one transmission line having a characteristic impedance of 50 ohm (in other words, minimize branching of the transmission line) It is preferable to connect the cathode of the APD.

  As the circulators 81c and 82e, known ones can be applied, and a detailed description thereof will be omitted.

[Second Embodiment]
A second embodiment in which the present invention is suitably implemented will be described.
FIG. 13 shows a configuration of a main part of the photon detector according to the present embodiment. In FIG. 13, the same parts as those of the first embodiment are omitted, and only different parts are shown. Specifically, a configuration relating to the application of a voltage to the photon detection current S2 output from the anode terminal of the APD 1 and the resistor 23 and the amplifier circuit 24 built in the charge pulse cancel circuit 21 is shown.

  In the photon detector according to this embodiment, the bias voltage for suppressing the after-pulse is controlled by controlling the potential difference of the bias voltage applied between the anode and the cathode of the APD 1 and changing the voltage of the signal S2 on the anode side. This is realized by letting

The switch element 41 in the after-pulse suppression circuit 4 is controlled by a logic signal generated through the delay circuit 3 based on the photon detection signal S3. As a result, the voltage supplied from the DC power supply circuit 42 is applied to the anode of the APD 1 as the after-pulse suppression signal AC1.
When the switch element 41 is OFF, the output S2 on the anode side of the APD 1 is grounded via the resistor 23. In this state, during the blanking time, the dark current of APD1 is on the order of nA, and the anode potential can be regarded as approximately 0 V. Therefore, the bias voltage applied to APD1 is a value according to the output VB1 of DC bias power supply circuit 7 (To be more precise, a DC offset depending on the mark rate of the gate pulse GP1 occurs, but the details are omitted).
On the other hand, when the switch element 41 is turned on, the anode potential is increased by the voltage supplied from the DC power supply circuit 42. At this time, since the bias voltage of the APD 1 is a potential difference between the anode and the cathode, a decrease in the bias voltage corresponding to the output voltage of the DC power supply circuit 42 can be obtained.

In the present embodiment, the absolute value of the voltage connected to the switch element is lower than that of the configuration (configuration shown in FIG. 11) in which the switch element is arranged on the cathode side described in the first embodiment. Therefore, the element configuration can be simplified. Note that the anode of the APD 1 and the after-pulse suppression circuit 4 may be connected via a resistor.
Here, a transistor or FET can be used as the switch element 41, but the configuration and design of the switch circuit are not the gist of the present invention, and thus the description thereof is omitted.

[Third Embodiment]
A third embodiment in which the present invention is preferably implemented will be described.
FIG. 14 shows the configuration of the photon detector according to this embodiment. Although the configuration is almost the same as that of the first embodiment, the delay circuit 3 is different in that the blanking signal S5 is input instead of the photon detection signal S3.

  Since the photon detector according to the present embodiment can also generate the after-pulse suppression signal AC1 during the blanking time, the residual carriers can be effectively suppressed and the blanking time can be shortened without increasing the gate pulse amplitude.

[Fourth Embodiment]
A fourth embodiment in which the present invention is preferably implemented will be described.
FIG. 15 shows the configuration of the photon detector according to this embodiment. The configuration is almost the same as that of the first embodiment, except that the after pulse suppression signal AC1 output from the after pulse suppression circuit 4 is input to the DC bias power supply circuit 7.

  The photon detector according to the present embodiment controls the output voltage of the DC bias power supply circuit 7 by controlling the afterpulse suppression signal AC1 output from the afterpulse suppression circuit 4, thereby controlling the bias voltage for afterpulse suppression. To control. For this reason, in this embodiment, a variable voltage power supply circuit that can be controlled by an external input is applied as the DC bias power supply circuit 7. Since the variable voltage power supply circuit itself can apply a known configuration, a detailed description thereof will be omitted.

  In the present embodiment, the after-pulse suppressing circuit 4 does not require a driver circuit. Further, it is possible to avoid the disturbance of the characteristic impedance of the transmission path of the gate pulse GP1. As a result, the circuit configuration can be simplified.

[Fifth Embodiment]
A fifth embodiment preferably implementing the present invention will be described.
FIG. 16 shows the configuration of the photodetector according to this embodiment. The photon detector according to the present embodiment has a configuration in which the delay circuit and the blanking control circuit are omitted from the photon detector according to the first embodiment.

  In the present embodiment, the blanking time is generated based on the after-pulse suppression signal AC1. As shown in FIG. 17, when the amplitude of the after-pulse suppression signal AC1 is equal to or greater than the gate pulse, the blanking time is generated based on the after-pulse suppression signal, and the gate pulse GP1 is applied during that time. Even if the operation is continued, the bias voltage of the APD becomes sufficiently low. This effectively suppresses residual carriers and shortens the blanking time.

  As the addition circuit 81, the subtraction circuit 82, and the after-pulse suppression circuit 4, those having the same configuration as those of the above embodiments can be applied.

Each of the above embodiments is an example of a preferred embodiment of the present invention, and the present invention is not limited to these.
For example, in each of the above embodiments, the case where a single photon is detected is taken as an example, but the present invention can also be applied to a circuit that detects weak light composed of a plurality of photons.
In each of the above embodiments, the photon detection circuit has been described as an example. However, the well-known photon detection circuit included in the known optical measuring device, quantum cryptography device, quantum communication device, and quantum computer has been described in each of the above embodiments. It is also possible to replace it with something.
As described above, the present invention can be variously modified.

It is a figure which shows the structure of the photon detection circuit which concerns on this invention. It is a figure which shows another structure of the photon detection circuit which concerns on this invention. It is a time chart explaining the principle of the photon detection operation | movement by this invention. It is a characteristic diagram of APD explaining the principle of photon detection operation. It is a characteristic view of APD explaining the principle of the photon detection operation by this invention. It is a figure which shows the structure of the photon detection circuit which concerns on 1st Embodiment which implemented this invention suitably. It is a time chart explaining the photon detection operation | movement by the photon detection circuit which concerns on 1st Embodiment. It is a block diagram which shows the structure of the addition circuit and subtraction circuit which produce | generate the bias voltage applied to the cathode terminal of APD. It is a schematic diagram explaining the transmission spectrum of a filter. It is a block diagram which shows another structure of the addition circuit and subtraction circuit which produce | generate the bias voltage applied to the cathode terminal of APD. It is a block diagram which shows another structure of the addition circuit and subtraction circuit which produce | generate the bias voltage applied to the cathode terminal of APD. It is a block diagram which shows another structure of the addition circuit and subtraction circuit which produce | generate the bias voltage applied to the cathode terminal of APD. It is a figure which shows the structure of the principal part of the photon detection circuit which concerns on 2nd Embodiment which implemented this invention suitably. It is a figure which shows the structure of the photon detection circuit which concerns on 3rd Embodiment which implemented this invention suitably. It is a figure which shows the structure of the photon detection circuit which concerns on 4th Embodiment which implemented this invention suitably. It is a figure which shows the structure of the photon detection circuit which concerns on 5th Embodiment which implemented this invention suitably. It is a time chart explaining the principle of the photon detection operation | movement by the photon detection circuit which concerns on 5th Embodiment. It is a schematic diagram explaining a photon detection operation | movement and an after pulse. It is an actual measurement example explaining an after pulse by photon detection. It is a schematic diagram explaining a photon detection operation | movement and an after pulse. It is a block diagram which shows the structure of a photon detection circuit.

Explanation of symbols

1, 101 APD
3 Delay circuit 4, 104 After pulse suppression circuit 5 Blanking control circuit 6, 106 Gate pulse driver circuit 7, 107 DC bias power supply circuit 21 Charge pulse cancel circuit 22 Identification circuit 23, 82c Resistor 24 Amplifier circuit 41 Switch element 42 DC power supply Circuit 81 Adder circuit 81a LPF
81b HPF
81c, 82e Circulator 82 Subtractor 82b BPF
82d, 92 Capacitor 91, 93 Termination resistor 181, 182 Superposition circuit S1 Photon signal (optical signal)
S2 APD output signal (photon detection waveform: analog)
S3 Photon detection signal (logic signal)
S5 Blanking signal S21 Charge pulse cancel waveform (analog)
C1 Timing clock signal GP1 Gate pulse signal AC1 After pulse suppression signal VB1 DC component of bias voltage VB2 Bias voltage superimposed with gate pulse VB3 Bias voltage applied to APD

Claims (27)

An avalanche photodiode,
A DC power supply circuit for outputting a DC power supply voltage;
A gate pulse driver circuit that generates a gate pulse in accordance with an externally input timing clock; and
A first superimposing circuit for superimposing the gate pulse on the DC power supply voltage;
An after-pulse suppression circuit that generates an after-pulse suppression signal that reduces the bias voltage applied to the avalanche photodiode for a predetermined time;
A second superimposing circuit that superimposes the after-pulse suppression signal on the DC power supply voltage,
The avalanche photodiode is characterized in that a DC power supply voltage in which the gate pulse and the after-pulse suppression signal are superimposed is applied to one electrode, and a photodetection signal is output from the other electrode. A blanking circuit that stops the gate pulse driver circuit for a predetermined time according to the light detection signal;
The photodetector circuit according to claim 1, further comprising a delay circuit that activates the after-pulse suppression circuit during the operation of the blanking circuit.   The photodetection circuit according to claim 1, wherein the afterpulse suppression circuit operates for a predetermined time in accordance with the photodetection signal and generates the afterpulse suppression signal having an amplitude equal to or greater than the amplitude of the gate pulse.   4. The photodetection circuit according to claim 1, wherein the first and second superimposing circuits include a plurality of filter circuits or impedance matching circuits whose pass bands do not overlap each other. 5. The first superposition circuit includes:
A first filter circuit used to superimpose the gate pulse and having the highest passband;
A second filter circuit used for superimposing the power supply voltage and having the lowest passband,
The second superposition circuit includes:
A third filter circuit that is used to superimpose the after-pulse suppression signal and that passes a pass band of the first filter circuit and an intermediate band of the second filter circuit. Item 5. The photodetector circuit according to Item 4. The first superposition circuit includes:
A fourth filter circuit used for superimposing the gate pulse;
A fifth filter circuit used to superimpose the DC power supply voltage and having a pass band lower than that of the fourth filter circuit;
The second superposition circuit includes:
5. The photodetector circuit according to claim 4, further comprising a resistor that uses the after-pulse suppression signal and has a resistance value sufficiently higher than an output impedance of the gate pulse driver circuit. The first superposition circuit includes:
A sixth filter circuit used for superimposing the DC power supply voltage; a seventh filter circuit used for superimposing the gate pulse; and having a passband higher than that of the sixth filter circuit;
A three-terminal first circulator inserted between the gate pulse driver circuit and the seventh filter circuit;
A first termination circuit connected to the remaining one end of the first circulator;
The second superposition circuit includes:
An eighth filter circuit used for superimposing the after-pulse suppression signal;
A three-terminal second circulator inserted between the after-pulse suppressing circuit and the eighth filter circuit;
The photodetection circuit according to claim 4, further comprising a second termination circuit connected to the other end of the second circulator. The gate pulse output from the gate pulse generation circuit passes through the first circulator to the avalanche photodiode side,
The after-pulse suppression signal output from the after-pulse suppression circuit passes through the second circulator to the avalanche photodiode side,
8. The photodetection circuit according to claim 7, wherein a signal input from the avalanche photodiode side to the first or second circulator passes to the first or second termination circuit. An avalanche photodiode,
A DC power supply circuit for outputting a DC power supply voltage;
A gate pulse driver circuit that generates a gate pulse in accordance with an externally input timing clock; and
A first superimposing circuit for superimposing the gate pulse on the DC power supply voltage;
An after-pulse suppression circuit that generates an after-pulse suppression signal that lowers the bias voltage applied to the avalanche photodiode for a predetermined time;
A DC power supply voltage on which the gate pulse is superimposed is applied to one electrode of the avalanche photodiode,
The afterpulse suppression circuit is connected to the other electrode of the avalanche photodiode via a resistor having a finite resistance value including zero,
The photodetection circuit, wherein the potential difference between the two electrodes of the avalanche photodiode is reduced by increasing the potential of the other electrode by the after-pulse suppression signal. A blanking circuit that stops the gate pulse driver circuit for a predetermined time according to a light detection signal output from the other electrode of the avalanche photodiode;
The photodetection circuit according to claim 9, further comprising a delay circuit that activates the after-pulse suppression circuit during the operation of the blanking circuit.   The after-pulse suppression circuit operates for a predetermined time according to a light detection signal output from the other electrode of the avalanche photodiode, and generates the after-pulse suppression signal whose amplitude is equal to or greater than the amplitude of the gate pulse. The photodetection circuit according to claim 9.   12. The method according to claim 1, wherein an electrical switch element is used in the after-pulse suppression signal generation circuit, and whether or not the after-pulse suppression signal is output is switched by a switching operation of the electrical switch element. The photodetector circuit according to the item.   The DC bias power supply circuit has an output voltage variable by external control, and also functions as the second superposition circuit by reducing the DC power supply voltage in accordance with the output of the after-pulse suppression circuit. The photodetection circuit according to claim 1, wherein the photodetection circuit is characterized in that:   The photodetection circuit according to claim 1, wherein the avalanche photodiode is capable of detecting a single photon.   The photodetection circuit according to claim 1, further comprising a charge pulse cancel circuit that removes a differential component of the gate pulse output from the avalanche photodiode. Bias voltage control for generating a blanking time to stop the gate pulse after detecting a photon by superimposing a gate pulse on a DC component of a bias voltage applied to the avalanche photodiode of a photodetection circuit using an avalanche photodiode in a gate mode A method,
Bias voltage control characterized by applying an after-pulse suppression signal that further lowers the bias voltage applied to the avalanche photodiode to a voltage defined by its DC component during at least a part of the blanking time. Method. Bias voltage control for generating a blanking time to stop the gate pulse after detecting a photon by superimposing a gate pulse on a DC component of a bias voltage applied to the avalanche photodiode of a photodetection circuit using an avalanche photodiode in a gate mode A method,
At least part of the blanking time, a DC component of the bias voltage is reduced by an afterpulse suppression signal having an amplitude in which the peak voltage of the gate pulse applied to the avalanche photodiode is lower than the breakdown voltage of the avalanche photodiode. A method for controlling a bias voltage, wherein the bias voltage is decreased.   The amplitude of the after-pulse suppression signal is an amplitude that reduces the multiplication factor of the avalanche photodiode to a predetermined value by a voltage defined by a DC component of a bias voltage applied to the avalanche photodiode. 18. The method for controlling a bias voltage according to claim 16 or 17. The multiplication factor of the avalanche photodiode at the peak of the gate pulse is 10 ⁴ to 10 ⁶ times, and the multiplication factor of the avalanche photodiode according to the voltage defined by the DC component of the bias voltage during the blanking time When the after-pulse suppression signal is applied, the after-pulse suppression signal is applied so that a multiplication factor of the avalanche photodiode when applying the after-pulse suppression signal is several to 10 times. The method for controlling a bias voltage according to any one of claims 16 to 18.   A photodetector using the photodetector circuit according to claim 1.   A photodetector for controlling a bias voltage to be applied to an avalanche photodiode by the method for controlling a bias voltage according to any one of claims 16 to 19.   A measuring instrument using the photodetector according to claim 20 or 21.   A quantum cryptography device using the photodetector according to claim 20 or 21.   A quantum communication device using the photodetector according to claim 20 or 21.   A quantum computer using the photodetector according to claim 20 or 21.   A measurement system comprising the measuring instrument according to claim 22.   An information communication system comprising at least one of the quantum cryptography device according to claim 23, the quantum communication device according to claim 24, and the quantum computer according to claim 25.

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