JP2009231372A - Pattern formation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern formation method capable of correctly forming a plurality of sparsely and densely arranged patterns. <P>SOLUTION: The method includes a step of forming a first insulation film 15 on a substrate 14, forming a first mask material 31 having first aperture patterns 31a-31d sparsely and densely provided on the first insulation film 15 and etching the first insulation film 15 by means of the first mask material 31 to transfer the first aperture patterns 31a-31d, a step of removing the first mask material 31 and forming a second insulation film 32 made of a material different from that of the first insulation film 15 to cover the upper surface of the first aperture patterns 15a-15d on the first insulation film 15, and a step of forming a second mask material 36 having second aperture patterns 36a-36d opposite to the first aperture patterns 15a-15d on the second insulation film 32, etching the second insulation film 32 by means of the second mask material 36, and etching the first insulation film 15 to a predetermined depth by means of the second mask material 36. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pattern forming method.

  Corresponding to miniaturization and high integration of semiconductor devices, there is a need for a pattern forming method capable of accurately and easily forming a multilayer wiring pattern that connects lower layer wiring and upper layer wiring by via contact.

  Conventionally, a hole for via contact is formed in the interlayer insulating film formed on the lower layer wiring, and a resist film for forming a wiring groove for embedding the upper layer wiring is applied on the interlayer insulating film in which the hole is formed. In this case, there is a problem that the resist film thickness is reduced when the holes are densely arranged, and the resist film thickness is increased when the holes are sparsely arranged.

  Therefore, when the resist film thickness is thin, the lower layer wiring may be damaged, and when the resist film thickness is thick, a fence-like deposit (crown fence) may be generated around the hole, and between the upper layer wiring and the via contact. There is a problem in that the resistance of the multi-layer wiring decreases and the reliability of the multilayer wiring decreases.

  On the other hand, a method is known in which a wiring groove is formed so that a crown fence does not occur around the hole, and a lower layer wiring is protected from damage caused by etching in a process of forming the hole and the wiring groove (for example, (See Patent Document 1).

In the method of forming a multilayer wiring disclosed in Patent Document 1, after patterning a lower layer wiring on a first interlayer insulating film on a semiconductor substrate, an etching stop layer, a second interlayer insulating film, and an antireflection film are sequentially deposited. .
Next, holes and wiring grooves are sequentially patterned in the second interlayer insulating film. At this time, an etching condition is set so that the lower layer wiring is not exposed, and a recess is formed in the etching stop layer. Next, the etching stopper layer located below the hole is removed, and then the lower layer wiring is exposed, and then the via contact and the upper layer wiring are formed.

However, the method for forming a multilayer wiring disclosed in Patent Document 1 does not disclose anything about a case where a plurality of multilayer wirings are densely arranged.
JP 2004-63731 A

  Provided is a pattern forming method capable of accurately forming a plurality of densely arranged patterns.

  In the pattern forming method of one embodiment of the present invention, a first insulating film is formed on a substrate, and a first mask material having a plurality of first opening patterns arranged densely on the first insulating film is formed. Etching the first insulating film using the first mask material to transfer the plurality of first opening patterns; removing the first mask material; and covering upper surfaces of the plurality of first opening patterns. And forming a second insulating film made of a material different from that of the first insulating film on the first insulating film, and a plurality of second facing the plurality of first opening patterns on the second insulating film. A second mask material having an opening pattern is formed, the second insulating film is etched using the second mask material, and the first insulating film is etched to a predetermined depth using the second mask material. And a step of performing

  A pattern forming method capable of accurately forming a plurality of densely arranged patterns is obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A pattern forming method according to Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing a multilayer wiring of a semiconductor device using a pattern forming method. FIG. 1A is a sectional view thereof, FIG. 1B is a perspective view showing an essential part thereof, and FIGS. It is sectional drawing which shows a formation process in order.

As shown in FIG. 1, a multilayer wiring 10 of a semiconductor device using the pattern forming method of this embodiment includes a semiconductor substrate (not shown), an insulating film 11 formed on the semiconductor substrate, and an insulating film 11. A substrate 14 having a first wiring 12 embedded in a formed wiring trench (not shown) and an insulating film 11 and an insulating film 13 formed on the upper surface of the first wiring 12 is provided.
Furthermore, the first insulating film 15 formed on the substrate 14, the via contact 16 formed at a position facing the first wiring 12 below the first insulating film 15, and the upper side of the first insulating film 15 A second wiring 17 embedded in a wiring groove (not shown) formed at a position facing the via contact 16 and connected to the first wiring 12 through the via contact 16; a first insulating film 15; And a protective film 18 formed on the wiring 17.

Of the via contacts 16, the via contacts 16a, 16b, and 16c are arranged at a first pitch L1, and the via contacts 16d are arranged from the via contacts 16c at a second pitch L2 that is larger than the first pitch L1.
Similarly, of the second wiring 17, the second wirings 17a, 17b, 17c are arranged at the first pitch L1, and the second wiring 17d is a second pitch L2 larger than the first pitch L1 from the second wiring 17c. Is arranged in.

That is, the via contacts 16a, 16b, 16c and the second wirings 17a, 17b, 17c are densely arranged. The via contact 16d and the second wiring 17d are sparsely arranged.
The first pitch L1 is in the submicron order, the second pitch L2 is in the micron order, and the ratio between the first pitch L1 and the second pitch L2 is, for example, about 1: 3.

  2 to 4 are cross-sectional views sequentially showing a pattern forming process for forming a hole pattern to be the via contact 16 of the multilayer wiring 10 and a trench (wiring groove) pattern to be the second wiring 17.

  First, as shown in FIG. 2 (a), a semiconductor substrate (not shown), an insulating film 11 formed on the semiconductor substrate, and a trench (not shown) formed in the insulating film 11 and arranged densely. The substrate 14 having the first wiring 12 embedded in the first wiring 12 and the insulating film 11 and the insulating film 13 formed on the upper surface of the first wiring 12 is formed.

  Specifically, a silicon oxide film is formed on the semiconductor substrate (not shown) as the insulating film 11 by, for example, a CVD (Chemical Vapor Deposition) method, and is densely arranged on the insulating film 11 by, for example, an RIE (Reactive Ion Etching) method. A trench (not shown) is formed, a conductive material (copper) is deposited on the insulating film 11 by, for example, electrolytic plating, and the conductive material is applied until the surface of the insulating film 11 is exposed by CMP (Chemical Mechanical Polishing). The first wiring 12 having a conductive material embedded in the trench is removed, and a silicon nitride film is formed as an insulating film 13 on the upper surfaces of the insulating film 11 and the first wiring 12 by, for example, a plasma CVD method.

Next, a silicon oxide film having a thickness of about 1 μm and serving as the first insulating film 15 is formed on the substrate 14 by, eg, CVD.
Next, a resist film is applied on the silicon oxide film by a spin coating method and patterned by a photolithography method, and a plurality of first opening patterns 31a and 31b are arranged at positions facing the densely arranged first wirings 12. , 31c and 31d are formed.

Next, as shown in FIG. 2B, the substrate 14 is accommodated in a reaction vessel (not shown), and the first mask material 31 is used as a process gas for CH ₂ F ₂ , C ₄ F ₈ , Plasma treatment using a mixed gas containing Ar and O ₂ is performed to etch the silicon oxide film.
Thereby, the first insulating film 15 to which the plurality of first opening patterns 15a, 15b, 15c, and 15d arranged in a sparse and dense manner are transferred is obtained.

Next, as shown in FIG. 2C, while the substrate 14 is housed in a reaction vessel (not shown), the process gas is switched to O ₂ gas and plasma treatment (ashing) is performed, so that the first mask material is obtained. 31 is removed.

Next, as shown in FIG. 3A, plasma processing is performed by switching the process gas to a mixed gas containing CH ₂ F ₂ and C ₄ F ₈ while the substrate 14 is housed in a reaction vessel (not shown). To form a CF-based deposit having a thickness of about 50 to 100 nm.
As a process gas, Ar provides an assisting action for etching and is basically unnecessary. However, Ar may be contained if the amount is small.
Accordingly, the second insulating film 32 made of a material different from that of the first insulating film 15 is formed on the first insulating film 15 by covering the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d that are densely arranged. .

  Since the CF-based deposit only needs to block the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d, the cavity 32a is formed in the CF-based deposit attached inside the first opening patterns 15a, 15b, 15c, and 15d. There is no problem.

Next, as shown in FIG. 3B, a resist is applied on the second insulating film 32 by spin coating and baked to form a resist film 33 having a thickness of about 300 nm.
At this time, since the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d arranged in a sparse and dense manner are blocked by the second insulating film 32, the information on the density of the basal pattern is masked. The resist film 33 having a uniform thickness can be formed without being affected by the density.

Next, organic silicon is applied on the resist film 33 formed to a uniform thickness by spin coating, and baked to form a silicon oxide film 34.
Next, a resist is applied on the silicon oxide film 34 by spin coating, and baked to form a resist film 35.

  Next, the resist film 35 is patterned by a photolithography method to form a plurality of second opening patterns 35a, 35b, 35c, 35d at positions facing the first opening patterns 15a, 15b, 15c, 15d.

Next, as shown in FIG. 3C, using the resist film 35 having the second opening patterns 35a, 35b, 35c, and 35d as a mask, for example, CHF ₃ , C ₄ F ₈ , Ar, and O ₂ are used as process gases. Plasma treatment using the mixed gas is performed, the silicon oxide film 34 and the resist film 33 are etched, and the second insulating film 32 is exposed.
Thereby, the second mask material 36 having the second opening patterns 36a, 36b, 36c, and 36d arranged in a sparse and dense manner is formed.

Next, as shown in FIG. 4A, plasma treatment using a mixed gas containing, for example, C ₄ F ₈ , Ar, and O ₂ as a process gas is performed using the second mask material 36 to form the first opening. The second insulating film 32 that covers the upper surfaces of the patterns 15a, 15b, 15c, and 15d is etched.

Next, as shown in FIG. 4B, using the second mask material 36, for example, a plasma treatment using a mixed gas containing CH ₂ F ₂ , C ₄ F ₈ , Ar, and O ₂ as a process gas is performed. The first insulating film 15 is etched to a predetermined depth L3 (corresponding to the thickness of the second wiring 17) to form second opening patterns 15e, 15f, 15g, and 15h.
At the same time, the second insulating film 32 attached to the inside of the first opening patterns 15a, 15b, 15c, and 15d is also etched to the depth L3.

Next, as shown in FIG. 4C, for example, plasma treatment (ashing) is performed with O ₂ gas as a process gas, and the second insulation adhered inside the first opening patterns 15a, 15b, 15c, and 15d. The film 32 is etched to expose the insulating film 13.
At the same time, for example, plasma processing (ashing) is performed using O ₂ gas as a process gas, and the remaining portion of the resist film 33 and the second insulating film 32 left under the resist film 33 are etched.
The insulating film 13 serves as an etching stopper so that damage caused by etching does not reach the first wiring 12.

  Thus, the first insulating film 15 having the first opening patterns 15a, 15b, 15c, and 15d as the hole patterns on the lower side and the second opening patterns 15e, 15f, 15g, and 15h as the trench patterns on the upper side is formed. The

  Next, the insulating film 13 is etched by RIE to expose the first wiring 12, and then into the first opening patterns 15a, 15b, 15c, and 15d and the second opening patterns 15e, 15f, 15g, and 15h. A conductive material such as copper is embedded. Thereby, the via contact 16 and the second wiring 17 are formed.

  FIG. 5 is a diagram showing the pattern shape of the present example in comparison with the comparative example, FIG. 5A is a diagram showing the pattern shape of the present example, and FIG. 5B is a diagram showing the pattern shape of the comparative example. It is. FIG. 6 is a cross-sectional view sequentially showing the main part of the manufacturing process of the comparative example.

  Here, the comparative example shows a case where there is no step of forming the second insulating film 32 on the first insulating film 15 by closing the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d that are densely arranged. ing. First, the manufacturing process of the comparative example will be described.

  As shown in FIG. 6A, in the comparative example, a resist is applied by spin coating on the first insulating film 15 having the plurality of first opening patterns 15a, 15b, 15c, and 15d that are arranged densely and densely. In some cases, the second insulating film 32 formed on the first insulating film 15 is not provided by closing the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d that are densely arranged.

For this reason, the information on the density of the underlying pattern is not masked, and the resist film thickness on the densely arranged first opening patterns 15a, 15b, and 15c becomes thin, and on the sparsely arranged first opening pattern 15d. The resist film thickness increases. As a result, a resist film 61 having a non-uniform film thickness is formed.
The non-uniformity of the resist film thickness depends on the viscosity of the resist to be applied and the spin coating rotation speed, but is caused by the supplied resist being absorbed inside the first opening patterns 15a, 15b, 15c, and 15d. It is.

Next, a silicon oxide film 62 is formed on the resist film 61 formed to have a nonuniform thickness, and a resist film 63 is formed on the silicon oxide film 62.
Next, the resist film 63 is patterned by a photolithography method to form a plurality of second opening patterns 63a, 63b, 63c, and 63d at positions facing the first opening patterns 15a, 15b, 15c, and 15d.

Next, as shown in FIG. 6B, using the resist film 63 having the second opening patterns 63a, 63b, 63c, and 63d as a mask, for example, CHF ₃ , C ₄ F ₈ , Ar, and O ₂ are used as process gases. The silicon oxide film 62 and the resist film 61 are etched by performing plasma treatment using a mixed gas containing the mixed gas.
Thereby, the second mask material 64 having the second opening patterns 63a, 63b, 63c, and 63d arranged in a sparse and dense manner is formed.

At this time, since the second insulating film 32 serving as an etching stopper does not exist, the resist film 63 disappears, and the first opening pattern 15a of the first insulating film 15 reflects the film thickness non-uniformity of the resist film 61. The upper portion of the resist 61 filled in 15b, 15c, and 15d is also etched.
Thereby, the resist film 61a of the first opening patterns 15a, 15b, and 15c arranged densely is thin, and the resist film 61b of the first opening pattern 15d arranged sparsely is thick and non-uniform.

Next, as shown in FIG. 6C, plasma processing using a mixed gas containing, for example, CH ₂ F ₂ , C ₄ F ₈ , Ar, CO, and O ₂ as process gases is performed using the second mask material 64. Then, the first insulating film 15 is etched to a depth L3 to form second opening patterns 15e, 15f, 15g, and 15h.
At the same time, the resists 61a and 61b filled in the first opening patterns 15a, 15b, 15c and 15d are also etched.

At this time, the etching rate of the first insulating film 15 is higher than the etching rate of the resist film 61 due to the difference in selectivity, so that the etching amount of the first insulating film 15 is larger than the etching amount of the resist film 61.
As a result, in the sparsely arranged second opening patterns 15h, since the film thickness difference L4 between the first insulating film 15 and the resist film 61b at the start of etching is small, the thickness of the resist film 61b is the first insulating film 15 Greater than the thickness of
When the thickness of the resist film 61 is larger than the thickness of the first insulating film 15, the etching product is deposited inside the first opening pattern 15h, and a fence-like deposit 65 is generated.

  Further, in the densely arranged second opening patterns 15e, 15f, and 15g, since the film thickness difference L5 between the first insulating film 15 and the resist film 61 at the start of etching is large, the resist film 61a disappears, and the insulating film 13 is etched, and the first wiring 12 may be damaged.

  Therefore, as shown in FIG. 5B, in the comparative example, a pattern shape in which unnecessary fence-like deposits 65 are generated around the sparsely arranged first opening patterns 15d is obtained.

  On the other hand, as shown in FIG. 5A, in this embodiment, since the thickness of the second insulating film 32 adhered in the first opening patterns 15a, 15b, 15c, and 15d is uniform, a fence-like deposition is performed. An accurate pattern shape without the object 65 is obtained.

  Furthermore, the second insulating film 32 that is desired to remain on the bottom of the first opening patterns 15a, 15b, 15c, and 15d can be secured so that the insulating film 13 is not etched and damages the first wiring 12.

  As described above, in the pattern forming method of the present embodiment, the second insulating film 32 is formed on the first insulating film 15 by closing the upper surfaces of the first opening patterns 15a, 15b, 15c, and 15d that are densely arranged. The process to perform is comprised.

As a result, since the information on the underlying pattern is masked by the second insulating film 32, a resist film 33 having a uniform thickness is formed on the second insulating film 32 without being affected by the density of the underlying pattern. can do.
Accordingly, it is possible to obtain a pattern forming method capable of accurately forming a plurality of densely arranged patterns.

  Here, a case has been described in which the densely arranged first opening patterns are hole patterns and the second opening patterns are trench patterns, but other patterns may be used.

  Although the case where the etching of the first insulating film 15, the removal of the first mask material 31, and the formation of the second insulating film 32 are performed by adjusting the process gas and performing the plasma treatment in the same reaction vessel has been described, You may do it individually.

  Although the case where the first wiring 12 and the second wiring 17 are connected via the via contact 16 in which copper is embedded in the first opening pattern has been described, a copper film is formed on the inner surface of the first opening pattern. It is also possible to connect via a through hole.

FIGS. 1A and 1B are cross-sectional views of a semiconductor device using a pattern forming method according to a first embodiment of the present invention, and FIG. 1B is a perspective view of a main part thereof. Sectional drawing which shows the pattern formation process which concerns on Example 1 of this invention in order. Sectional drawing which shows the pattern formation process which concerns on Example 1 of this invention in order. Sectional drawing which shows the pattern formation process which concerns on Example 1 of this invention in order. FIG. 5A is a diagram showing a pattern shape according to Example 1 of the present invention in comparison with a comparative example, FIG. 5A is a diagram showing the pattern shape of the present example, and FIG. 5B is a pattern shape of the comparative example. Figure. Sectional drawing which shows the principal part of the pattern formation process of the comparative example of this invention in order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multilayer wiring 11 Insulating film 12 1st wiring 13 Insulating film 14 Substrate 15 1st insulating films 15a-15d, 31a-31d 1st opening pattern 15e-15h, 35a-35d, 36a-36d, 63a-63d 2nd opening pattern 16 Via contact 17 Second wiring 18 Protective film 31 First mask material 32 Second insulating film 32a Cavity 33, 35, 61, 63 Resist film 34, 62 Silicon oxide film 36, 64 Second mask material 65 Fence-like deposit

Claims (5)

A first insulating film is formed on the substrate, a first mask material having a plurality of first opening patterns arranged densely on the first insulating film is formed, and the first mask material is used to form the first mask material. Etching the insulating film to transfer the plurality of first opening patterns;
Removing the first mask material, closing upper surfaces of the plurality of first opening patterns, and forming a second insulating film made of a material different from the first insulating film on the first insulating film;
A second mask material having a plurality of second opening patterns facing the plurality of first opening patterns is formed on the second insulating film, and the second insulating film is etched using the second mask material. Etching the first insulating film to a predetermined depth using the second mask material;
The pattern formation method characterized by comprising.   The plurality of densely arranged first opening patterns includes the first opening pattern arranged at a first pitch and the first opening pattern arranged at a second pitch larger than the first pitch. The pattern forming method according to claim 1.   The pattern forming method according to claim 1, wherein the first opening pattern is a hole pattern, and the second opening pattern is a trench pattern. The pattern forming method according to claim 1, wherein the second insulating film is formed by plasma treatment using a gas containing CH ₂ F ₂ and C ₄ F ₈ .   The etching of the first insulating film, the removal of the first mask material, and the formation of the second insulating film are performed by plasma processing in the same reaction vessel by adjusting a process gas. Item 4. The pattern forming method according to Item 1.

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