JP2009230615A - Image processor, image processing system, and head-up display system for vehicle - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor or the like for executing relatively quickly processing for generating a pixel data constituting the second image based on a pixel data constituting the first image. <P>SOLUTION: This image processor 10 includes a bus interface part 400 for interface-processing a bus 40 connected to a storage device stored with a pixel data of the first image, and an image data generation processing part 300 for transmitting a request signal of requesting the pixel data of the first image to the bus interface part, and for generating the data of the pixel of the second image, based on the data of the pixel data of the first image received from the bus interface part. The bus interface part transmits the first acknowledge signal to the image data generation processing part, when receiving the request signal from the image data generation processing part, and sets a bus possessory right to the bus 40, when the image data generation processing part transmits continuously the request signal after transmitting the first acknowledge signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing device, an image processing system, and a vehicle head-up display system.

There is provided an image processing apparatus that generates an output image by applying various arithmetic processes such as distortion, enlargement, reduction, rotation, and reversal to an input image. For example, in a head-up display system for a vehicle, various types of information are displayed on the windshield in order to reduce the movement distance of the driver's line of sight during travel. However, since the surface of the windshield is curved or installed perpendicular to the driver's eyes, the image projected on the windshield surface by the image display device is distorted. For example, when the rectangular image 900 shown in FIG. 13A is displayed on the surface of the windshield, an image 902 displayed on the surface of the windshield by the image display device 910 as shown in FIG. Causes distortion. Therefore, an image as shown in FIG. 13C in which the image 900 of FIG. 13A is distorted in the reverse direction in advance with respect to the distortion generated according to the shape of the surface of the windshield and the position of the driver's eye line. An image processing apparatus that generates 904 has been proposed.
Japanese Patent Laid-Open No. 11-30764

  In an image processing apparatus that generates an output image by performing various arithmetic processes on such an input image, for example, pixel data of the input image is stored in a storage device external to the image processing device, and is stored via a bus. The pixel data of the output image is generated while sequentially reading out necessary pixel data. Here, in a storage device such as SDRAM, burst read is possible when reading pixel data continuously from continuous addresses, and header processing is not required for reading the second and subsequent pixel data, so latency is reduced. Can be zero. That is, if burst read is possible, the pixel data read time can be shortened, so that the processing speed of the image processing apparatus can be increased.

  However, for example, when an image processing apparatus generates an output image that has been distorted in advance, as in a head-up display system for a vehicle, for each pixel data of the output image, the input image necessary for the generation is determined. The number of pixel data and relative coordinates change. Therefore, there are many cases where pixel data cannot be read continuously from consecutive addresses, and single read is likely to occur. On the other hand, when the number of devices connected to the bus increases, the time during which the bus can be occupied for data communication between the image processing apparatus and the storage device becomes relatively short. Therefore, if the bus is released every time the image processing apparatus performs a single read, there is no guarantee that the right to occupy the bus can be secured for the next single read, and reception of necessary pixel data of the input image is awaited. Cannot be generated at an appropriate timing, resulting in a decrease in processing speed of the image processing apparatus.

  The present invention has been made in view of the above problems, and by improving the efficiency of the process of reading out the pixel data constituting the first image from the storage device, the pixel data constituting the first image. An object of the present invention is to provide an image processing device, an image processing system, and a vehicle head-up display system that can perform processing for generating pixel data constituting a second image at a relatively high speed.

(1) The present invention
An image processing apparatus that generates data of pixels constituting a second image based on data of pixels constituting a first image,
A bus interface unit that performs an interface process with respect to a bus that can set a bus occupancy right to which a storage device in which pixel data of the first image is stored is connected;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. When transmission is continued, a bus occupation right is set for the bus.

  The data of the pixels constituting the first image and the data of the pixels constituting the second pixel may be RGB data or luminance data, for example.

  The external storage device may be a burst readable storage device such as an SDRAM (Synchronous Dynamic Random Access Memory).

  According to the present invention, the image data generation processing unit transmits a request signal when requesting pixel data of the first image. That is, the image data generation processing unit transmits a request signal when requesting the next data even after receiving the first acknowledge signal. Therefore, the bus interface unit can determine whether the image data generation processing unit further requests data by transmitting the first acknowledge signal. Then, when the image data generation processing unit requests more data, the bus interface unit sets the bus occupation right to the bus until the data request is completed. That is, the bus can be occupied while the image data generation processing unit continues to request the pixel data of the first image. Therefore, according to the present invention, the process of generating the pixel data constituting the second image based on the pixel data constituting the first image can be performed at a relatively high speed.

  Further, according to the present invention, when a plurality of data can be burst read from the storage device, the latency for reading the second and subsequent data can be eliminated by occupying the bus. Can be made faster.

  According to the present invention, when the image data generation processing unit requests only one data, the request signal is not transmitted after receiving the first acknowledge signal, so the bus interface unit sets the bus occupation right to the bus. do not do. Therefore, according to the present invention, when only one pixel data is read from the storage device, the bus is not occupied unnecessarily, so that the bus can be effectively used by another device connected to the bus.

(2) In the image processing apparatus of the present invention,
The image data generation processing unit
Based on the first acknowledge signal, an address for reading pixel data of the first image from the storage device may be generated.

  According to the present invention, the image data generation processing unit reads the pixel data of the first image based on the first acknowledge signal before the bus interface unit receives the acknowledge signal from the storage device via the bus. The processing for generating the address for this can be performed. Therefore, the image generation process can be further speeded up.

(3) In the image processing apparatus of the present invention,
The bus interface unit
When the request signal is received, a request signal for requesting pixel data of the first image is transmitted to the storage device via the bus, and a request signal is received based on the acknowledge signal received from the storage device via the bus. 2 acknowledge signal is transmitted to the image data generation processing unit,
The image data generation processing unit
The pixel data of the first image may be received based on the second acknowledge signal.

(4) In the image processing apparatus of the present invention,
The image data generation processing unit
Until the number of the first acknowledge signals equal to the number of pixel data of the first image necessary for generating the data of n (n ≧ 1) pixels of the second image is received. You may make it continue transmitting a request signal.

  According to the present invention, the bus can be occupied until all the pixel data of the first image that needs to be read from the storage device to generate the n pixel data of the second image is read. Therefore, the process of generating n pixel data of the second image can be performed without stopping midway.

  Further, according to the present invention, the bus can be released as soon as all the pixel data of the first image that needs to be read from the storage device to generate the n pixel data of the second image is read. . Therefore, it is possible to prevent the operation of other devices connected to the bus from being stopped more than necessary.

(5) In the image processing apparatus of the present invention,
The image data generation processing unit
A determination processing unit that determines the number of pixel data of the first image necessary to generate data of n pixels of the second image;
A status buffer for storing a determination result of the determination processing unit;
An address buffer for storing an address for reading out pixel data of the first image from the storage device based on a determination result of the determination processing unit;
And a data buffer for storing pixel data of the first image read from the storage device.

(6) In the image processing apparatus of the present invention,
The image data generation processing unit
Including three status buffers, two address buffers, and two data buffers, and a process of generating data of n pixels of the second image in a first stage, a second stage, and a second stage In the first stage, the determination result is stored in the status buffer and the address is stored in the address buffer. In the second stage, the pixel of the first image is stored in the data buffer. Of the second image based on the determination result stored in the status buffer and the pixel data of the first image stored in the data buffer in the third stage. A process of generating data for n pixels is performed, and three processes are performed for each n pixel data of the second image. The status buffer, two of said address buffer and two respectively to cycle through the data buffer the first stage, may perform processing of the second stage and the third stage.

  According to the present invention, the writing process to the address buffer is performed in the first stage, and the reading process from the address buffer is performed in the second stage. Therefore, the image data read interface unit 330 includes two address buffers so as not to stop the image data generation process. Similarly, the writing process to the data buffer is performed in the second stage, and the reading process from the data buffer is performed in the third stage. Therefore, the image data read interface unit 330 includes two data buffers so as not to stop the image data generation process. On the other hand, the writing process to the status buffer is performed in the first stage, and the reading process from the status buffer is performed in the third stage. Therefore, the image data read interface unit 330 includes three status buffers so as not to stop the image data generation process.

  Therefore, according to the present invention, n pixel data generation processing is divided into three stages, and three sets of n pixel data generation processing are simultaneously performed while shifting one stage at a time. Can be

(7) The present invention
An image processing device for generating data of pixels constituting the second image based on data of pixels constituting the first image;
A storage device storing pixel data of the first image;
A bus capable of setting a bus occupation right to which the image processing device and the storage device are connected, and
The image processing apparatus includes:
A bus interface unit that performs interface processing with respect to the bus;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. When the transmission is continued, a bus occupation right is set for the bus.

(8) The present invention
An image processing device for generating data of pixels constituting the second image based on data of pixels constituting the first image;
A storage device storing pixel data of the first image;
A bus capable of setting a bus occupation right to which the image processing device and the storage device are connected;
An image display device that displays the second image on a windshield based on pixel data generated by the image processing device,
The image processing apparatus includes:
A bus interface unit that performs interface processing with respect to the bus;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. In the vehicle head-up display system, when the transmission is continued, a bus occupation right is set for the bus.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Image Processing Device and Image Processing System FIG. 1 is a diagram for explaining a configuration example of an image processing device and an image processing system of the present embodiment.

  The image processing system 1 includes an image processing apparatus 10 and an SDRAM 20. In addition, the image processing system 1 may include a bus 40 to which the image processing apparatus 10, SDRAM 20, and other devices 30 are connected. The bus 40 is a bus capable of setting a bus occupation right. The image processing system 1 may include an LCD 50.

  The image processing apparatus 10 uses the pixel data (hereinafter referred to as pixel data of the first image) constituting the first image (hereinafter referred to as pixel data of the second image). Data). The pixel data of the first image is stored in, for example, the SDRAM 20 or other storage device (not shown), and the image processing device 10 receives the first image from the SDRAM 20 or other storage device (not shown) via the bus 40. The device 30 (for example, a microprocessor) may be configured to supply pixel data of the first image to the image processing apparatus 10 via the bus 40. May be. The second image is an image 52 displayed on the LCD 50, for example.

  The SDRAM 20 is a burst readable storage device, and corresponds to a pixel (hereinafter referred to as a vertex pixel) located at each vertex of a plurality of rectangular blocks obtained by dividing the second image in a grid pattern in the row direction and the column direction. Position specifying data for specifying the position of the pixel of the first image may be stored. The position specifying data may be coordinate data of a pixel of the second image corresponding to each vertex pixel of the second image, or the coordinates of each vertex pixel of the second image and the first corresponding to the pixel. The offset data may represent the difference from the pixel coordinates of the image.

  The image processing apparatus 10 includes at least an image data generation processing unit 300 and a bus interface unit 400. Further, the image processing apparatus 10 may include a memory interface unit 100, an SRAM 200, and an LCD controller 500.

  The memory interface unit 100 reads out the position specifying data of the vertex pixels in each row of the second image from the SDRAM 20 in a burst manner, and reads the position specifying data of the vertex pixels of at least two rows of the second image. You may make it perform the process stored in SRAM200.

  The image data generation processing unit 300 transmits a request signal for requesting pixel data of the first image to the bus interface unit 400, and the second data based on the pixel data of the first image received from the bus interface unit 400. A process of generating pixel data of the image is performed.

  Further, the image data generation processing unit 300 specifies the position of the pixel of the first image based on the position specifying data stored in the SRAM 200, and blocks the pixel data of the second image based on the data of the pixel. You may make it perform the process produced | generated in order for every. The image data generation processing unit 300 may generate pixel data of a second image obtained by performing arbitrary conversion processing on the first image, for example, enlargement, reduction, rotation, inversion, distortion correction, and the like. Good.

  The pixel data 302 generated by the image data generation processing unit 300 is converted into the drive signal 12 of the LCD 50 by the LCD controller 500 and output, for example. The LCD 50 displays an image (second image) 52 based on the drive signal 12. The LCD controller 500 may be outside the image processing apparatus 10.

  The bus interface unit 400 performs interface processing for the bus 40. For example, the bus interface unit 400 transmits a request signal or an address signal for requesting position specifying data or pixel data of the first image to the SDRAM 20 or the like via the bus 40, and acknowledges from the SDRAM 20 or the like via the bus 40. A process of receiving position specifying data and pixel data of the first image is performed together with the signal.

  When a device (device 30 or the like) other than the image processing apparatus 10 and the SDRAM 20 is connected to the bus 40, the bus interface unit 400 receives the request signal from the image data generation processing unit 300 and performs image data generation processing. When the first acknowledge signal is transmitted to the unit 300 and the image data generation processing unit 300 continues to transmit the request signal even after the transmission of the first acknowledge signal, processing for setting the bus occupation right to the bus 40 is performed. .

  FIG. 2 is a diagram for explaining a state in which an image (second image) configured by pixels having pixel data generated by the image processing apparatus of the present embodiment is divided into a plurality of blocks. Hereinafter, FIG. 2 will be described with reference to FIG.

The second image 52 is a VGA size image, for example, and is composed of 640 × 480 pixels. In FIG. 2, the coordinates of the pixel located at the intersection of the x column and the y row are represented as (x, y), and the pixel at the coordinate _{(x, y)} is represented as p _{(x, y)} . The second image 52 is divided into 4800 (80 × 60) rectangular blocks B _{(0,0) to} B _(59,79) in a grid pattern in the row direction and the column direction. Here, if the distance between two pixels is 1, the block B _{(i, j)} (i = 0 to 78, j = 0 to 58) is 8 × 8 in size, and 9 × 9 pixels are Contains. At the positions of the four vertices of the block B _{(i, j)} (i = 0 to 78, j = 0 to 58), vertex pixels p _{(8i, 8j)} , p _{(8 (i + 1), 8j)} , p _{( 8i, 8 (j + 1))} , p _{(8 (i + 1), 8 (j + 1))} . For example, vertex pixels p _(0,0) , p _(8,0) , p _(0,8) , and p _(8,8) exist at the positions of the four vertices of the block B _(0,0) .

On the other hand, no pixel exists on the right side of the block B _{(79, j)} (j = 0 to 58) existing at the right end in FIG. Therefore, the block B _{(79, j)} (j = 0 to 58) has a size of 8 × 8, but includes only 8 × 9 pixels. Then, vertex pixels p _(632,8j) and p _{(632,8 (j + 1))} exist at the positions of the two vertices on the left side of each of the blocks B _{(79, j)} (j = 0 to 58). However, there is no vertex pixel at the position of the two vertices on the right side. Therefore, dummy vertex pixels d _(640,8j) and d _{( 640,8 (j + 1))} exist at the two vertices on the right side of each of the blocks B _{(79, j)} (j = 0 to 58). Think of it.

Similarly, no pixel exists on the lower side of the block B _{(i, 59)} (i = 0 to 78) existing at the lower end. Accordingly, the block B _{(i, 59)} (i = 0 to 78) has a size of 8 × 8, but includes only 9 × 8 pixels. Then, vertex pixels p _{(8i, 472)} and p _{(8 (i + 1), 472)} exist at the positions of the two vertices on the upper side of each of the blocks B _{(i, 59)} (i = 0 to 78). However, there is no vertex pixel at the position of the two vertices on the lower side. Therefore, dummy vertex pixels d _{(8i, 480)} and d _{(8 (i + 1), 480)} exist at the two vertices on the lower side of each of the blocks B _{(i, 59)} (i = 0 to 78). I think to do.

Further, the block B _{(79, 59)} is 8 × 8 in size but includes only 8 × 8 pixels. A vertex pixel p _{(632, 472)} exists at the position of the upper left vertex of the block B _{(79, 59),} but no vertex pixel exists at the positions of the upper right, lower left, and lower right vertices. Therefore, dummy vertex pixels d _(640,472) , d _(632,480), and d _(640,480) exist at the three vertices at the upper right, lower left, and lower right of the block B _(79,59) , respectively. Think of things.

  As described above, by assuming the presence of dummy vertex pixels in the rightmost block and the lowermost block, the calculation processing by the image data generation processing unit 300 is performed in the rightmost block and the lowermost block in the same manner as other blocks. Can do.

In FIG. 2, two blocks adjacent in the row direction share pixels existing on one side. For example, the block B _{(0, 0)} and the block B _{(1, 0)} adjacent in the row direction share nine pixels p _{(8, j)} (j = 0 to 8) existing on the adjacent sides. As a result, the block B _(0,0) and the block B _(1,0) share the two vertex pixels p _(8,0) and p _(8,8) existing on the adjacent sides.

In FIG. 2, two blocks adjacent in the column direction share pixels existing on one side. For example, the block B _(0,0) and the block B _(0,1) adjacent in the column direction share the pixel p _{(i, 8)} (i = 0 to 8). As a result, the block B _(0,0) and the block B _(0,1) share the two vertex pixels p _(0,8) and p _(8,8) present on the adjacent sides.

Hereinafter, a row in which vertex pixels (including dummy vertex pixels) of each block exist is referred to as a block line. That is, as shown in FIG. 2, each block line BL _j (j = 0 to 59) has vertices existing at the positions of the vertices on the upper side of each of the blocks B _{(i, j)} (i = 0 to 79). There are pixels p _{(8i, 8j)} (i = 0-79) and dummy vertex pixels d _(640,8j) . The block line BL ₆₀ includes dummy vertex pixels d _{(8i, 480)} (i = 0 to 80).

  Note that the second image 52 may be an image of any size, and the image processing apparatus 10 may be capable of variably setting the size of the second image 52.

  Further, one block that divides the second image 52 may be a block of any size, and the shape of the block may be a square or a rectangle. For example, it may be a block having a size of 2 × 2, 4 × 4, 2 × 4, 4 × 2, 4 × 8, or the like.

  Furthermore, the image processing apparatus 10 includes a first setting register for setting information for specifying the number of pixels in the row direction included in each of the blocks of the second image 52, and each of the blocks of the second image. And a second setting register for setting information specifying the number of pixels in the column direction included. In this case, the image data generation processing unit 300 calculates the number of pixels in the row direction and the number of pixels in the column direction of the block of the second image based on the setting value of the first setting register and the setting value of the second setting register. The pixel data of the second image may be generated in order for each block.

The rightmost block B _{(79, j)} (j = 0 to 58) is a 7 × 8 block, and the lowermost block B _{(i, 59)} (i = 0 to 78) is 8 × 7. By _setting the size of the lower right block B _{(79, 59)} to a 7 × 7 size block, the dummy vertex pixels need not be considered. In this way, when the rightmost block and the lowermost block have different sizes from the other blocks, the calculation processing of the rightmost block and the lowermost block by the image data generation processing unit 300 is different from the calculation processing of the other blocks. You can do it.

For example, when the pixel at the coordinates (x1, y1) of the first image is used as the vertex pixel p _{(x2, y2) at} the coordinates (x2, y2) of the second image 52, the first image The pixel at the coordinate (x1, y1) is associated with the vertex pixel p _{(x2, y2)} . In this case, the offset data of the vertex pixel p _(x2, y2) is given as (x1-x2, y1-y2), for example.

FIG. 3 is a diagram for explaining an example of offset data (an example of position specifying data) stored in the SDRAM. As shown in FIG. 3, the SDRAM 20, the first corresponding to the vertex pixel _{p (8i, 0) (i} = 0~79) and dummy vertex pixel _{d (640, 0)} that exists on the block line BL ₀ Offset data for specifying the position of the pixel of the image is continuously stored at addresses 00000000H to 00000050H. In addition, the SDRAM 20, the pixels in the first image corresponding to the vertex pixel _{p (8i, 8) (i} = 0~79) and dummy vertex pixel _{d (640,8)} present on the block line BL ₁ Offset data for specifying the position is continuously stored at addresses 00000060H to 000000B0H. Similarly, the vertex pixels and dummy vertex pixels respectively existing on the block lines BL _{2 to} BL ₅₉ are stored at consecutive addresses of the SDRAM 20, and the dummy vertex pixels d _{(8i, 8)} existing on the block line BL ₆₀ are similarly stored _{. 480)} Offset data for specifying the position of the pixel of the first image corresponding to (i = 0 to 80) is continuously stored at addresses 00001680H to 000016D0H.

  As described above, by storing the offset data of the vertex pixels and the offset data of the dummy vertex pixels existing on one block line at successive addresses of the SDRAM 20, the burst read function of the SDRAM 20 can be used. . For example, when the SDRAM 20 is set to be capable of burst reading of 16 pieces of offset data, latency is required for reading the first offset data, but for reading the 2nd to 16th pieces of offset data. Does not require latency. Therefore, it is possible to speed up the process in which the image processing apparatus 10 reads offset data for one block line from the SDRAM 20.

  FIG. 4 is a diagram for explaining a configuration example of the memory interface unit. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  The memory interface unit 100 includes a bus read address generation unit 110, a memory counter unit 120, a memory address generation unit 130, a buffer 1-1 (140), a buffer 1-2 (150), a buffer 1-3 (160), and a buffer 1 -4 (170) and the control unit 180. The buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170) function as four first buffers.

  The bus read address generation unit 110 generates an address signal 112 for reading the offset data stored in the SDRAM 20 and outputs it to the bus interface unit 400.

  The memory counter unit 120 includes counters such as a burst read counter, a block counter, a line counter, and a block line counter, and supplies these counter values to the address generation unit 110 and the memory address generation unit 130.

  The memory address generation unit 130 performs processing for generating an address signal 132 (write address or read address) for the SRAM 200 based on the count value supplied by the memory counter unit 120. The offset data 402 is written at the address of the SRAM 200 specified by the address signal 132 (write address).

  The offset data 202 read from the address of the SRAM 200 designated by the address signal 132 (read address) is buffer 1-1 (140), buffer 1-2 (150), buffer 1-3 (160), buffer 1- 4 (170).

The memory interface unit 100 uses vertex pixels p _{(8i, 8j)} , p ₍ 4) located at the four vertices of each block B _{(i, j)} (i = 0 to 79, j = 0 to 59) of the second image. _{8 (i + 1), 8j)} , p _{(8i, 8 (j + 1))} , p _{(8 (i + 1), 8 (j + 1))} offset data is read from the SRAM 200 and buffer 1-1 (140), buffer 1-2 (150), buffer 1-3 (160), and buffer 1-4 (170) may be stored respectively.

Furthermore, when the memory interface unit 100 reads out from the SRAM 200 the offset data of the vertex pixel of the block adjacent in the column direction to the block from which the offset data was previously read, the two vertex pixels shared by the two blocks are shared. The offset data of the other two vertex pixels are read from the SRAM 200 so that the offset data of the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1- 4 (170) may be stored in each of the two buffers. For example, the memory interface unit 100 uses the four vertex pixels p _(0,0) , p _(8,0) , p _(0,8) , and p _(8,8) offsets of the block B _(0,0). In the state where data is read from the SRAM 200 and stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170), respectively, the block B _{( 0,0)} and four vertex pixels p _(8,0) , p _(16,0) , p _(8,8) , p _(16,8) of block B _(1,0) adjacent in the column direction When the offset data is read from the SRAM 200, the offset data of the two vertex pixels p _(8,0) and p _(8,8) shared by the two blocks B _(0,0) and B _(1,0) are stored. as but not overwritten, the other two vertices pixel p _{(16, 0} And buffer 1-1 (140) reads the offset data from SRAM200 of _{p (16, 8)} and may be respectively stored in the buffer 1-3 (160). Further, the memory interface unit 100 stores the offset data of the two vertex pixels p _{(8, 0)} and p _{(8, 8)} stored in the buffer 1-2 (150) and the buffer 1-4 (170), respectively. After transferring to the buffer 1-1 (140) and the buffer 1-3 (160), the offset data of the other two vertex pixels p _(16,0) and p _(16,8) are read from the SRAM 200 and buffer 1- 2 (150) and buffer 1-4 (170), respectively.

  The control unit 180 transmits a request signal for requesting reading of offset data stored in the SDRAM 20 to the bus interface unit 400, receives an acknowledge signal from the bus interface unit 400, and operates the bus read address generation unit 110. The timing and operation timing of the memory counter unit 120 are controlled. In addition, the control unit 180 receives a request signal for requesting reading of offset data stored in the SRAM 200 by the image data generation processing unit 300, transmits an acknowledge signal to the image data generation processing unit 300, and a memory counter unit. The operation timing of 120 is controlled.

  FIG. 5 is a diagram for explaining a configuration example of the image data generation processing unit. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  The image data generation processing unit 300 includes an offset data read interface unit 310, a coordinate calculation processing unit 320, an image data read interface unit 330, and a FIFO 340.

  The offset data read interface unit 310 includes a control unit 350, an H counter (pixel counter) 352, a V counter (line counter) 354, a buffer 2-1 (356), a buffer 2-2 (358), and a buffer 2-3 (360). ) And a buffer 2-4 (362). The buffer 2-1 (356), the buffer 2-2 (358), the buffer 2-3 (360), and the buffer 2-4 (362) function as a second buffer.

  The control unit 350 transmits a request signal for requesting reading of the offset data stored in the SRAM 200 to the memory interface unit 100. In addition, the control unit 350 instructs the coordinate calculation processing unit 320 to start coordinate calculation processing described later for each block.

  The H counter 352 and the V counter 354 specify the coordinates of the pixel for which pixel data is to be generated. That is, the H counter 352 functions as a pixel counter that counts the number of pixels included in each row of the second image, and the V counter 354 functions as a line counter that counts the number of rows of the second image.

  When the control unit 350 receives an acknowledge signal for the request signal from the memory interface unit 100, the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), the buffer 1 of the memory interface unit 100 are received. -4 (170) stores offset data 142, 152, 162, and 172 as buffers 2-1 (356), buffers 2-2 (358), buffers 2-3 (360), and buffers 2-4 (362). ). Here, the memory interface unit 100 immediately after the offset data is taken into the buffer 2-1 (356), the buffer 2-2 (358), the buffer 2-3 (360), and the buffer 2-4 (362), The offset data of the four vertex pixels of the next calculation target block are respectively stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170). You may do it.

  When the coordinate calculation processing unit 320 receives an instruction to start coordinate calculation processing for each block from the control unit 350, the buffer 2-1 (356), the buffer 2-2 (358), the buffer 2-3 (360), and the buffer 2 -4 (362), the coordinate data 322 of the first image corresponding to the pixels included in the block is calculated from the offset data stored in the block 362 (362).

For example, the vertex pixels p _{(Mi, Nj)} and p _{(M (i + 1)} located at the four vertices A, B, C, and D of the block B _{(i, j) having} the size of M × N as shown in FIG. _{, Nj), p (Mi,} N (j + 1)), p (M (i + 1), N (j + 1)) respectively offset data _{(X a, Y a),} (X b, Y b), (X c , Y _c ), (X _d , Y _d ), the column direction of each pixel p _{(Mi + m, Nj + n)} (0 ≦ m <M, 0 ≦ n <N) included in the block B _{(i, j)} The offset value OffsetX (m, n) and the offset value OffsetY (m, n) in the row direction can be calculated by, for example, the following equations (1) and (2), respectively.

ここで、オフセット値OffsetX(ｍ,ｎ)及びOffsetY(ｍ,ｎ)は小数点以下の数字を含んでいてもよい。

Here, the offset values OffsetX (m, n) and OffsetY (m, n) may include numbers after the decimal point.

Further, the x-coordinate X ′ (m, n) and y-coordinate Y ′ (m, n) of the pixel of the first image corresponding to each pixel p _{(Mi + m, Nj + n)} (0 ≦ m <M, 0 ≦ n <N). n) can be calculated by, for example, the following equations (3) and (4), respectively.

ここで、座標値X ’(m,n)、Y ’(m,n)は、小数点以下の数字を含んでいてもよい。座標データ３２２は座標値X ’(m,n)、Y ’(m,n)を含むデータであってもよい。

Here, the coordinate values X ′ (m, n) and Y ′ (m, n) may include numbers after the decimal point. The coordinate data 322 may be data including coordinate values X ′ (m, n) and Y ′ (m, n).

  The image data read interface unit 330 needs to read from the SDRAM 20 based on the n coordinate data calculated by the coordinate calculation processing unit 320 in association with the n (n ≧ 1) pixel data of the second image. A process for sequentially generating addresses of pixel data of a certain first image is performed. Further, the image data read interface unit 330 transmits a request signal and an address signal for requesting pixel data of the first image to the bus interface unit 400, and the first image of the first image is transmitted together with the acknowledge signal from the bus interface unit 400. A process of receiving pixel data is performed. Further, the image data read interface unit 330 generates n pieces of pixel data 332 of the second image based on the pixel data of the first image received from the bus interface unit 400, and sequentially outputs them to the FIFO 340. .

  The FIFO 340 includes a multi-stage buffer (shift register, etc.), stores the pixel data 332 generated by the image data read interface unit 330 in order in the multi-stage buffer, and stores the pixel data 302 stored in the buffer in the order in which they are stored. 500 is output at a constant timing (for example, 60 fps (frame per second)).

  FIG. 7 is a diagram for explaining a configuration example of the image data read interface unit. 7, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.

  The image data read interface unit 330 includes, for example, a FIFO 370, a determination processing unit 372, an address generation unit 374, an address cache 376, an address buffer 0 (378), an address buffer 1 (380), a status buffer 0 (382), and a status buffer 1 (384), status buffer 2 (386), control unit 388, data buffer 0 (390), data buffer 1 (392), data cache 394, and correction calculation processing unit 396.

  The FIFO 370 is configured by an n-stage buffer (shift register or the like), and sequentially stores the n coordinate data 322 generated by the coordinate calculation processing unit 320 in the n-stage buffer, and stores the n coordinate data stored in the buffer. It outputs to the determination process part 372 in the order stored.

  The determination processing unit 372 determines the number of pixel data of the first image read from the SDRAM 20 to generate n pixel data of the second image based on each of the n coordinate data. For example, when the coordinate data indicates coordinates outside the display area of the first image, there is no pixel data of the corresponding first image, and therefore it is not necessary to read out the pixel data from the SDRAM 20. Further, for example, when the correction calculation processing unit 396 performs correction calculation of the nearest neighbor method to generate pixel data of the second image, the pixel of the first image closest to the coordinates specified by the coordinate data It is sufficient to read only the data. Further, for example, when the correction calculation processing unit 396 performs the bilinear correction calculation to generate the pixel data of the second image, 4 of the first image surrounding the point indicated by the coordinates specified by the coordinate data. What is necessary is just to read the data of one pixel. Further, for example, when the correction calculation processing unit 396 performs the bilinear correction calculation to generate the pixel data of the second image, the coordinates specified by the coordinate data are in the row direction or the column direction of the first image. When a point on a straight line connecting two adjacent pixels is indicated, only the data of the two pixels is read, and when the pixel of the first image exists at the coordinates specified by the coordinate data, it corresponds to the pixel Only the data to be read need be read out.

  If the determination processing unit 372 determines that it is necessary to read out pixel data of at least one first image for each of the n pieces of coordinate data, the coordinate generation unit 374 sends each coordinate data To instruct the generation of the read address of the SDRAM 20 from.

  The address generation unit 374 stores the generated address in the address buffer 0 (378) or the address buffer 1 (380). In addition, when the generated address does not exist in the address cache 376, the address generation unit 374 may perform a process of writing the generated address in the address cache 376.

  Further, the determination processing unit 372 determines whether or not pixel data to be read from the SDRAM 20 exists in the address cache 376. The determination processing unit 372 determines that it is not necessary to read pixel data from the SDRAM 20 even when pixel data to be read from the SDRAM 20 exists in the address cache 376.

  Therefore, for example, when the correction calculation processing unit 396 performs the bilinear correction calculation to generate the pixel data of the second image, the number of pixel data read from the SDRAM 20 with respect to one coordinate data is all 0-4. This can happen. That is, for example, when four pixel data of the second image is generated based on four coordinate data (case of n = 4), the number of pixel data read from the SDRAM 20 is any one of 0 to 16 become.

  Further, the determination processing unit 372 stores the determination result in one of the status buffer 0 (382), the status buffer 1 (384), and the status buffer 2 (386).

  The control unit 388 requests the pixel data of the first image from the bus interface unit 400 based on the determination results stored in the status buffer 0 (382), the status buffer 1 (384), and the status buffer 2 (386). A process of transmitting a request signal 389 and receiving a pre-acknowledge signal 404 (first acknowledge signal) and an acknowledge signal 406 (second acknowledge signal) from the bus interface unit 400 is performed. The address generation unit 374 may generate an address for reading the next pixel data of the first image from the SDRAM 20 based on the pre-acknowledge signal 404 (first acknowledge signal) received by the control unit 388. Good.

  When the bus interface unit 400 receives the request signal 389 from the image data generation processing unit 330 (control unit 388), the bus interface unit 400 transmits a pre-acknowledge signal 404 (first acknowledge signal) to the image data generation processing unit 330 (control unit 388). When the image data generation processing unit 330 (control unit 388) continues to transmit the request signal 389 even after transmission of the pre-acknowledge signal 404 (first acknowledge signal), the burst signal 18 is transmitted to the bus 40 and the bus Performs processing to set the exclusive right. The image data generation processing unit 330 (control unit 388) has a number of pre-acknowledge signals 404 (first number) equal to the number of pixel data of the first image read from the SDRAM 20 to generate n pixel data of the second image. The request signal 389 may continue to be transmitted until the first acknowledge signal is received.

  Further, when the bus interface unit 400 receives the request signal 389 from the image data generation processing unit 330 (control unit 388), the bus interface unit 400 transmits the request signal 16 for requesting the pixel data of the first image to the SDRAM 20 via the bus 40. Based on the acknowledge signal 42 received from the SDRAM 20 via the bus 40, an acknowledge signal 406 (second acknowledge signal) is generated and transmitted to the image data generation processing unit 330 (control unit 388).

  In addition, the bus interface unit 400 transmits the pixel data 44 of the first image received from the SDRAM 20 via the bus 40 together with the acknowledge signal 42 to the image data generation processing unit 330. The image data generation processing unit 330 receives the pixel data 408 of the first image based on the acknowledge signal 406 (second acknowledge signal), and uses the pixel data 408 as the data buffer 0 (390) or the data buffer 1 (392). To store.

  The correction calculation processing unit 396 performs predetermined processing based on the pixel data of the first image stored in the data buffer 0 (390) or the data buffer 1 (392) or the pixel data of the first image stored in the data cache 394. The correction calculation is performed to generate n pixel data of the second image in order, and the generated n pixel data 332 is sequentially transmitted to the FIFO 340. Here, when the address generated by the address generation unit 374 exists in the address cache 376, the pixel data of the first image stored in the data cache 394 is used. When the address generated by the address generator 374 does not exist in the address cache 376, the pixel data of the first image stored in the data buffer 0 (390) or the data buffer 1 (392) is used and the data cache is used. 394 is written.

  The correction calculation performed by the correction calculation processing unit 396 is, for example, a nearest neighbor method in which one pixel, two pixels, or four pixels that are closest to the point of the first image indicated by the coordinate data 322 are selected, Any method such as a linear method or a bilinear method may be used.

  FIG. 8 is a timing chart for explaining signal transmission / reception timing between the image data read interface unit and the bus interface unit. Hereinafter, FIG. 8 will be described with reference to FIG.

First, the image data read interface unit 330 at time T _0, the m pixel data of the first image required to generate n pixel data of the second image with respect to the bus interface unit 400 the first request signal 389 (e.g., H-level signal) for requesting pixel data and first pixel data out to transmit an address signal 379 indicating the address a ₀ of SDRAM20 stored.

The bus interface unit 400 receives the request signal 389 and transmits a first pre-acknowledge signal 404 (for example, an H level signal) to the image data read interface unit 330 at times T _{1 to} T ₂ . The bus interface unit 400 receives an address signal 379 indicating the address A _0, is stored in an internal buffer (not shown).

Image data read interface unit 330, first receives a pre-acknowledge signal 404, at time T _2, 2 nd request signal 389 and the two requests pixel data eye pixels to the bus interface unit 400 data transmits the address signal 379 indicating the address _{a 1} of SDRAM20 stored.

At time T ₃ , the bus interface unit 400 stores the request signal 16 (for example, an H level signal) for requesting the first pixel data from the SDRAM 20 via the bus 40 and the first pixel data. It transmits an address signal 14 indicating the address _{a 0} of the are SDRAM 20. Further, at time T ₃ , the bus interface unit 400 receives the request signal 389 requesting the second pixel data, transmits the burst signal 18 (for example, an H level signal) to the bus 40, and acquires the bus occupation right. Set.

SDRAM20 the address _A reads pixel data _{D 0} in first stored in _0, at time _T 4 through T _5, first acknowledge signal 42 to the bus interface unit 400 via the bus 40 ( for example sends an H level signal) and first pixel data D _0.

The bus interface unit 400 receives the first acknowledge signal 42 and the first pixel data D _0, and receives a second pre-acknowledge signal from the image data read interface unit 330 at times T _{4 to} T ₅ . 404 and a first acknowledge signal 406 (for example, an H level signal) are transmitted. The bus interface unit 400 at time _{T 4,} and transmits the first pixel data _{D 0} to the image data read interface unit 330.

Image data read interface unit 330, the second receiving the pre-acknowledge signal 404, at time T _5, 3 nd one request signals 389 and 3 requests the pixel data eye pixels to the bus interface unit 400 data transmits the address signal 379 indicating the address _{a 2} of SDRAM20 stored.

At time T ₅ , the bus interface unit 400 receives the request signal 16 for requesting the second pixel data from the SDRAM 20 via the bus 40 and the address A ₁ of the SDRAM 20 in which the second pixel data is stored. The address signal 14 shown is transmitted.

SDRAM20 reads a second pixel data _{D 1} stored in the address _{A 1,} at time _T 6 through T _7, the second acknowledge signal 42 and the bus interface unit 400 via the bus 40 It transmits second pixel data D _1.

Bus interface unit 400, the second acknowledge signal 42 and the received second pixel data _{D 1,} at time _T 6 through T _7, 3 nd pre acknowledge signal to the image data read interface unit 330 404 and a second acknowledge signal 406 are transmitted. The bus interface unit 400 at time _{T 6,} and transmits the image data read interface unit 330 second pixel data _{D 1.}

Hereinafter the same process is repeated, SDRAM 20 at time _T 8 through T _9, m-1 -th acknowledge signal 42 and m-1 th pixel data _{D m} to the bus interface unit 400 via the bus 40 _-2 is transmitted.

Bus interface unit 400 receives the m-1 th acknowledge signal 42 and m-1 th pixel data _{D m-2,} at time _T 8 through T _9, m with respect to image data read interface unit 330 The first pre-acknowledge signal 404 and the (m-1) th acknowledge signal 406 are transmitted. The bus interface unit 400 at time _{T 8,} and transmits the m-1 th pixel data _{D m-2} to the image data read interface unit 330.

Image data read interface unit 330 receives the m th pre-acknowledge signal 404, at time _{T 9,} and stops the transmission of the request signal 389 to the bus interface unit 400. Bus interface unit 400 at time T _9, and stops transmission of the burst signal 18 cancels the setting of the bus usage right to the bus 40.

At time T ₉ , the bus interface unit 400 sends the request signal 16 for requesting the mth pixel data to the SDRAM 20 via the bus 40 and the address A _{m− of the} SDRAM 20 in which the mth pixel data is stored. An address signal 14 indicating ₁ is transmitted.

The SDRAM 20 reads the _m-th pixel data D _m−1 stored at the address A _m−1, and the _m-th pixel data D _m−1 with respect to the bus interface unit 400 via the bus 40 at times T _{10 to} T ₁₁ . The acknowledge signal 42 and the m-th pixel data D _m−1 are transmitted.

The bus interface unit 400 receives the mth acknowledge signal 42 and the mth pixel data _Dm−1, and receives the mth acknowledge from the image data read interface unit 330 at times T _{10 to} T ₁₁ . A signal 406 is transmitted. The bus interface unit 400 at time _{T 10,} and transmits the pixel data _{D m-1} of the m-th to the image data read interface unit 330.

  As described above, according to the image processing apparatus of the present embodiment, until all the m pieces of pixel data of the first image that need to be read from the SDRAM 20 to generate the n pieces of pixel data of the second image are read. The bus 40 can be occupied. Therefore, the process of generating n pixel data of the second image can be performed without stopping midway.

  Further, according to the image processing apparatus of the present embodiment, as soon as all the m pixel data of the first image that need to be read from the SDRAM 20 to generate the n pixel data of the second image are read out. The bus 40 can be released. Accordingly, it is possible to prevent the operation of other devices connected to the bus 40 from being stopped more than necessary.

  FIG. 9 is a timing chart for explaining access timings for the status buffer, address buffer, and data buffer in the image data read interface unit. Hereinafter, FIG. 9 will be described with reference to FIG.

First, in the period from time T _{0 to} T ₁ , the image data read interface unit 330 displays the _first n pixel data of the second image (for example, when n = 4, p _{(0, 0) in} FIG. 2 _). N determination results determined by the determination processing unit 370 based on the coordinate data of the pixels of the first image corresponding to each of .about.p _(3,0) ) are written in the status buffer 0 (382). Further, in the period of time T _{0 to} T ₁ , the image data read interface unit 330 sets each address of the pixel data of the first image that needs to be read from the SDRAM 20 in order to generate the first n pixel data. Write to address buffer 0 (378). The period from time T _{0 to} T ₁ corresponds to the first stage of the generation process of the first n pixel data.

Next, in the period of time T _{1 to} T ₂ , the image data read interface unit 330 sequentially reads out the addresses stored in the address buffer 0 (378) and transmits them to the bus interface unit 400. In the period from time T _{1 to} time T ₂ , the image data read interface unit 330 receives each pixel of the first image received from the bus interface unit 400 corresponding to each address stored in the address buffer 0 (378). Data is written to data buffer 0 (390). The period from time T _{1 to} T ₂ corresponds to the second stage of the first n pixel data generation processing.

Further, in the period of time T _{1 to} T ₂ , the image data read interface unit 330 performs the second n pixel data of the second image (for example, when n = 4, p _{(4, 0) in} FIG. 2 _). N determination results determined by the determination processing unit 370 based on the coordinate data of the pixels of the first image for each of _{.about.p (7,0)} ) are written in the status buffer 1 (384). In the period from time T _{1 to} time T ₂ , the image data read interface unit 330 sets each address of the pixel data of the first image that needs to be read from the SDRAM 20 in order to generate the second n pixel data. Write to address buffer 1 (380). The period from time T _{1 to} T ₂ also corresponds to the first stage of the generation process of the second n pixel data.

Next, during the period from time T _{2 to} time T ₃ , the image data read interface unit 330 includes the n determination results stored in the status buffer 0 (382) and the first determination result stored in the data buffer 0 (390). The pixel data of the image is read and correction calculation is performed to generate the first n pixel data. The period from time T _{2 to} T ₃ corresponds to the third stage of the generation processing of the first n pixel data.

In the period from time T _{2 to} time T ₃ , the image data read interface unit 330 sequentially reads out the addresses stored in the address buffer 1 (380) and transmits them to the bus interface unit 400. In the period from time T _{2 to} time T ₃ , the image data read interface unit 330 receives each pixel of the first image received from the bus interface unit 400 corresponding to each address stored in the address buffer 1 (380). Data is written to the data buffer 1 (392). The period from time T _{2 to} T ₃ also corresponds to the second stage of the generation process of the second n pixel data.

Furthermore, in the period from time T _{2 to} time T ₃ , the image data read interface unit 330 displays the _third n pixel data of the second image (for example, p _{(0, 1) in} FIG. 2 when n = 4 _). N determination results determined by the determination processing unit 370 based on the coordinate data of the pixels of the first image for each of .about.p _(3,1) ) are written in the status buffer 2 (386). In the period from time T _{2 to} time T ₃ , the image data read interface unit 330 sets each address of the pixel data of the first image that needs to be read from the SDRAM 20 in order to generate the third n pixel data. Write to address buffer 0 (378). The period from time T _{2 to} T ₃ also corresponds to the first stage of the third n pixel data generation process.

Next, in the period from time T _{3 to} T ₄ , the image data read interface unit 330 displays the n determination results stored in the status buffer 1 (380) and the first determination result stored in the data buffer 1 (392). The pixel data of the image is read out and correction calculation is performed to generate the second n pixel data. The period from time T _{3 to} T ₄ corresponds to the third stage of the process of generating the second n pixel data.

In the period from time T _{3 to} time T ₄ , the image data read interface unit 330 sequentially reads out the addresses stored in the address buffer 0 (378) and transmits them to the bus interface unit 400. In the period from time T _{3 to} time T ₄ , the image data read interface unit 330 receives each pixel of the first image received from the bus interface unit 400 corresponding to each address stored in the address buffer 0 (378). Data is written to data buffer 0 (390). The period from time T _{3 to} T ₄ also corresponds to the second stage of the third n pixel data generation process.

Further, in the period of time T _{3 to} T ₄ , the image data read interface unit 330 displays the _fourth n pixel data of the second image (for example, p _{(4, 1) in} FIG. 2 when n = 4 _). N determination results determined by the determination processing unit 370 based on the coordinate data of the pixels of the first image for each of .about.p _(7,1) ) are written in the status buffer 0 (382). In the period from time T _{3 to} time T ₄ , the image data read interface unit 330 sets each address of the pixel data of the first image that needs to be read from the SDRAM 20 in order to generate the fourth n pixel data. Write to address buffer 1 (380). The period from time T _{3 to} T ₄ also corresponds to the first stage of the generation processing of the fourth n pixel data.

Next, in the period of time T _{4 to} T ₅ , the image data read interface unit 330 displays the n determination results stored in the status buffer 2 (382) and the first determination result stored in the data buffer 0 (390). The pixel data of the image is read and correction calculation is performed to generate the third n pixel data. The period from time T _{4 to} T ₅ corresponds to the third stage of the generation processing of the third n pixel data.

In the period from time T _{4 to} time T ₅ , the image data read interface unit 330 sequentially reads out the addresses stored in the address buffer 1 (380) and transmits them to the bus interface unit 400. In the period from time T _{4 to} time T ₅ , the image data read interface unit 330 receives each pixel of the first image received from the bus interface unit 400 corresponding to each address stored in the address buffer 1 (380). Data is written to the data buffer 1 (392). The period from time T _{4 to} T ₅ also corresponds to the second stage of the fourth n pixel data generation processing.

Further, in the period of time T _{4 to} T ₅ , the image data read interface unit 330 displays the _fifth n pixel data of the second image (for example, p _{(0, 2) in} FIG. 2 when n = 4 _). N determination results determined by the determination processing unit 370 based on the coordinate data of the pixels of the first image for each of .about.p _(3,2) ) are written in the status buffer 1 (384). In the period from time T _{4 to} time T ₅ , the image data read interface unit 330 sets each address of the pixel data of the first image that needs to be read from the SDRAM 20 in order to generate the fifth n pixel data. Write to address buffer 0 (378). The period from time T _{4 to} T ₅ also corresponds to the first stage of the fifth n pixel data generation process.

  Thereafter, the same processing is repeated, and the image data read interface unit 330 generates all the pixel data of the second image.

  As described above, the writing process to the address buffer is performed in the first stage, and the reading process from the address buffer is performed in the second stage. Therefore, the image data read interface unit 330 includes two address buffers so as not to stop the image data generation process. Similarly, the writing process to the data buffer is performed in the second stage, and the reading process from the data buffer is performed in the third stage. Therefore, the image data read interface unit 330 includes two data buffers so as not to stop the image data generation process. On the other hand, the writing process to the status buffer is performed in the first stage, and the reading process from the status buffer is performed in the third stage. Therefore, the image data read interface unit 330 includes three status buffers so as not to stop the image data generation process.

  As described above, according to the image processing apparatus of the present embodiment, the n pixel data generation process is divided into three stages, and the three sets of n pixel data generation processes are simultaneously performed while shifting one stage at a time. As a result, the image processing can be further speeded up.

  FIG. 10 is an example of a flowchart illustrating a processing procedure in which the image processing apparatus generates pixel data of the second image for one screen of the VGA illustrated in FIG. In the flowchart of FIG. 10, the SRAM 200 is a memory having, for example, a 9-bit address space as shown in FIG. 11, and the storage area for the offset data is the area where the most significant bit of the write address is 0 (offset data storage). It is assumed that the area 0) and the most significant bit are divided into 1 areas (offset data storage area 1).

  First, the image processing apparatus 10 initializes k = 0 and the memory area selection flag = 0 (step S10). Specifically, the memory interface unit 100 initializes the block line counter of the memory counter unit 120 to 0. The memory interface unit 100 has, for example, a 1-bit memory area selection flag register in the memory address generation unit 130 and initializes the value to 0.

Next, the image processing apparatus 10 receives vertex pixels p _(0,0) , p _(8,0) , p _(16,0) ,..., P _(624,0) from the SDRAM 20 on the block line BL _0. , p _(632,0) and dummy vertex pixel d _(640,0) are read out and written to addresses 000H to 050H in the offset data storage area 0 of the SRAM 200 (step S12). Specifically, the memory interface unit 100, a bus read address by the generator 110 and the control unit 180, and burst read from SDRAM20 offset data 402, for example, for each 16 on the block line BL _0, the block counter of the memory counter 120 Is counted up from 0 to 79, the memory address generation unit 130 sequentially generates the address signal 132 of addresses 000H to 050H, and writes the offset data in the offset data storage area 0 of the SRAM 200.

  Next, the image processing apparatus 10 increments k by 1 and inverts the memory area selection flag (step S14). Specifically, the memory interface unit 100 increments the block line counter of the memory counter unit 120 by one. Further, the memory interface unit 100 inverts the value of the memory area selection flag register from 0 to 1.

Next, the image processing apparatus 10, the apex pixels on the block line BL ₁ from _{SDRAM20 p (0,8), p (} 8,8), p (16,8), ···, p (624,8) , p _{(632, 8)} and dummy vertex pixel d _{(640, 8)} are read out and written to addresses 100H to 150H in the offset data storage area 1 of the SRAM 200 (step S16). Specifically, the memory interface unit 100, a bus read address by the generator 110 and the control unit 180, and burst read from SDRAM20 offset data 402, for example, for each 16 on the block line BL _1, the block counter of the memory counter 120 Is counted up from 0 to 79, the memory address generation unit 130 sequentially generates the address signal 132 of addresses 000H to 150H, and writes the offset data in the offset data storage area 1 of the SRAM 200.

Next, the image processing apparatus 10 reads the offset data from the offset data storage area 0 and the offset data storage area 1 of the SRAM 200, and blocks B _(0,0) , B _(1,0) , B _(2,0) , _.. , B _(78,0) , B _(79,0) are generated (step S18). Specifically, the memory interface unit 100 initializes the block counter of the memory counter unit 120 to 0, and based on the address signal 132 generated by the bus read address generation unit 110, the address in the offset data storage area 0 of the SRAM 200 The offset data of the pixel p _{(0, 0)} stored in 000H is read out and stored in the buffer 1-1 (140). In addition, the memory interface unit 100 increments the block counter of the memory counter unit 120 and stores it in the address 001H in the offset data storage area 0 of the SRAM 200 based on the address signal 132 generated by the bus read address generation unit 110. The offset data of the pixel p _{(8, 0)} is read and stored in the buffer 1-2 (150). The memory interface unit 100 also initializes the block counter of the memory counter unit 120 to 0, and stores it at the address 100H in the offset data storage area 1 of the SRAM 200 based on the address signal 132 generated by the bus read address generation unit 110. The offset data of the pixel p _(0,8) is read and stored in the buffer 1-3 (160). Further, the memory interface unit 100 increments the block counter of the memory counter unit 120 and stores it in the address 101H in the offset data storage area 1 of the SRAM 200 based on the address signal 132 generated by the bus read address generation unit 110. The offset data of the pixel p _{(8, 8)} is read and stored in the buffer 1-4 (170). That is, the memory interface unit 100 uses the offset data of the four vertex pixels p _(0,0) , p _(0,8) , p _(8,0) , p _(8,8) of the block B _(0,0). Are stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170), respectively. The image data generation processing unit 300 includes offset data 142, 152, 152 stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170), respectively. 162 and 172 are loaded into the buffer 2-1 (356), the buffer 2-2 (358), the buffer 2-3 (360), and the buffer 2-4 (362), respectively, and the H counter 352 and the V counter 354 are operated. _However, a process of generating n pieces of pixel data included in the block B _{(0, 0)} is performed.

Subsequently, the memory interface unit 100 stores the offset data of the pixel p _{(8,0) and} the offset data of the pixel p _(8,8) stored in the buffer 1-2 (150) and the buffer 1-4 (170), respectively. The data are transferred and stored in the buffer 1-1 (140) and the buffer 1-3 (160), respectively. In addition, the memory interface unit 100 increments the block counter of the memory counter unit 120 and stores the address counter 002H in the offset data storage area 0 of the SRAM 200 based on the address signal 132 generated by the bus read address generation unit 110. The offset data of the pixel p _(16,0) is read and stored in the buffer 1-2 (150). Further, the memory interface unit 100 stores the offset data of the pixel p _{(16, 8)} stored at the address 102H in the offset data storage area 1 of the SRAM 200 based on the address signal 132 generated by the bus read address generation unit 110. Read and store in buffer 1-4 (170). That is, the memory interface unit 100 uses the offset data of the four vertex pixels p _(8,0) , p _(16,0) , p _(8,8) , and p _(16,8) of the block B _(1,0). Are stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170). The image data generation processing unit 300 includes offset data 142, 152, 152 stored in the buffer 1-1 (140), the buffer 1-2 (150), the buffer 1-3 (160), and the buffer 1-4 (170), respectively. 162 and 172 are loaded into the buffer 2-1 (356), the buffer 2-2 (358), the buffer 2-3 (360), and the buffer 2-4 (362), respectively, and the H counter 352 and the V counter 354 are operated. _However, a process of generating n pieces of pixel data included in the block B _{(1, 0)} is performed.

The memory interface unit 100 and the image data generation processing unit 300 _thereafter repeat the same processing to generate n pieces of pixel data included in the blocks B _{(0, 0)} to B _{(79, 0)} .

  Next, the image processing apparatus 10 increments k by 1 and inverts the memory area selection flag (step S20). Specifically, the memory interface unit 100 increments the block line counter of the memory counter unit 120 by one. Further, the memory interface unit 100 inverts the value of the memory area selection flag register from 1 to 0.

  Next, the image processing apparatus 10 determines whether the memory area selection flag is 0 or 1 (step S22).

If the memory area selection flag = 0 (Yes in step S22), the image processing apparatus 10, the apex pixels on the block line BL _k from _{SDRAM20 p (0,8k), p (} 8,8k), p ( ₁₆ , _8k) ,..., P ₍₆₂₄ , _8k) , p _{(632, 8k)} and offset data of the dummy vertex pixel d _{(640, 8k)} are read out, and the offset data storage area 0 of the SRAM 200 is read. Are written to addresses 000H to 050H (step S24). Further, the image processing apparatus 10 reads the offset data from the offset data storage area 0 of the SRAM 200, and blocks B _{(0, k-1)} , B _{(1, k-1)} , B _{(2, k-1)} ,. .., B _{(78, k-1)} , B _{(79, k-1)} includes pixel data included (step S26). For example, apex pixels on the block line BL ₀ in step _{S18 p (0,0), p (} 8,8), p (16,0), ···, p (624,0), p (632,0 ₎ Offset data and dummy vertex pixel d _(640,0) offset data, vertex pixels p _(0,8) , p _(8,8) , p _(16,8) on the block line BL _{1 ,.} ·, _{p (624,8),} using the offset data of the _p offset data and the dummy vertex pixel _d of the _{(632,8) (640,8),} the block _{B (0,0), B (1, 0)} , B _(2,0) ,..., B _(78,0) , B _(79,0) are generated, and then the memory selection flag is inverted from 1 to 0 in step 20. Thus, in the process of step S24, the vertex pixels on the block line _{BL 2 p (0,16), p} (8,16), p (16,16), ···, p (624,16), p ( _632,16) and dummy vertex pixel d _(640,16) offset data are written into the offset data storage area 0 of the SRAM 200. Here, included in the blocks B _(0,1) , B _(1,1) , B _(2,1) ,..., B _(78,1) , B _(79,1) performed in the following step S26. in the generation process of the pixel data, the vertex pixels on the block line _{BL 1 p (0,8), p} (8,8), p (16,8), ···, p (624,8), p ( _632,8) offset data and dummy vertex pixel d _(640,8) offset data are necessary, but vertex pixel p _(0,0) , p _(8,8) , p on block line BL ₀ The offset data of _(16,0) ,..., P _(624,0) , p _{(632,0) and} the offset data of the dummy vertex pixel d _(640,0) are unnecessary. Therefore, in step S24, the vertex pixel _{p (0, 16)} on the block line _{BL 2, p (8,16),} p (16,16), ···, p (624,16), p (632, _{16) and} the offset data of the dummy vertex pixel d _{(640, 16)} are _converted into the vertex pixels p ₍₀ , ₀₎ , p ₍₈ , ₈₎ , p _{( 16, 0 )} , ..., offset data storage area 0 in which offset data of p _(624,0) , p _(632,0) and dummy vertex pixel d _(640,0) is stored can be overwritten. .

On the other hand, if the memory area selection flag = 1 (No at step S22), the image processing apparatus 10, the apex pixels on the block line BL _k from _{SDRAM20 p (0,8k), p (} 8,8k), The offset data of p _(16,8k) ,..., p _(624,8k) , p _(632,8k) and the dummy vertex pixel d _(640,8k) are read and stored in the SRAM 200. Write to the addresses 100H to 150H in area 1 (step S28). Further, the image processing apparatus 10 reads the offset data from the offset data storage area 1 of the SRAM 200, and blocks B _{(0, k-1)} , B _{(1, k-1)} , B _{(2, k-1)} ,. .., B _{(78, k-1)} , B _{(79, k-1)} includes pixel data included (step S30). For example, vertex pixel _{p (0, 8)} on the block line BL ₁ at step _{S26, p (8,8), p} (16,8), ···, p (624,8), p (632,8 offset data, apex pixels on the block line BL _{2 p} of offset data and the dummy vertex pixel _{d (640,8) in) (0,16), p (8,16} ), p (16,16), ·· _.. , P ₍₆₂₄ , ₁₆₎ , p _{(632, 16)} and the dummy vertex pixel d _{(640, 16)} using the offset data, the block B ₍₀ , ₁₎ , B _{(1, 1)} , B _(2,1) ,..., B _(78,1) , B _(79,1) are generated, and then the memory selection flag is inverted from 0 to 1 in step 20. Thus, in the process of step S28, the vertex pixels on the block line _{BL 3 p (0,24), p} (0,24), p (16,24), ···, p (624,24), p ( _{632, 24)} and dummy vertex pixel d _{(640, 24)} offset data are written into the offset data storage area 1 of the SRAM 200. Here, included in blocks B _(0,2) , B _(1,2) , B _(2,2) ,..., B _(78,2) , B _(79,2) performed in the subsequent step S30. in the generation processing of the pixel data of pixels, vertices pixels on the block line _{BL 2 p (0,16), p} (8,16), p (16,16), ···, p (624,16), p is the offset data is required for offset data and the dummy vertex pixel _{d (640,16)} of _(632,16), apex pixels on the block line BL _{1 p (0, 8), p (8, 8)} , p _(16,8) ,..., p _(624,8) , p _(632,8) and dummy vertex pixel d _{( 640,8)} are unnecessary. Therefore, in step S24, the vertex pixels on the block line _{BL 3 p (0,24), p} (0,24), p (16,24), ···, p (624,24), p (632, offset data of offset data and the dummy vertex pixel _{d 24) (640,24),} apex pixels on the block line _{BL 1 p (0,8), p} (8,8), p (16,8), ···, _{p (624,8),} can offset data of _p offset data and the dummy vertex pixel _d of the _{(632,8) (640,8)} overwrites the offset data storage area 1 stored .

  Next, the image processing apparatus 10 determines whether k = 60 (number of block lines) (step S32). If k ≠ 60 (No in step S32), the image processing apparatus 10 repeats the processes in steps S20 to S30. If k = 60 (Yes in step S32), the process for all block lines is performed. Therefore, the image processing apparatus 10 ends the generation of pixel data for one screen.

  As described above with reference to FIGS. 1 to 13, according to the image processing apparatus of this embodiment, the image data generation processing unit 300 (image data read interface unit 330) requests pixel data of the first image. In this case, a request signal 389 is transmitted. That is, the image data generation processing unit 300 (image data read interface unit 330) transmits a request signal 389 when requesting the next data even after receiving the pre-acknowledge signal 404. Accordingly, the bus interface unit 400 can determine whether or not the image data generation processing unit 300 (image data read interface unit 330) requests more data by transmitting the pre-acknowledge signal 404. When the image data generation processing unit 300 (image data read interface unit 330) requests more data, the bus interface unit 400 transmits the burst signal 18 to the bus 40 until the data request is completed. Set up exclusive rights. That is, the bus 40 can be occupied while the image data generation processing unit 300 (image data read interface unit 330) continues to request the pixel data of the first image. Therefore, according to the image processing apparatus of the present embodiment, the process of generating the pixel data constituting the second image based on the pixel data constituting the first image can be performed at a relatively high speed.

  Further, according to the image processing apparatus of the present embodiment, when a plurality of data can be burst read from the SDRAM 20, the latency of reading the second and subsequent data can be eliminated by occupying the bus 40. Therefore, the image generation process can be further accelerated.

  Further, according to the image processing apparatus of the present embodiment, when the image data generation processing unit 300 (image data read interface unit 330) requests only one data, the request signal 389 is transmitted after receiving the preacknowledge signal 404. Therefore, the bus interface unit 400 does not set the bus occupation right for the bus 40. Therefore, according to the image processing apparatus of the present embodiment, when only one pixel data is read from the SDRAM 20, the bus 40 is not unnecessarily occupied, so that the bus 40 by another device 30 or the like connected to the bus 40 is not used. Effective use can be achieved.

  Further, according to the image processing apparatus of the present embodiment, the image data generation processing unit 300 (image data read interface unit 330) is configured so that the bus interface unit 400 receives the acknowledge signal 42 from the SDRAM 20 via the bus 40. Based on the pre-acknowledge signal 404, processing for generating an address for reading out pixel data of the first image can be performed. Therefore, the image generation process can be further speeded up.

  Further, according to the image processing apparatus of the present embodiment, the offset data is stored in the SDRAM 20 capable of burst reading, and the memory interface unit 100 performs burst reading of the offset data from the SDRAM 20 one by one to offset at least two rows. Data is stored in the internal SRAM 200. That is, since all the offset data necessary for generating the second image for one screen is stored in the SDRAM 20, it is not necessary to store it in the SRAM 200. Therefore, the SRAM 200 only needs to be able to store offset data for at least two rows, and the size of the SRAM 200 can be greatly reduced. Therefore, the cost of the image processing apparatus 10 can be reduced relatively. Further, since the offset data is read out in bursts from the SDRAM 20 by a predetermined number, the latency required for reading the offset data can be greatly reduced. Therefore, the processing speed of the image processing apparatus 10 can be relatively increased.

  Further, according to the image processing apparatus of the present embodiment, two blocks adjacent in the row direction share pixels existing on one side, so that the offset data of the vertex pixels existing on one shared side is the data of the two blocks. Shared for image processing operations. Therefore, the number of offset data stored in the SDRAM 20 and read by the memory interface unit 100 can be reduced. Further, since the SRAM 200 includes two offset data storage areas, and the memory interface unit 100 stores the offset data for the current row in an offset data storage area different from the previously used offset data storage area, the two blocks The offset data shared for the image processing operation can be used in the current calculation processing while remaining in the previously used offset data storage area. Therefore, according to the image processing apparatus of the present embodiment, the processing speed can be further increased by effectively using the SRAM 200 having a small size.

  In addition, according to the image processing apparatus of the present embodiment, two blocks adjacent in the column direction share pixels existing on one side, so that offset data of vertex pixels existing on one shared side is the data of the two blocks. Shared for image processing operations. Therefore, the number of offset data stored in the SDRAM 20 and read by the memory interface unit 100 can be reduced. Further, the offset data shared by the image processing operations of the two blocks need only be read once from the SRAM 200. Therefore, according to the image processing apparatus of this embodiment, the processing speed can be further increased by efficiently using the SRAM 200 having a small size.

  Further, according to the image processing apparatus of the present embodiment, four double buffers (buffer 1-1, buffer 2-1, buffer 1 for storing four offset data respectively corresponding to the four vertex pixels of each block). -2 and buffer 2-2, buffer 1-3 and buffer 2-3, buffer 1-4 and buffer 2-4). Therefore, calculation processing for generating the pixel data by storing the offset data in the block to be calculated this time in the buffers 2-1 to 2-4, and reading the offset data in the block to be calculated next time from the SRAM 200 to the buffer 1 -1 to buffer 1-4 can be performed in parallel. Therefore, according to the image processing apparatus of this embodiment, the processing speed can be further increased by efficiently using the SRAM 200 having a small size.

  Further, according to the image processing apparatus of the present embodiment, the size and shape of the block that divides the second image can be set variably. Therefore, for example, when the distortion in the column direction is large, the shape of the block is set to a rectangle in which the number of pixels in the row direction is smaller than the number of pixels in the column direction, or the block size is set smaller. The accuracy of the second image can be improved or maintained according to the use environment.

2. Vehicle Head-Up Display System FIG. 12 is a diagram illustrating a configuration example of a vehicle head-up display system as an example of an image processing system using the image processing apparatus described with reference to FIGS.

  The vehicle head-up display system 600 includes an image processing device 610, an SDRAM 620 (an example of a storage device), an LCD projector 630 (an example of an image display device), and a CPU 640. The image processing device 610, SDRAM 620, and CPU 640 are connected to the bus 650.

  The image processing device 610 receives pixel data constituting the input image (first image) to be displayed, and generates pixel data constituting the output image (second image) based on the pixel data. Do. Pixel data constituting the input image may be stored in the SDRAM 620, or may be stored in another storage device (not shown) connected to the bus 650.

  The SDRAM 620 is a storage device capable of burst reading. For example, offset data indicating the difference between the coordinates of the vertex pixels of each block obtained by dividing the output image and the coordinates of the pixels of the input image corresponding to these vertex pixels. Is remembered.

  The LCD projector 630 generates an output image composed of pixel data generated by the image processing device 610 and projects it on the surface of the windshield 800.

  CPU 640 controls operations of image processing device 610 and LCD projector 630.

  The vehicle head-up display system 600 is disposed in the dashboard 700, for example. Since the surface of the windshield 800 shown in FIG. 12 is curved, the output image is obtained by adding a distortion in the reverse direction to the input image in advance for the distortion generated according to the shape of the windshield 800 and the position of the driver's eyes. Pixel data is generated. By doing so, an image viewed from the driver's line of sight can be prevented from being distorted.

  By applying the image processing apparatus according to the present embodiment to the image processing apparatus 610, the vehicle head-up display system 600 can improve the efficiency of the process of reading out the pixel data constituting the first image from the storage device, The process of generating the pixel data constituting the second image based on the pixel data constituting the first image can be performed at a relatively high speed.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 3 is a diagram for describing a configuration example of an image processing apparatus and an image processing system according to the present embodiment. The figure for demonstrating the state which divided | segmented the image comprised by the pixel which has the pixel data which the image processing apparatus of this embodiment produces | generates into several blocks. The figure for demonstrating an example of the offset data memorize | stored in SDRAM. The figure for demonstrating the structural example of a memory interface part. The figure for demonstrating the structural example of an image data generation process part. The figure for demonstrating the calculation method of the offset value of each pixel which comprises a 2nd image. The figure for demonstrating the structural example of an image data read interface part. The timing chart for demonstrating the transmission / reception timing of the signal between an image data read interface part and a bus interface part. FIG. 4 is a timing chart for explaining access timing to a status buffer, an address buffer, and a data buffer in an image data read interface unit. The figure which shows an example of the flowchart which shows the procedure of the process which the image processing apparatus produces | generates the pixel data of the 2nd image for 1 screen. The figure for demonstrating the offset data storage area of SRAM. The figure which shows the structural example of the head-up display system for vehicles as an example of an image processing system. FIG. 13A to FIG. 13C are diagrams for explaining a conventional image processing system.

Explanation of symbols

1 image processing system, 10 image processing apparatus, 12 pixel data, 14 address signal, 16 request signal, 18 burst signal, 20 SDRAM, 30 device, 40 bus, 42 acknowledge signal, 44 pixel data, 50 LCD, 52 second Image, 100 memory interface unit, 110 bus read address generation unit, 112 address signal, 120 memory counter unit, 130 memory address generation unit, 132 address signal, 140 buffer, 142 offset data, 150 buffer, 152 offset data, 160 buffer, 162 offset data, 170 buffer, 172 offset data, 180 control unit, 200 SRAM, 300 image data generation processing unit, 302 pixel data, 310 offset Data read interface, 320 coordinate calculation processing unit, 322 coordinate data, 330 image data read interface unit, 332 pixel data, 340 FIFO, 350 control unit, 352 H counter (pixel counter), 354 V counter (line counter), 356 buffer 358 buffer, 360 buffer, 362 buffer, 370 FIFO, 372 decision processing unit, 374 address generation unit, 376 address cache, 378 address buffer 0, 379 address signal, 380 address buffer 1, 382 status buffer 0, 384 status buffer 1 386 Status buffer 2, 388 Control unit, 389 Request signal, 390 Data buffer 0, 392 Data buffer 1, 394 data Cache, 396 correction calculation unit, 400 bus interface unit, 402 offset data, 404 pre-acknowledge signal, 406 acknowledge signal, 408 pixel data, 500 LCD controller, 600 vehicle head-up display system, 610 image processing device, 620 SDRAM, 630 LCD projector, 640 CPU, 650 bus, 700 dashboard, 800 windshield, 900 images, 902 images, 904 images, 910 display device

Claims (8)

An image processing apparatus that generates data of pixels constituting a second image based on data of pixels constituting a first image,
A bus interface unit that performs an interface process with respect to a bus that can set a bus occupancy right to which a storage device in which pixel data of the first image is stored is connected;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. An image processing apparatus, wherein when the transmission is continued, a bus occupation right is set for the bus. In claim 1,
The image data generation processing unit
An image processing apparatus generating an address for reading out pixel data of the first image from the storage device based on the first acknowledge signal. In claim 1 or 2,
The bus interface unit
When the request signal is received, a request signal for requesting pixel data of the first image is transmitted to the storage device via the bus, and a request signal is received based on the acknowledge signal received from the storage device via the bus. 2 acknowledge signal is transmitted to the image data generation processing unit,
The image data generation processing unit
An image processing apparatus for receiving pixel data of the first image based on the second acknowledge signal. In any one of Claims 1 thru | or 3,
The image data generation processing unit
Until the number of the first acknowledge signals equal to the number of pixel data of the first image necessary for generating the data of n (n ≧ 1) pixels of the second image is received. An image processing apparatus characterized by continuing to transmit a request signal. In claim 4,
The image data generation processing unit
A determination processing unit that determines the number of pixel data of the first image necessary to generate data of n pixels of the second image;
A status buffer for storing a determination result of the determination processing unit;
An address buffer for storing an address for reading out pixel data of the first image from the storage device based on a determination result of the determination processing unit;
An image processing apparatus comprising: a data buffer for storing pixel data of the first image read from the storage device. In claim 5,
The image data generation processing unit
Including three status buffers, two address buffers, and two data buffers, and a process of generating data of n pixels of the second image in a first stage, a second stage, and a second stage In the first stage, the determination result is stored in the status buffer and the address is stored in the address buffer. In the second stage, the pixel of the first image is stored in the data buffer. Of the second image based on the determination result stored in the status buffer and the pixel data of the first image stored in the data buffer in the third stage. A process of generating data for n pixels is performed, and three processes are performed for each n pixel data of the second image. The status buffer, the image processing apparatus characterized by two of said address buffer and two of the data buffer is cyclically each said first stage, the process of the second stage and the third stage carried out. An image processing device for generating data of pixels constituting the second image based on data of pixels constituting the first image;
A storage device storing pixel data of the first image;
A bus capable of setting a bus occupation right to which the image processing device and the storage device are connected, and
The image processing apparatus includes:
A bus interface unit that performs interface processing with respect to the bus;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. An image processing system, wherein when the transmission is continued, a bus occupation right is set for the bus. An image processing device for generating data of pixels constituting the second image based on data of pixels constituting the first image;
A storage device storing pixel data of the first image;
A bus capable of setting a bus occupation right to which the image processing device and the storage device are connected;
An image display device that displays the second image on a windshield based on pixel data generated by the image processing device,
The image processing apparatus includes:
A bus interface unit that performs interface processing with respect to the bus;
A request signal for requesting pixel data of the first image is transmitted to the bus interface unit, and pixel values of the second image are determined based on pixel data of the first image received from the bus interface unit. An image data generation processing unit for generating data,
The bus interface unit
When the request signal is received from the image data generation processing unit, a first acknowledge signal is transmitted to the image data generation processing unit, and the image data generation processing unit transmits the request signal after the transmission of the first acknowledge signal. The vehicle head-up display system is characterized in that when the transmission is continued, a bus occupation right is set for the bus.

Images