JP2009224758A - Composite semiconductor substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a composite semiconductor substrate that lowers defect density in a nitride semiconductor layer and at the same time, an amount of warpage of the composite semiconductor substrate by reducing stress between an Si substrate and a nitride semiconductor layer. <P>SOLUTION: The composite semiconductor substrate includes a silicon board (101) which has a principal plane having a (111) plane orientation and a plurality of protrusions formed thereon, and a nitride semiconductor layer (102) covering the principal plane, wherein an air void (103) is present in a space between each protrusion out of the plurality of protrusions. In such a composite substrate, stress caused by the inclusion of different types of materials of silicon and the nitride semiconductor can be reduced, thereby holding the defect density in the nitride semiconductor layer at a low level and minimizing warpage of the composite substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a composite semiconductor substrate including a nitride-based semiconductor layer, and particularly to a composite semiconductor substrate including a high-quality nitride-based semiconductor layer and a method for manufacturing the same.

  Nitride-based semiconductors are attracting attention as materials for optical devices and electronic devices. However, in order to achieve good device characteristics and ensure reproducibility, it is necessary to epitaxially grow a nitride-based semiconductor layer with few crystal defects.

  As a technique for reducing crystal defects in the nitride-based semiconductor layer, an ELOG (epitaxial lateral growth) technique is well known. In addition, Japanese Patent Application Laid-Open No. 2002-246698 of Patent Document 1, Japanese Patent Application Laid-Open No. 2004-356454 of Patent Document 2, and Japanese Patent Application Laid-Open No. 2005-64469 of Patent Document 3 also show crystal defects in the nitride-based semiconductor layer. A technique for reducing the amount is disclosed.

Patent Documents 1 to 3 relate to a nitride semiconductor layer growth technique used for a laser diode. In the techniques disclosed in these patent documents, a plurality of grooves having a width of several μm to several tens of μm and a depth of submicron to several μm are formed in a periodic stripe pattern on one main surface of a substrate wafer. Thereby, surface irregularities are provided. Thereafter, a nitride semiconductor layer is grown by the ELOG technique, and a defect concentration region and a low defect density region parallel to the groove of the substrate are generated in the grown nitride semiconductor layer. Each element of the laser diode is formed in the low defect density region. That is, since the width of the ridge portion of a general ridge stripe laser diode is several μm, the ridge portion corresponding to the light emitting region can be formed in the low defect density region, and the laser diode has good light emitting characteristics. Can be obtained.
JP 2002-246698 A JP 2004-356454 A Japanese Patent Laying-Open No. 2005-064469 JP 2002-343728 A

  Unlike the laser diode described above, a heterojunction field effect transistor fabricated using a nitride-based semiconductor layer has a much larger operating area for current flow. In particular, in the case of a high power transistor, it is necessary to reduce the defect density in the nitride-based semiconductor layer over an area of several hundred μm to several mm square or more. This is because if the defect density is high within the operating area where current flows in the transistor, the leakage current increases and the breakdown voltage decreases, and the reliability decreases.

  Therefore, a technique capable of growing a nitride-based semiconductor layer having a low defect density over a large area is desired, and an example of a technique that can make it possible is disclosed in Japanese Patent Laid-Open No. 2002-343728. . The schematic cross-sectional view of FIG. 6 illustrates the crystal growth technique of the nitride-based semiconductor layer disclosed in Patent Document 4.

  In FIG. 6A, an undoped GaN film is formed on a wafer-like single crystal sapphire substrate 501 having a crystallographic (0001) plane (abbreviated as C plane) by a MOCVD (metal organic chemical vapor deposition) method. Layer 502 is grown.

  In FIG. 6B, a metal Ti film 503 is laminated on the undoped GaN layer 502 by vapor deposition.

In FIG. 6C, the wafer on which the metal Ti film 503 is deposited is introduced into the MOCVD apparatus, and is subjected to heat treatment at 1050 ° C. for 30 minutes in an ammonia stream mixed with 20% of H ₂ . As a result, the Ti film 503 changes to a TiN film 503a. At this time, a large number of minute through holes are uniformly formed in the TiN film 503a at intervals of about 0.1 μm. Along with this, the underlying GaN film 502 is changed to a GaN film containing a large number of voids having a depth of about 400 nm (hereinafter referred to as “gap-containing GaN layer”) 502a. The cross section of the void-containing GaN layer 502a includes a large number of minute triangle regions, and the apexes of these minute triangles support the TiN film 503a.

  In FIG. 6D, if the GaN layer 504 is grown on the TiN film 503a by MOCVD, voids in the underlying GaN film 502a are preferentially embedded through a large number of minute through holes included in the TiN film 503a. Subsequently, a GaN layer 504 is grown on the TiN film 503a, and finally a composite substrate including the GaN layer 504 having a flat surface is obtained.

However, the thermal expansion coefficient of the TiN film (about 9 × 10 ⁻⁶ / K) is greatly different from the thermal expansion coefficient of the GaN layer (about 5.6 × 10 ⁻⁶ / K). Therefore, a large stress is generated at the interface between the TiN film 503a and the GaN layer 504 due to a large temperature difference between about 1000 ° C., which is the temperature during the growth of the GaN layer, and room temperature, which is the environmental temperature after the growth. The stress can cause defects and cracks in the GaN layer 504.

  Further, the composite substrate disclosed in Patent Document 4 includes an expensive sapphire substrate, and in particular, a large-diameter sapphire substrate is difficult to obtain and is more expensive. However, since a high power transistor has a large element area, it is desired to increase the substrate diameter in order to reduce the cost by mass production. In order to effectively dissipate heat generated from the power transistor, a substrate having high thermal conductivity is desired. It is considered preferable to use a Si substrate as a substrate that satisfies the conditions of these large diameters and high thermal conductivity.

  From such a viewpoint, it has been attempted to epitaxially grow a nitride-based semiconductor layer on a Si substrate. However, compared with the lattice mismatch ratio between the sapphire substrate and the GaN layer (approximately 13%), the lattice mismatch ratio between the Si substrate and the GaN layer (approximately 20%) is large, and a high-quality GaN layer is grown on the Si substrate. It turns out to be difficult.

Further, regarding the thermal expansion coefficient, the Si substrate (about 2.times.10.sup.- ⁶ / K) is different from the difference between the sapphire substrate (about 5.times.10.sup.- ⁶ / K) and the GaN layer (about 5.6.times.10.sup.- ⁶ / K). The difference between 6 × 10 ⁻⁶ / K) and the GaN layer is greater. Therefore, in the temperature difference between the growth temperature of the GaN layer (about 1000 ° C.) and the environmental temperature after growth (room temperature), stress is generated due to the difference in thermal expansion coefficient between the Si substrate and the GaN layer, which causes defects and cracks. Therefore, it is difficult to obtain a GaN crystal layer having a low defect density.

  Furthermore, since a large difference in thermal expansion coefficient exists between the Si substrate and the GaN layer and the diameter of the Si substrate is large, the Si substrate after crystal growth of the GaN layer tends to greatly warp. With a sapphire substrate having a small diameter for a conventional laser diode, even if the curvature radius of the warp increases, the warp amount of the substrate surface does not become a problem. However, if a large-diameter substrate having a diameter of 6 inches or more, such as a Si substrate, is used, even if the curvature radius is the same, the amount of warpage on the substrate surface can be a large difference in height of several tens of micrometers or more. When such a large amount of warpage is caused by stress based on the difference in thermal expansion coefficient, crystal defects are introduced or cracks are generated in the GaN layer so that the epitaxial GaN layer relieves the stress. .

  Furthermore, when the substrate is greatly warped, it is difficult to perform a device manufacturing process after epitaxial layer growth. Specifically, in the photolithography process, it becomes difficult to focus when using a reduction projection type exposure apparatus, and when a contact aligner exposure apparatus is used, the substrate and the mask do not adhere to each other to obtain high resolution. It becomes difficult. That is, the resolution decreases with increasing distance between the substrate and the mask.

  Furthermore, when heat treatment is performed in the device manufacturing process, the substrate is placed on a hot plate and heated, or the substrate is placed on a carbon plate and heated by a lamp. It cannot adhere to the part. In this case, the temperature distribution in the substrate surface becomes non-uniform, and the non-uniform temperature distribution can cause variations in device characteristics and defects.

  Further, in the device manufacturing process, the substrate is often vacuum-sucked on a stage or the like, and if the warp of the substrate is large, stable vacuum suction cannot be performed, and in the worst case, the substrate may be cracked.

  As a method of reducing the amount of warpage of the substrate in order to solve the above-mentioned problem, the substrate warpage amount (stress) is obtained by alternately stacking a plurality of AlN sublayers and GaN sublayers as buffer layers between the substrate and the device structure layer. Attempts have also been made to control. However, since the device structure of a laser or transistor is usually stacked on such a buffer layer, the balance of stress is lost if the type or thickness of the epitaxial growth layer included in the device structure is changed. It is necessary to reset the number and thickness of the sub-layers in the buffer layer.

  It is possible to design the buffer layer by theoretical stress calculations based on the respective lattice constants, thicknesses, elastic constants, etc. for the AlN and GaN sublayers in the buffer layer and the epitaxial layers in the device structure. However, since the lattice constant difference between the Si substrate and the AlN / GaN buffer layer on the Si substrate is large and defects or cracks may occur in the buffer layer to cause stress relaxation, the design according to the theoretical calculation is actually applied. It is difficult.

  Furthermore, since the change of the buffer layer also affects the crystal defects in the device structure above it, it is necessary to review the buffer layer and the device structure together to find the growth conditions of each nitride-based semiconductor layer. .

  Furthermore, on a Si substrate, it is difficult to grow a nitride semiconductor layer having a low defect density to a thickness of several microns or more because of a large difference in lattice constant and a difference in thermal expansion coefficient.

  In view of the situation in the prior art as described above, the main object of the present invention is to reduce the stress between the Si substrate and the nitride-based semiconductor layer thereon in the composite semiconductor substrate. It is to reduce the defect density and to reduce the amount of warpage of the composite semiconductor substrate.

  A composite semiconductor substrate according to the present invention includes a silicon substrate having a (111) plane orientation and having a principal surface on which a plurality of convex portions are formed, and a nitride-based semiconductor layer covering the principal surface, It is characterized by the presence of voids between the convex portions. In such a composite substrate, stress due to the inclusion of silicon and nitride semiconductors of different materials can be reduced, the defect density in the nitride semiconductor layer can be kept low, and the warpage of the composite substrate can be reduced. be able to.

  The nitride-based semiconductor layer covers not only the first nitride-based semiconductor sublayer covering only the top surfaces of the plurality of protrusions, but also the space between the plurality of protrusions as well as the first nitride-based semiconductor sublayer. And a second nitride-based semiconductor sublayer.

  The height of the convex portion is preferably larger than any of the width and interval, and is preferably five times or more. Since the height of the convex portion is large, the gap between the convex portions is reliably held, and the stress can be relieved by the gap. On the other hand, the width of the convex portion is preferably about 0.2 μm or less. By narrowing the width of the convex portion in this way, the area where the convex portion of the Si substrate and the nitride-based semiconductor layer are in contact with each other is reduced, and the stress generated between different materials can be reduced.

  By using the nitride-based semiconductor layer of the composite semiconductor substrate as described above, a high-quality semiconductor device can be obtained. In the semiconductor device, since the defect density is low, low leakage current, high breakdown voltage, etc. are good. Not only can the characteristics be obtained, but the amount of warpage of the composite substrate is small, so that the manufacturing process can be easily performed.

  In the above method for manufacturing a composite semiconductor substrate, a resin film containing a bond of silicon and oxygen is formed on one main surface of the silicon substrate, and the resin film is dry-etched using an etching gas containing oxygen gas. A mask pattern is formed by etching, one main surface of the silicon substrate is etched through the mask pattern to form a plurality of convex portions, the mask pattern is removed after the formation of the plurality of convex portions, and then one main surface of the silicon substrate is formed. It is preferable to include a step of growing a nitride-based semiconductor layer so as to cover the surface. In this case, the nitride-based semiconductor layer is preferably crystal-grown under reduced pressure.

  In the above-described method for manufacturing a composite semiconductor substrate, a first nitride-based semiconductor sublayer is formed on one main surface of a silicon substrate, and a resin film containing a bond of silicon and oxygen is formed on the silicon substrate. A mask pattern is formed on the main surface by dry etching the resin film using an etching gas containing oxygen gas, and one main surface of the first nitride-based semiconductor sublayer and the silicon substrate through the mask pattern Are etched to form a plurality of protrusions, and after the formation of the plurality of protrusions, the mask pattern is removed, and then the second nitride covering not only the first nitride-based semiconductor sublayer but also the plurality of protrusions. A step of crystal growth of the nitride-based semiconductor sublayer. In this case, it is preferable that at least the second nitride semiconductor sublayer among the first and second nitride semiconductor sublayers is crystal-grown under reduced pressure.

  In the composite semiconductor substrate according to the present invention as described above, not only the crystal defects in the nitride-based semiconductor layer grown on the silicon substrate are reduced, but also the warpage of the composite semiconductor substrate is reduced. Since the nitride-based semiconductor layer of the composite semiconductor substrate has a low defect density, not only the characteristics of the nitride-based semiconductor device manufactured using it are improved, but also the warpage of the composite semiconductor substrate is small. There is no problem in the subsequent device fabrication process. Moreover, since it is easy to increase the area of the composite semiconductor substrate, a nitride-based semiconductor device having good characteristics can be provided at low cost.

(Embodiment 1)
FIG. 1 is a diagram for explaining the structural features of the composite semiconductor substrate model according to Embodiment 1 of the present invention and the operational effects of the structure.

  The schematic cross-sectional view of FIG. 1A shows a cross-sectional structure of a composite semiconductor substrate model for which stress distribution calculation has been performed. In this composite semiconductor substrate model, a plurality of columnar convex portions 101a having a width A = 0.1 μm and a height B = 0.5 μm are arranged at intervals C = 0. They are separated by 1 μm. That is, the gap 103 exists between the plurality of columnar convex portions 101a. A GaN layer 102 having a thickness of 0.5 μm is laminated on the columnar protrusions 101a.

  Since the interval C between the columns 101a is narrow and the aspect ratio (B / A) is large, the gap between the plurality of columns 101a is not filled when the GaN layer 102 is vapor-phase crystal grown on the upper surface of the Si substrate 101. The existence of 103 is ensured. When the aspect ratio (B / A) is 1, the space between the pillars 101a can be filled with a nitride-based semiconductor. Therefore, in this embodiment, the aspect ratio is set to 5. If the aspect ratio is at least 5 or more, the presence of the air gap 103 can be ensured.

  In the stress distribution calculation, it was assumed that the crystal lattice spacing of the GaN layer 102 was 20% smaller than that of the Si substrate 101 and the lattice was not relaxed by crystal defects or cracks.

  FIG. 1B is a diagram representing the stress distribution in the lateral direction in the region 105 surrounded by the broken line in FIG. In this shading diagram, the higher the concentration, the greater the stress. Moreover, FIG.1 (c) is a graph which shows the stress distribution along the broken line 104 in FIG.1 (b).

  1B and 1C that the stress is concentrated on the columnar portion 101a of the Si substrate 101. FIG. Further, as can be seen from the graph of FIG. 1C, the stress is transferred from the compressive stress to the tensile stress in the column portion 101a, so that the stress is relieved in the thickness direction of the Si substrate 101. Absent. As a result, the warpage of the composite semiconductor substrate can be reduced. Also, the stress in the GaN layer 105 can be reduced. The reduction of the internal stress is more effective as the width A of the column portion is reduced. As the width A is increased, the stress at the interface between the nitride-based semiconductor layer 102 and the Si substrate column 101a is increased.

(Embodiment 2)
The schematic cross-sectional view of FIG. 2 illustrates the manufacturing process of the composite semiconductor substrate according to the second embodiment of the present invention.

  In FIG. 2A, first, a resin film 202 is formed on a silicon substrate 201 having a (111) principal surface. In this embodiment, the polyimide resin film 202 containing a bond of silicon and oxygen is formed to a thickness of 2 μm by spin coating.

  In FIG. 2B, the polyimide resin film 202 is etched by anisotropic etching such as reactive ion etching (RIE) using oxygen gas. At this time, since the bond between silicon and oxygen contained in the resin film 202 is not etched by oxygen gas, the bond is aggregated on the upper surface of the Si substrate 201 and remains as a needle-like deposit 203 having a diameter of about 0.1 μm. In this case, the aggregation state can be changed by changing the thickness and concentration of the resin film, and the size and density of the acicular deposit 203 can be changed.

  In FIG. 2C, the Si substrate 201 is etched through the needle-like mask 203 by anisotropic etching such as RIE using chlorine gas or the like. In this embodiment, anisotropic etching was performed using chlorine gas in an ICP (inductive coupling plasma) method. By this etching, a large number of fine columnar protrusions 204 are formed on the upper surface of the silicon substrate 201.

  Thereafter, cleaning with concentrated sulfuric acid and cleaning with hydrofluoric acid were performed to remove the needle-like mask 203 and to clean the upper surface of the silicon substrate 201. FIG. 3 shows an SEM (scanning electron microscope) photograph in which a large number of minute columnar protrusions 204 formed on the upper surface of the cleaned silicon substrate 201 are observed. The white line segment shown at the bottom of this SEM photograph represents a length of 100 nm (0.1 μm). In FIG. 3, it can be seen that a large number of cylindrical convex portions 204 having a diameter of about 0.1 μm to 0.2 μm or less and a height of about 1 μm are formed. Note that a resist used in photolithography can be used for the resin film in the present invention, and a polymer material containing a bond of silicon and oxygen can be used.

In FIG. 2D, on the upper surface of the silicon substrate 201 processed as shown in FIG. 3, NH ₃ (ammonia) as a group V element material and TMA (trimethylaluminum) as a group III element material are added. According to the MOCVD method used, an AlN layer 205 as a first buffer layer is grown to a thickness of 100 nm at a crystal growth temperature of 1000 ° C., and then an AlGaN layer 206 as a second buffer layer is formed thereon. The film was grown to 250 nm. On the AlGaN layer 206, a GaN layer 207 for crystallinity evaluation was grown at 1100 ° C. to a thickness of 2 μm.

  In crystal growth in this case, first, a nitride-based semiconductor layer starts growing on the top surface of the columnar protrusion 204 in a direction perpendicular to the substrate, and laterally extends from the side surface of the nitride-based semiconductor layer as the growth time elapses. Growth will also occur. As the crystal growth rate in the lateral direction increases, the nitride-based semiconductor layer spreads in a bowl shape from the top surface of the protrusions 204, and the space between the plurality of protrusions 204 is covered. Then, the side surfaces of the nitride-based semiconductor layers extending in a bowl shape from the top surfaces of the adjacent convex portions 204 are united, and dislocations extending in the lateral direction are terminated to reduce the defect density.

  In the case of the second embodiment, the pressure in the reaction chamber at the time of crystal growth until the gap between adjacent convex portions 204 is covered with a nitride-based semiconductor layer was set to 20 kPa. If crystal growth is performed in a reaction chamber close to atmospheric pressure, the space between the protrusions may be embedded with nitride semiconductor crystals, but the space between the protrusions becomes less likely to be embedded with nitride semiconductor crystals as the degree of decompression in the reaction chamber increases. As a result, voids are easily left between the convex portions. More specifically, when the height of the convex portions is larger than both the width and the interval, the crystal growth of the nitride-based semiconductor layer in the reduced pressure reaction chamber ensures the formation of voids between the convex portions. It becomes possible to leave.

  At this time, on the upper surface of the Si substrate 201, a nitride-based crystal is not formed between the plurality of column portions 204, and a gap remains. Thereafter, the growth rate in the thickness direction of the nitride-based semiconductor layer is increased, and the GaN layer 207 having a flat surface can be finally formed.

The obtained GaN layer 207 was immersed in a mixed solution of phosphoric acid and sulfuric acid heated to 250 ° C., and defects (etch pits) appearing on the surface were observed by SEM. As a result, the defect density on the surface of the GaN layer 207 was 1 × 10 ⁶ units, which was 1 to 2 digits lower than that in Patent Document 4. Further, the amount of warpage of the composite substrate in FIG. 2D was 10 μm or less due to the height difference of the 6-inch diameter substrate surface.

  In the present embodiment, the etching mask is formed using a resin. However, the etching mask can be formed using a metal in addition to the processing of the Si substrate using the resin. Specifically, a metal such as Al or In serving as an etching mask is deposited on the Si substrate to a thickness of several tens of nanometers. As a metal deposition method, electron beam evaporation, resistance heating evaporation, sputtering, or the like can be used. During the deposition, the metal atoms diffuse on the surface of the Si substrate, the metal atoms collide and bond with each other, and growth nuclei are randomly generated to aggregate the metal atoms. Thus, a large number of island-like metal patterns are formed. Using this island-like metal pattern as a mask, the Si substrate is anisotropically etched by RIE. Thereafter, the metal mask is etched away with acid, whereby a large number of minute cylindrical Si protrusions can be formed.

(Embodiment 3)
The schematic cross-sectional view of FIG. 4 illustrates the manufacturing process of the composite semiconductor substrate according to the third embodiment of the present invention.

In FIG. 4A, first, crystal growth at 1000 ° C. is performed on a silicon substrate 401 having a (111) principal surface by MOCVD using NH _{3 as a} group V element material and TMA as a group III element material. The AlN layer 402 was grown to a thickness of 100 nm at a temperature. In the present embodiment, the AlN layer 402 is crystal-grown, but the GaN layer may be grown by changing the MOCVD conditions.

  In FIG. 4B, similarly to the second embodiment, the upper surface of the AlN layer 402 and the Si substrate 401 is anisotropically etched using a resin film and RIE to form a columnar convex portion 403. That is, the convex portion 403 includes a Si pillar portion 401a and an AlN layer portion 402a thereon.

  In FIG. 4C, after removing the RIE mask, the nitride-based semiconductor layer 404 is grown on the cylindrical protrusion 403 again by MOCVD. As the MOCVD condition for the nitride-based semiconductor layer 404, it is preferable to select a condition in which the growth rate in the lateral direction is higher than that in the thickness direction. Then, the nitride-based semiconductor layer 404 spreads in a bowl shape from the top surface of the convex portion 403 so that the space between the plurality of convex portions 403 is covered. Then, the side surfaces of the nitride-based semiconductor layer 404 extending in a bowl shape from the top surfaces of the adjacent convex portions 403 are united with each other, dislocations extending in the lateral direction are terminated, and the defect density is reduced. At this time, on the upper surface side of the Si substrate 401, a nitride-based crystal is not formed between the plurality of column portions 403, and a gap remains. As a result, the nitride semiconductor layer including the AlN layer 402a as the first nitride semiconductor sublayer and the GaN layer 404 as the second nitride semiconductor sublayer is finally formed on the silicon substrate 401. It was done.

(Embodiment 4)
The schematic cross-sectional view of FIG. 5 shows a heterojunction field effect transistor according to Embodiment 4 of the present invention. This transistor is manufactured using the method for forming a composite semiconductor substrate according to Embodiment 2 described above.

  That is, in manufacturing the transistor of FIG. 5, instead of the GaN layer 207 in the composite semiconductor substrate of FIG. 2D, a GaN layer 208 having a thickness of 3 μm as a channel layer and an AlGaN having a thickness of 30 nm as a barrier layer. Layer 209 is subsequently grown by MOCVD. Then, by forming the gate electrode 212, the source electrode 210, and the drain electrode 211 on the AlGaN layer 209, a heterojunction field effect transistor can be manufactured.

  In the production of such a transistor, the difference in thermal expansion coefficient between the Si substrate and the nitride-based semiconductor layer in the temperature difference between the growth temperature of the nitride-based semiconductor layer (about 1000 ° C.) and the environmental temperature after growth (room temperature). Since the stress due to the above can be relieved by the column portion 204 of the composite semiconductor substrate, a nitride-based semiconductor stack with a low defect density can be obtained. Therefore, not only a low leakage current can be realized as transistor characteristics, but also the transistor manufacturing process can be easily performed because the warpage of the composite semiconductor substrate is small.

  Instead of the AlGaN layer 206 as the second buffer layer, a multilayer film in which, for example, an AlN layer having a thickness of 3 nm and a GaN layer having a thickness of 10 nm, for example, are alternately stacked is formed, and then a GaN layer 208 is formed thereon. An AlGaN layer 209 may be stacked. The multilayer film can be expected to act to further reduce the defect density in the AlN layer 208 and the GaN layer 209.

  Moreover, although the MOCVD method is used in the above-described Embodiments 2 to 4, it goes without saying that the HVPE (hydride vapor phase epitaxy) method may be used instead.

  As described above, in the composite semiconductor substrate according to the present invention, not only crystal defects in the nitride-based semiconductor layer grown on the silicon substrate are reduced, but also the warpage of the composite semiconductor substrate is reduced. Since the nitride-based semiconductor layer of the composite semiconductor substrate has a low defect density, not only the characteristics of the nitride-based semiconductor device manufactured using it are improved, but also the warpage of the composite semiconductor substrate is small. There is no problem in the manufacturing process of the device. Moreover, since it is easy to increase the area of the composite semiconductor substrate, a nitride-based semiconductor device having good characteristics can be provided at low cost.

It is a figure for demonstrating the structural characteristic of the composite semiconductor substrate model by one Embodiment of this invention, and the effect of the structure. It is typical sectional drawing illustrating the manufacturing process of the composite semiconductor substrate by other embodiment of this invention. FIG. 3 is a scanning electron micrograph showing a number of fine protrusions formed on the upper surface of the Si substrate in the manufacturing process of the composite semiconductor substrate of FIG. 2. FIG. It is a typical sectional view illustrating the manufacture process of the compound semiconductor substrate by further another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a heterojunction field effect transistor according to still another embodiment of the present invention. It is typical sectional drawing illustrating an example of the manufacturing process of the composite substrate by a prior art.

Explanation of symbols

  101, 201, 401 Si substrate, 101a Micro Si convex part, 102 GaN layer, 103 void, 104 Line where stress distribution of FIG. 1 (c) exists, 105 Region corresponding to stress distribution diagram of FIG. 1 (b), 202 resin film, 203 mask including many fine needle-like regions, 204 fine cylindrical silicon, 205 AlN layer, 206 AlGaN layer, 207 GaN layer, 208 GaN layer, 209 AlGaN layer, 210 source electrode, 211 drain electrode, 212 Gate electrode, 401a Fine columnar silicon, 402 AlN layer, 402a AlN layer on fine columnar silicon 401a, 403 Fine projection including fine columnar silicon 401a and AlN layer 402a, 404 Nitride semiconductor layer, 501 Sapphire substrate, 502 GaN Layer, 502a G with voids formed N layer, 503 Ti film, 503a a large number of TiN film containing fine through-holes, 504 GaN layer.

Claims (10)

A silicon substrate having a (111) plane orientation and having one principal surface on which a plurality of convex portions are formed;
A nitride-based semiconductor layer covering the one main surface,
A composite semiconductor substrate, wherein voids exist between the plurality of convex portions.   The nitride-based semiconductor layer includes a first nitride-based semiconductor sublayer that covers only top surfaces of the plurality of protrusions, and a space between the plurality of protrusions as well as the first nitride-based semiconductor sublayer. And a second nitride-based semiconductor sublayer covering the composite semiconductor substrate.   The composite semiconductor substrate according to claim 1, wherein a height of the convex portion is larger than any of a width and an interval thereof.   4. The composite semiconductor substrate according to claim 3, wherein the height of the convex portion is at least five times the width.   The composite semiconductor substrate according to claim 1, wherein a width of the convex portion is 0.2 μm or less.   6. A semiconductor device manufactured using the nitride-based semiconductor layer of the composite semiconductor substrate according to claim 1. A method for manufacturing the composite semiconductor substrate of claim 1, comprising:
Forming a resin film containing a bond of silicon and oxygen on one main surface of the silicon substrate;
A mask pattern is formed by dry etching the resin film using an etching gas containing oxygen gas,
Etching the one main surface of the silicon substrate through the mask pattern to form the plurality of convex portions;
Removing the mask pattern after forming the plurality of convex portions;
Thereafter, the method includes a step of crystal-growing the nitride-based semiconductor layer so as to cover the one main surface of the silicon substrate.   The manufacturing method according to claim 7, wherein the nitride-based semiconductor layer is crystal-grown under reduced pressure. A method for manufacturing the composite semiconductor substrate of claim 2, comprising:
Forming the first nitride-based semiconductor sublayer on one main surface of the silicon substrate;
Forming a resin film containing a bond of silicon and oxygen on the one principal surface of the silicon substrate;
A mask pattern is formed by dry etching the resin film using an etching gas containing oxygen gas,
Etching the first nitride-based semiconductor sublayer and the one main surface of the silicon substrate through the mask pattern to form the plurality of protrusions;
Removing the mask pattern after forming the plurality of convex portions;
Thereafter, the method includes a step of crystal-growing a second nitride-based semiconductor sublayer that covers not only the first nitride-based semiconductor sublayer but also between the plurality of convex portions.   10. The method according to claim 9, wherein at least the second nitride-based semiconductor sublayer of the first and second nitride-based semiconductor sublayers is crystal-grown under reduced pressure.