JP2009224711A - Semiconductor device and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact semiconductor device which can improve the productivity and reliability, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: In one main surface of a semiconductor wafer part 11, there are formed through plating: a first connection part 23 which connects an active region 12, which is a semiconductor element formed with approximately identical dimension, to an electrode pad 13 of a semiconductor chip 10 covered with a passivation film 14, which opens a part of electrode pad 13; a second connection part 25, which is connected to a substrate 100 and is located outside the semiconductor wafer part 11; and a lead part 20, which makes the first connection part 23 and the second connection part 25 continue and is provided with a curvature part 24, which has a predetermined angle to first connection part 23 and the second connection part 25. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a small semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a device capable of improving productivity and reliability.

  2. Description of the Related Art In recent years, with the development and spread of information processing technology, miniaturization of semiconductor devices has been demanded as electronic devices have become smaller, thinner and higher performance. Conventionally, SOP (Small Out-line Package), QFP (Quad Flat Package), and the like have been used for semiconductor devices of several pins to about 100 pins used for portable terminals and the like. However, non-lead-type SON (Small Out-line Non-Lead Package), QFN (Quad Flat Non-Lead Package), etc. are used for further downsizing. In recent years, a smaller CSP (Chip Scale Package) has also been used.

  Since SON and QFN are non-lead types, in the type of semiconductor device in which the leads do not protrude to the outside of the package and the electrodes are exposed on the bottom and side surfaces of the package, the connection to the substrate electrode by soldering is not possible. This is done on the bottom and side of the device.

  The CSP is the smallest semiconductor device in which the sizes of the internal semiconductor element and the semiconductor device are substantially the same. Such a CSP is generally mounted on a substrate by forming a plurality of solder balls in a lattice shape on the lower surface of the package and connecting the solder balls to substrate electrodes.

  In the manufacturing process of semiconductor devices such as SOP, QFP, SON, and QFN, first, a semiconductor chip separated after dicing is mounted on a lead frame. Next, it is connected to the electrodes and leads of the semiconductor chip by wire bonding, the semiconductor chip is molded with a sealing resin, the leads are cut off, and finally the leads are externally plated. Through these steps, a semiconductor device is manufactured.

  On the other hand, in the manufacturing process of the CSP, a semiconductor device is manufactured by mounting solder balls on the surface of a semiconductor wafer and dicing them into individual pieces. Thus, the CSP has higher productivity than other semiconductor devices.

  Such a CSP is connected to a substrate electrode via a solder ball provided on a semiconductor wafer. However, in a general CSP semiconductor device, for example, a semiconductor wafer formed of silicon is mounted on a glass epoxy substrate, so that the linear thermal expansion coefficients of the substrate and the semiconductor device are different. For this reason, shear stress concentrates on the connection part of a solder ball by the thermal expansion difference (dimensional difference) of CSP and a board | substrate accompanying a temperature change. Due to the temperature cycle test of the reliability test of electronic devices, the use of electronic devices, etc., shear stress is repeatedly applied to the joints of solder balls, and there is a high possibility of fatigue fracture (shearing).

  However, such solder ball connection is often made on the lower surface of the semiconductor chip, and visual inspection after mounting is virtually impossible, so there is a possibility that a connection failure or the like cannot be found. For this reason, at present, semiconductor devices with relatively high connection reliability such as SOP and QFP capable of visual inspection are used instead of CSP in which visual inspection is impossible.

  However, even a CSP is known as a semiconductor device capable of external appearance inspection (see, for example, Patent Document 1). In such a semiconductor device, a through hole is provided on a dicing line of a semiconductor wafer, the through hole is metallized and diced to divide the through hole into a semicircular shape, and an electrode is provided on an end surface portion of the semiconductor chip. That's it.

With the semiconductor device having such a configuration, the sizes of the semiconductor element and the semiconductor chip are substantially the same, and solder mounting is possible using the electrode on the end face of the package when mounting on the substrate. In addition, since the electrodes are formed outside the end face of the semiconductor chip, the appearance inspection after mounting can be performed.
Japanese Patent Laid-Open No. 11-204519

  There was a problem with the semiconductor device described above. That is, in order to provide a through-hole in a semiconductor wafer, a technique such as RIE (Reactive Ion Etching) is required, a new capital investment is required, and the manufacturing cost is increased. In addition, due to the difference in thermal expansion between the substrate and the semiconductor device that occurs due to the temperature cycle after mounting, stress concentrates on the solder connection between the substrate and the semiconductor device, and there is a risk of fatigue fracture of the solder connection. Can't get.

  Accordingly, the present invention provides a small-sized semiconductor device and a method for manufacturing the semiconductor device that can improve productivity and reliability at the time of mounting even if the semiconductor chip and the semiconductor element are semiconductor devices having substantially the same size. The purpose is that.

  In order to solve the above problems and achieve the object, a semiconductor device and a method for manufacturing the semiconductor device of the present invention are configured as follows.

  As one embodiment of the present invention, a semiconductor wafer, a semiconductor element disposed on the semiconductor wafer, a protective film covering the semiconductor element, and at least a part of one main surface and the protective film connected to the semiconductor element And a plurality of leads formed by a plating method in which one end is connected to the electrode and the other end protrudes from a side surface of the semiconductor chip. A semiconductor device is provided.

  One of the semiconductor wafers having a uniform body according to the present invention, wherein at least a part of electrodes respectively connected to a plurality of arranged semiconductor elements is opened and an insulating protective film covering the semiconductor elements is provided on one main surface Forming a resin layer having an opening for opening the electrode on the main surface, forming a conductive film on the electrode and the resin layer, and electroplating using the conductive film as a cathode, A semiconductor device comprising: a step of forming a lead in the opening; a step of cutting by dicing from the other surface of the semiconductor wafer to the resin layer; and a step of peeling and removing the resin layer. A manufacturing method is provided.

  According to the present invention, even when the semiconductor chip and the semiconductor element are semiconductor devices having substantially the same size, productivity and reliability during mounting can be improved.

  1 is a bottom view showing a configuration of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an XX section of the semiconductor device 1, and FIG. FIG. 4 is a cross-sectional view showing a YY cross section of an example of mounting of the semiconductor device 1.

  As shown in FIGS. 1 and 2, the semiconductor device 1 is formed in a CSP (Chip Scale Package) and includes a semiconductor chip 10 and a lead portion 20 provided in the semiconductor chip 10.

The semiconductor chip 10 includes, for example, a semiconductor wafer portion (hereinafter referred to as “wafer portion”) 11 formed of Si in a rectangular parallelepiped, and an active region 12 that is a semiconductor element such as a transistor formed on one main surface of the wafer portion 11. A plurality of electrode pads 13 mainly formed of Al and Cu, etc., formed on the active region 12, and a passivation film (protective film) 14 for coating one main surface of the wafer portion 11 and the active region 12. And has. The passivation film 14 is formed by laminating a SiO ₂ film, a SiN film, a polyimide film, and the like, and has an opening 15 at a position corresponding to the electrode pad 13.

  The wafer part 11 and the active area 12 have dimensions in the main surface direction that are slightly larger than the active area 12 or substantially the same dimension. Note that the surface of the active region 12 provided on the wafer unit 11 is coated with a passivation film 14.

  A plurality of electrode pads 13 are provided at end portions of the semiconductor chip 10 on the side surfaces facing each other and at positions where the end portions of the second connection portions 25 protrude from the side surfaces of the semiconductor chip 10 (in FIGS. Two are formed on each end face of the chip 10.

  The lead portion 20 includes a lead 21 formed of Cu or an alloy mainly containing Cu, and a laminated film 22 formed by plating an Sn alloy such as Sn or Sn—Ag on the surface of the lead 21. ing. The lead 21 includes a first connection portion 23 connected to each electrode pad 13 through the opening 15, and a bent portion 24 refracted at a predetermined angle with respect to the main surface of the semiconductor chip 10 from the first connection portion 23. The second connecting portion 25 is provided at the end of the bent portion 24 and connected to a metal pad 102 of the substrate 100 described later. Further, the electrode pad 13 and the opening 15 are connected to the lead portion 20 (first connection portion 23) via a seed layer 32 described later.

  The plurality of electrode pads 13 and the plurality of lead portions 20 are point-symmetric with respect to the center point of the semiconductor chip 10 or with respect to a center line parallel to the side surface on which the electrode pads 13 (lead portions 20) are provided. Thus, the other electrode pads 13 and the lead portions 20 are formed so as not to be positioned when moved in line symmetry. When the center line of the semiconductor chip 10 in the direction along the side surface where the electrode pad 13 is provided is not parallel (for example, when the semiconductor chip 10 is not square or rectangular), the semiconductor provided with the electrode pad 13 The center line is located between the side surfaces of the chip 10.

  The first connection portion 23 covers at least the electrode pad 13 exposed from the opening 15 and has a shape that expands in a direction away from the opening 15, for example, a trapezoidal cross section.

  The bent portion 24 is formed with a predetermined angle with respect to the first connection portion 23 and the second connection portion 25. This angle is determined when the first connection portion 23 and the second connection portion 25 are separated from each other due to a difference in thermal expansion between the semiconductor chip 10 and a substrate 100 described later when heat is applied to the semiconductor device 1. The lower surface (here, the surface opposite to the surface on the semiconductor chip 10 side) is formed at an angle that does not contact the substrate 100. For this reason, the angle of the bent portion 24 is appropriately set according to the relationship between the thermal expansion coefficients of the semiconductor chip 10 and the substrate 100.

  The second connection part 25 is formed in a shape in which at least a part of the second connection part 25 protrudes from the outer periphery of the semiconductor chip 10 when the semiconductor chip 10 and the lead part 20 are connected. Note that the protruding length of the second connection portion 25 is appropriately set depending on the mounting environment of the semiconductor device 1, the angle of the bent portion 24, the required bonding strength, the position of the first connection portion 23, and the like.

3 and 4, the semiconductor device 1 is mounted on the substrate 100.
The substrate 100 includes a resin substrate 101 formed of FR-4 or the like, a metal pad 102 provided on the resin substrate 101 and connected to another component or a wiring circuit, a part of the metal pad 102 or And a solder resist 103 provided on the resin substrate 101 except for the whole. The solder resist 103 is formed so that the metal pad 102 can be exposed to the outside by opening on the metal pad 102.

  As an example using such a substrate 100, the semiconductor device 1 is mounted by connecting the metal pads 102 of the substrate 100 and the second connection portions 25 of the leads 21 with solder H.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
As shown in FIG. 5, first, a plurality of active regions 12, a plurality of electrode pads 13 connected to each active region 12, and an opening on each electrode pad 13 are formed on a semiconductor wafer (hereinafter “wafer”) 11 </ b> A. A passivation film 14 having 15 is formed. The active region 12, the electrode pad 13, and the passivation film 14 are positioned so that each wafer unit 11 has the active region 12 and the electrode pad 13 when the wafer 11 </ b> A is an individual piece (wafer unit 11). It arrange | positions on the wafer 11A. As will be described later, the wafer portion 11 is a piece cut by a cutting portion Q indicated by a broken line of the wafer 11A.

  Next, as shown in FIG. 6, a first resist layer (resin layer) 30 is formed on the entire surface of the wafer 11A on the passivation film 14 by using, for example, a photosensitive liquid resist. After the first resist layer 30 is formed, the first resist layer 30 is exposed and developed using a light-shielding mask at a position where the electrode pad 13 is located, thereby forming a first opening 31 for opening the electrode pad 13. Form. The first opening 31 is formed, for example, so that the opening area increases as the distance from the wafer 11A in the thickness direction of the wafer 11A increases. The first resist layer 30 may be a dry film resist or the like instead of being formed of a liquid resist.

  After forming the first resist layer 30, as shown in FIG. 7, a seed layer (conductive film) 32 is deposited on the entire surface of the wafer 11A on the electrode pad 13 side as a power feeding layer for electroplating, which will be described later. It is formed by a physical deposition method such as sputtering. That is, the seed layer 32 is formed on the first resist layer 30 including the electrode pad 13, the passivation film 14, and the opening 31.

  For the seed layer 32, for example, a Ti film is formed on the entire surface of the wafer 11A by 0.1 μm, and a Cu film is formed by at least 0.2 μm to form a Ti / Cu laminated film. The Ti layer of the seed layer 32 improves the adhesion strength between the first resist layer 30 and the electrode pad 13 and the Cu layer, and the Cu layer serves as a current path during electroplating.

  Next, as shown in FIG. 8, a second resist layer 33 is formed on the seed layer 32 with a photosensitive liquid resist so as to have substantially the same thickness as the first resist layer 30. After the formation of the second resist layer 33, exposure and development are performed at a position where the first opening 31 of the second resist layer 33 is located, so that the second opening 34 is formed. The second opening 34 is larger than the first opening 31 of the first resist layer 30, and a part of the second opening 34 is located on the wafer portion 11 adjacent to the first opening 31. Form to shape.

  That is, the shape of the second opening 34 when viewed from above the wafer 11A is, for example, rectangular. As described above, the first opening 31 and the second opening 34 are continuous to form a rectangular opening 35 having different depths. The thickness of the second resist layer 33 is slightly thicker than the formation thickness of a Cu plating film 36 described later.

  Next, as shown in FIG. 9, the Cu plating film 36 is formed by the electroplating method with the opening 35 (the first opening 31 and the second opening provided in the first resist layer 30 and the second resist layer 33). Opening 34). Here, the electroplating method will be described. For example, the wafer 11A is immersed in a plating solution mainly composed of copper sulfate and sulfuric acid, and the negative electrode of the DC power source is connected to the seed layer 32. Next, a Cu plate is arranged as an anode placed so as to face the surface to be plated (seed layer 32) of the wafer 11A, and an anode of a DC power source is connected to the Cu plate, and a current flows. In this way, electroplating is performed to form a Cu plating film 36. Since the thickness of the Cu plating film 36 increases in proportion to the elapsed time, before the thickness of the Cu plating film 36 reaches the same as the thickness of the second resist layer 33 (the second resist layer 33). When the Cu plating film 36 is thinner than the thickness), the energization is stopped.

  After forming the Cu plating film 36, as shown in FIG. 10, the second resist layer 33 is mounted on a first mount film 37 for dicing, that is, for fixing the wafer 11A together. The first mount film 37 is provided with, for example, an adhesive on the mount surface, and the second resist layer 33 is mounted and fixed by the adhesive. For example, as the adhesive for the first mount film 37, an adhesive having a property that its adhesive strength is reduced by UV light is used.

  Next, as shown in FIG. 11, dicing is performed using a dicing blade 38 from the surface of the wafer 11 </ b> A opposite to the side on which the Cu plating film 36 is formed to the middle portion of the first resist layer 30. Here, for example, dicing is performed while confirming that the dicing position (dicing line) does not exceed the first resist layer 30. For this confirmation, for example, an infrared camera is used to align the dicing blade 38. By this dicing, the wafer 11 </ b> A has the seed layer 32 and the first resist layer 30 continuous from the second resist layer 33 fixed to the first mount film 37, but the wafer portion 11 including the passivation film 14. Will be singulated.

  After dicing in this way, as shown in FIG. 12, one sheet is formed on all the main surfaces of the plurality of wafer portions 11 that are opposite to the main surface of the wafer portion 11 provided with the second resist layer 33. The second mount film 39 is mounted. As described above, when all the wafer portions 11 are fixed by the second mount film 39, the first mount film 37 is irradiated with UV light, and the first mount film 37 is peeled off. The second mount film 39 may be the same mount film as the first mount film 37 or may be a different mount film. However, at least the second mount film 39 has elasticity.

  Next, when the first mount film 37 is peeled off, the second resist layer 33 is removed by immersing or applying the second resist layer 33 in an organic stripping solution as shown in FIG. At this time, since the organic stripping solution does not reach the first resist layer 30 by the seed layer 32, the first resist layer 30 remains without being removed.

  Next, as shown in FIG. 14, the seed layer 32 is removed by etching. In this etching, for example, Cu in the seed layer 32 is dissolved with an aqueous solution of ammonium persulfate, and Ti in the seed layer 32 is etched with a mixed solution of hydrogen peroxide water, ammonia water, and a chelating agent.

  At this time, the seed layer 32 to be removed is on the first resist layer 30 and the seed layer 32 outside the range where the Cu plating film 36 is provided, that is, the second resist layer 33 is removed. Thus, only the seed layer 32 exposed to the outside is obtained. Further, at the time of etching, when Cu of the seed layer 32 is dissolved by the ammonium persulfate aqueous solution, the Cu plating film 36 is also dissolved. However, since the dissolution of Cu in the seed layer 32 is about 0.2 μm, which is the Cu film thickness of the seed layer 32, the Cu plating film 36 is also dissolved only about 0.2 μm. Further, when Ti of the seed layer 32 is dissolved, since a mixed solution of hydrogen peroxide water, ammonia water and a chelating agent is used, the Cu plating film 36 is hardly dissolved. Thus, the Cu plating film 36 is hardly etched by the etching, and the Cu plating film 36 serves as an etching mask, and only the seed layer 32 exposed on the first resist layer 30 is completely etched. .

  Next, as shown in FIG. 15, the first resist layer 30 is removed with an organic stripping solution. By this process, the semiconductor chips 10 having the respective Cu plating films 36 are only mounted on the second mount film 39, and the respective semiconductor chips 10 are completely separated.

  Subsequently, as shown in FIG. 16, by etching Ti on the surface of the seed layer 32 remaining in the Cu plating film 36 with a mixed solution of hydrogen peroxide water, ammonia water and a chelating agent, a Cu plating film ( The lead 21 formed by the Cu plating film 36) is formed.

  After the formation of the lead 21, as shown in FIG. 17, a laminated film 22 made of Ni and Sn film is formed on the surface of the lead 21 by, for example, electroless plating. The laminated film 22 is formed to increase the wettability with the solder when the leads 21 are soldered onto the substrate 100. Instead of providing the laminated film 22, an organic rust preventive agent is applied. May be. Thus, the lead part 20 is formed by forming the laminated film 22 on the surface of the lead 21. Through these steps, the semiconductor chip 10 and the lead portion 20 are formed, and the semiconductor device 1 is formed.

  Next, as shown by the arrows in FIG. 18, the second mount film 39 is expanded in the direction in which the lead portion 20 of the semiconductor chip 10 is formed or in a plurality of directions including the direction in which the lead portion 20 is formed. Let In this way, by expanding the second mount film 39, the second mount film 39 is elastically deformed and the interval between the semiconductor chips 10 can be formed, so that the lead portion 20 is located at the end of the adjacent semiconductor chip 10. There is no.

  In this state, as shown in FIG. 19, by picking up the semiconductor device 1, the semiconductor chip 1 of the semiconductor device 1 to be picked up and the lead portion 20 of the adjacent semiconductor device 1 do not interfere with each other. Is separated from the second mount film 39.

  In the semiconductor device 1 configured as described above, the semiconductor device 1 is mounted on the substrate 100, whereby the second connection portion 25 of the lead portion 20 of the semiconductor device 1 and the metal pad 102 of the substrate 100 are fixed by the solder H. (Connected). Further, in the semiconductor device 1, the first connection portion 23 of the lead portion 20 is connected (fixed) to the electrode pad 13 through the opening portion 15 of the semiconductor chip 10 by an electrolytic plating method. The second connection portion 25 is continuous with the bent portion 24.

  When the semiconductor device 1 mounted on the substrate 100 is actually used, for example, when a current is supplied to the metal pad 102 via the wiring circuit of the substrate 100, the semiconductor chip is connected to the metal pad 102 from the lead portion 20 connected thereto. 10 is input. This input current flows downstream from another lead portion 20 via the active region 12 of the semiconductor chip 10.

  At this time, current flows through the wiring circuit of the substrate 100 and the metal pads 102 and the semiconductor device 1, so that the semiconductor device 1 and the substrate 100 generate heat. Due to such heat generation, the substrate 100 and the semiconductor device 1 become high temperature. Further, when the power supply of the device provided with the semiconductor device 1 is turned off and the current is cut off, the semiconductor device 1 and the substrate 100 are naturally cooled (cooling by a fan or the like depending on the electronic device). In this way, temperature cycles such as heat generation / cooling of the semiconductor device 1 and the substrate 100 are repeatedly performed.

  For example, the semiconductor device 1 may be mounted on the substrate 100 and a heat cycle test may be performed in which the heat generation / cooling cycle generated when the semiconductor device 1 is actually used is predicted and tested. The heat application by such a heat cycle test is applied to the substrate 100 and the semiconductor device 1 using, for example, a high-temperature bath or the like, the heat that is considered to be applied when the semiconductor device 1 is used, and the cycle of this heat. The connection status of each lead part 20 and the operation status of the semiconductor device 1 are confirmed. This is mainly performed at the time of product (semiconductor device 1) development, product shipment, or product improvement.

  When heat is applied to the semiconductor device 1 and the substrate 100 due to such use of the semiconductor device 1 and a thermal cycle test, the semiconductor device 1 and the substrate 100 are thermally expanded. Note that the amount of thermal expansion varies depending on the material, that is, the coefficient of thermal expansion differs, and therefore the material expands to a different size depending on the material.

  That is, the substrate 100 and the semiconductor device 1 (semiconductor chip 10) have different thermal expansion coefficients, and the thermal expansion amounts are different from each other. Here, since the substrate 100 and the semiconductor chip 10 are, for example, square and the thickness dimension is smaller than the width dimension, the width direction (main surface direction) mainly expands (becomes larger) than the thickness direction. .

  For example, as shown by the arrows in FIG. 4, when the substrate 100 and the semiconductor chip 10 are thermally expanded, they are expanded in the width direction. At this time, since the substrate 100 and the semiconductor chip 10 have different thermal expansion coefficients, the expansion amounts in the width direction are also different.

  Due to such thermal expansion, the first connection portion 23 and the second connection portion 25 move in accordance with the expansion of the semiconductor chip 10 and the substrate 100 to which they are fixed. However, since the expansion amounts of the substrate 100 and the semiconductor chip 10 are different, the movement amounts of the first connection portion 23 and the second connection portion 25 are also different. For example, when the thermal expansion coefficient of the substrate 100 is higher than that of the semiconductor chip 10, the substrate 100 performs thermal expansion more than the semiconductor chip 10, and the first connection portion 23 and the second connection portion 25 are separated from each other. Further, when the thermal expansion coefficient of the substrate 100 is lower than that of the semiconductor chip 10, the semiconductor chip 10 performs thermal expansion more than the substrate 100 and moves in the direction in which the first connection portion 23 and the second connection portion 25 approach each other. To do.

  At this time, the bent portion 24 is provided with a predetermined angle between the first connecting portion 23 and the second connecting portion 25, and the first connecting portion 23 and the second connecting portion 25 are moved away from each other. In other words, the first connecting portion 23 and the second connecting portion 25 are separated from each other by changing the angle of the bent portion 24.

  According to the semiconductor device 1 configured as described above, even if the semiconductor chip 10 and the active region 12 have substantially the same dimensions (CSP), the lead portion 20 can be formed by plating. In addition, since the first and second resist layers 30 and 33 are provided, the first and second openings 31 and 34 formed in the resist layers 30 and 33 are formed in two stages. The bent portion 24 can be provided.

  By adopting such a lead portion 20, even when the thermal expansion coefficients of the semiconductor chip 10 and the substrate 100 are different due to thermal expansion due to heat generated during use of the semiconductor device 1 (or thermal cycle test), By changing the angle of the bent portion 24, the first connecting portion 23 and the second connecting portion 25 can be separated from each other. In addition, since the first connection portion 23 and the second connection portion 25 can be separated from each other, shear stress is generated in each connection portion between the first connection portion 23 and the second connection portion 25, the semiconductor chip 10, and the substrate 100. It becomes possible to prevent application. That is, it is possible to prevent breakage due to shear stress at each bonding portion between the first connection portion 23 and the second connection portion 25 and the semiconductor chip 10 and the substrate 100, and to improve the reliability of the bonding portion.

  In addition, even when the semiconductor device 1 is mounted on the substrate 100, the connection portion between the second connection portion 25 and the substrate 100 (metal pad 102) is positioned outside the side surface of the semiconductor chip 10. A connection portion between the second connection portion 25 and the substrate 100 can be easily visually recognized. As a result, it is possible to easily confirm the state of adhesion between the second connecting portion 25 and the substrate 100 when the semiconductor device 1 is mounted on the substrate 100, that is, to perform an appearance inspection. Further, since the visual recognition can be surely performed, it is possible to find unbonded or broken between the first connecting portion 23 and the substrate 100, and the mounting reliability of the semiconductor device 1 is improved. In addition, visual inspection can be performed by visual recognition, and the inspection time can be shortened and the inspection cost can be reduced by introducing an inspection device or the like.

  Further, the lead portion 20 is point-symmetrical with respect to the center point of the semiconductor chip 10 on the semiconductor chip 10 or in a position that is line-symmetric with respect to the center line in the end surface direction on the side surface side where the lead portion 20 is provided. A plurality of other lead portions 20 are provided so as not to be positioned. Thereby, the adjacent lead part 20 provided in the semiconductor chip 10 and the lead part 20 provided in the adjacent semiconductor chip 10 do not interfere with each other during manufacturing. For this reason, a plurality of semiconductor devices 1 can be formed on the same wafer 11A in the series of processes described above, which facilitates the manufacturing process and improves the productivity.

  As described above, according to the semiconductor device 1 according to the present embodiment, even in the semiconductor device 1 substantially equivalent to the semiconductor chip 10, the connection portion between the lead portion 20 and the substrate 100 after the semiconductor device 1 is mounted. Visual confirmation is possible. By this visual confirmation, it is possible to confirm the disconnection between the substrate 100 and the second connection portion 25 or the breakage due to the heat application, and the reliability is improved. Further, by providing the bent portion 24 in the lead portion 20, the shear stress to the first and second connection portions 23 and 25 between the semiconductor device 1 and the substrate 100 and the lead portion 20 due to thermal expansion after the semiconductor device 1 is mounted. The application can be prevented, and the shearing (breaking) of each connecting portion can be prevented, and the reliability of the semiconductor device 1 can be improved.

  Furthermore, by forming the lead part 20 on the semiconductor chip 10 in an arrangement that does not interfere with the other lead part 20 provided in the semiconductor device 1 and the lead part 20 of the adjacent semiconductor device 1, at the wafer 11A level, The semiconductor device 1 can be formed into individual pieces. For this reason, even if it is the semiconductor device 1 which forms the lead part 20, it becomes possible to improve the productivity of the semiconductor device 1.

  Modifications other than the above-described embodiments will be described. For example, in the above-described example, two lead portions 20 formed on the semiconductor chip 10 are provided at one end portion and two at the opposite end portion, but this is limited to two. Is not to be done. That is, the lead portions 20 provided on the semiconductor chip 10 may be arranged so as to be within the range of the adjacent semiconductor chips 10 when the lead portions 20 are integrally formed on the wafer 11A, and the lead portions 20 do not interfere with each other.

  In the example described above, the semiconductor device 1 is configured to provide the lead portion 20 on the passivation film 14. However, as illustrated in FIG. 20, as the semiconductor device 50, a resin such as epoxy is further provided on the passivation film 14. Even if the layer 51 is coated and the lead portion 20A is formed there, it is applicable. In addition, there is no restriction | limiting in the thickness of the resin layer 51 at this time, and it can apply, if the lead part 20A is the structure which has the bending part 24, and can connect with the electrode pad 13 from the opening part of the resin layer 51. FIG. Further, as shown in FIG. 21, as the semiconductor device 60, a Cu post 61 may be formed on the electrode pad 13 and sealed with a resin layer 62. In this case, the lead portion 20B may be formed by electrode plating so as to connect to the Cu post 61.

  In addition, the wafer part 11, the seed layer 32, the first and second resist layers 30, 33, the leads 21, and the laminated film 22 in the above-described example can be applied even if the material, composition, dimensions, etc. are appropriately changed. Also, the composition of the plating solution and the plating conditions can be changed as appropriate.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a bottom view illustrating a configuration of a semiconductor device according to an embodiment of the present invention. Sectional drawing which shows the structure of the semiconductor device. The top view which shows an example of mounting of the same semiconductor device. Sectional drawing which shows an example of mounting of the semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Explanatory drawing which shows the manufacturing process of the same semiconductor device. Sectional drawing which shows the semiconductor device which concerns on the modification of this Embodiment. Sectional drawing which shows the semiconductor device which concerns on the modification of this Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor chip, 11 ... Semiconductor wafer part, 11A ... Semiconductor wafer, 12 ... Active region, 13 ... Electrode pad, 14 ... Passivation film | membrane, 15 ... Opening part, 20, 20A, 20B ... Lead part, DESCRIPTION OF SYMBOLS 21 ... Lead, 22 ... Laminated film, 23 ... 1st connection part, 24 ... Bending part, 25 ... 2nd connection part, 30 ... 1st resist layer, 31 ... 1st opening part, 32 ... Seed layer, 33 ... Second resist layer 34 ... second opening 35 ... opening 36 ... film 37 ... mount film 38 ... dicing blade 39 ... mount film 50 ... semiconductor device 51 ... resin layer 60 ... semiconductor Device 61 ... Post 62 ... Resin layer 100 ... Substrate 101 ... Resin substrate 102 ... Metal pad 103 ... Solder resist H ... Solder Q ... Cutting part

Claims (9)

A semiconductor element disposed on a semiconductor wafer, and a semiconductor chip connected to the semiconductor element and having at least a part of electrodes from one main surface;
And a plurality of leads formed by a plating method in which one end is connected to the electrode and the other end protrudes from a side surface of the semiconductor chip.   The lead has the one end and the other end spaced apart from each other in the height direction of the semiconductor chip, and the one end and the other end are continuous. The semiconductor device according to claim 1, further comprising a bent portion provided at an angle with respect to the main surface.   The leads are respectively provided on opposite side surfaces of the semiconductor chip, and are provided asymmetrically with respect to a center line of the semiconductor chip parallel to the side surfaces or a center point of the semiconductor chip. The semiconductor device according to claim 1.   The semiconductor chip includes a semiconductor wafer, a plurality of the semiconductor elements arranged on one main surface of the semiconductor wafer, the electrodes respectively connected to the semiconductor elements, and an insulating protective film covering the plurality of semiconductor elements The semiconductor device according to claim 1, wherein the semiconductor device is a piece including at least one of the semiconductor elements.   The semiconductor device according to claim 1, wherein the semiconductor element is formed in a shape equivalent to an outer shape of the semiconductor chip. Opening at least a part of the electrodes respectively connected to the semiconductor elements arranged in plural, and having the electrode on one main surface of the semiconductor wafer having an insulating protective film covering the semiconductor element on one main surface Forming a resin layer having an opening to be opened;
Forming a conductive film on the electrode and the resin layer;
Forming a lead in the opening by electroplating using the conductive film as a cathode;
Cutting from the other surface of the semiconductor wafer to the resin layer by dicing;
And a step of peeling off and removing the resin layer.   The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the resin layer, the opening is formed in a continuous step shape.   In the step of forming the resin layer, the opening is formed at a position where the opening provided for each of the plurality of semiconductor elements does not interfere with the opening formed on the adjacent semiconductor element. A method for manufacturing a semiconductor device according to claim 6.   The semiconductor device according to claim 6, wherein in the step of forming the resin layer, the opening is formed up to the adjacent semiconductor element.

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