JP2009218858A - Pixel periphery recording type imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dispense with the rearrangement of pixels read from a pixel periphery recording type element (ISIS). <P>SOLUTION: An ISIS_CCD includes: an N×M photodiodes arranged by N-periods in the longitudinal direction and M-periods in the horizontal direction; an M-number of vertical transfer passages being v×N-stages or more, which are directly or indirectly connected at v-stage interval to the N-number of photodiodes longitudinally arranged by each period in the horizontal direction; and horizontal transfer passages being h×M-stages or more, which are connected at h-stage interval to the respective one ends of the M-number of vertical transfer passages. When an electric charge is read from the ISIS_CCD, the respective M-number of vertical transfer passages perform a v-stage transfer operation whenever the electric charge is received from the connected photodiodes, and also transfer the imaging electric charges corresponding to one photodiode to the horizontal transfer passages. Then, the horizontal transfer passages perform transfer by h×M-stages or more concerning the transferred imaging electric charge, while keeping the h-stage interval, so as to perform line reading. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a pixel peripheral recording type imaging apparatus, and more particularly to an ISIS (In-situ).
The present invention relates to a pixel peripheral recording type imaging apparatus such as a high-speed imaging camera using a storage image sensor (CCD) (hereinafter referred to as ISIS_CCD).

  As conventional techniques, there are known high-speed photographing cameras using ISIS_CCD as disclosed in Patent Documents 1 and 2 and ISIS_CCD as described in Non-Patent Document 1. The camera of Non-Patent Document 1 is capable of shooting 144 frames of moving images at an ultra-high speed of 1 million frames / second under normal illumination.

1 and 2 are schematic diagrams for explaining pixel readout in a conventional single-plate color high-speed camera using ISIS_CCD.
In the ISIS_CCD, N photodiodes are arranged periodically in a vertical direction and M in a horizontal direction. Each photodiode is provided with a color filter for a single plate color on the front surface of the CCD, so that each pixel detects a predetermined color signal regularly (for example, in a Bayer array).

Here, paying attention to the uppermost row (Nth row), an s-stage oblique transfer path extends from each photodiode, and v stages of vertical transfer paths are coupled to the further (output side).
Such a structure is repeated in the vertical direction by the number of rows, and the v-stage vertical transfer path is actually configured continuously as an N × v-stage transfer path, and each column has an oblique transfer path in units of v stages. The charge from can be merged.
Since independent charges can be held in each stage of the transfer path, the number of frames that can be continuously shot in one high-speed shooting can be increased to s + v by storing charges in the vertical transfer path for v stages. This transfer path for s + v stages is hereinafter referred to as a memory / transfer path.

FIG. 1 exemplifies a state at the time when high-speed shooting is completed, and signal charges photoelectrically converted by each photodiode at a frame period are stored in each stage of the memory and transfer path. That is, the transfer path is in a state where charges having information for each frame corresponding to the number of stages are arranged.
Here, paying attention to the bottom row (first row), the charges read from the leftmost green pixel are stored in the order of G110, G111, G112,..., G11v in the first column vertical transfer path. . Similarly, R120 to R12v are stored in the second column vertical transfer path, and G1M0 to G1Mv are stored in order in the M column vertical transfer path. These signal charges are represented by the first character being the pixel color, the second character being the pixel vertical index (1 to N), and the third character being the pixel horizontal index (1 to N), The fourth character indicates the index of the number of stages in the transfer path (oblique: 0 to S, vertical: 0 to v, horizontal: 0 to h).
The lowermost part of each of the M vertical transfer paths is coupled to an h × M horizontal transfer path at an interval of h stages. An e-stage empty transfer path is connected to the end of the horizontal transfer path, and an FDA (Floating Diffusion Amplifier) is further connected to the end of the horizontal transfer path.

FIG. 2 shows a state in which the signal charges stored in the vertical transfer path are moved to the horizontal transfer path. The signal charge is transferred from the vertical transfer path to the horizontal transfer path by the number of stages h. Thereafter, if the horizontal transfer path and the empty transfer path are transferred (h × M) + e times, they are output as electrical signals via the FDA through the e stage of the empty transfer path.
That is, the horizontal transfer path transfers signal charges for h frames at a time and outputs them as electrical signals by the FDA. This electric signal is not a signal in which charges generated from spatially adjacent photodiodes are temporally adjacent. Therefore, it is necessary to rearrange the time order after output.

FIG. 3 is a timing chart of pixel readout described with reference to FIGS. In the figure, PG1 and PG2 are exposure, A1 to A4 are oblique transfer, B1 to B4 are vertical transfer (B1 and B3 are also used as A1 and A3 or independent), and C1 to C4 are pulses to perform horizontal transfer. TG in FIG. 8 is a transfer gate pulse for transferring charges from the vertical transfer path to the horizontal transfer path.
Usually, TG can be shared with B4 pulse, so it is omitted in this figure.

In FIG. 3, recording is completed within the recording period, and reading is performed during the reading period.
[Step S101]
First, when recording is started in the recording period, the electric charge photoelectrically converted by the photodiode by the PG pulse is taken out to the oblique transfer path and sequentially transferred by the oblique transfer pulse (A pulse). When charges are accumulated up to the last stage of the oblique transfer path by s times of exposure and transfer, the last stage charges are discarded on the CCD substrate when the next charge is transferred from the photodiode.
This recording state continues until an external trigger signal (not shown) that starts capturing is input. As a result, the charge for the immediately preceding s frames is always stored. Even after the external trigger signal is given, the recording state operation is continued by the number of stages corresponding to the predetermined number of frames.

[Step S102]
When a predetermined number of frames elapses from the external trigger signal, vertical transfer pulses (B pulses) having the same frequency as the A pulse are given v times, and the charge from the oblique transfer path is guided to the vertical transfer path without being discarded, Charges are transferred for v stages of the vertical transfer path, and the recording period ends. As a result, the vertical transfer path is filled with v × N charges. FIG. 1 corresponds to the state at this time.

[Step S103]
In the next readout period, first, every time B1 to B4 are driven by one pulse, C1 to C4 and TG are driven by one pulse, so that the charges stored in the vertical transfer path of FIG. Perform the sending operation. By repeating this operation h times, charges corresponding to h stages are transferred to the horizontal transfer path. During this time, the PG pulse and the A2 and A4 pulses are stopped. FIG. 2 corresponds to a state in which the h-stage vertical horizontal transfer is finished.

[Step S104]
Next, the pulses of C1 to C4 are driven (h × M) + e times including the empty transfer path, and the charges in the horizontal transfer path are output to the outside via the FDA.

[Step S105]
Steps S103 and S104 are repeated until all the charges of v × N stages of the vertical transfer path have been transferred.

[Step S106]
When the vertical transfer path becomes empty in step S105, the same operation as in step S102 is performed again, and the A pulse and the B pulse are driven v times so that the charge remaining in the oblique transfer path is transferred to the vertical transfer path by v stages. Transfer minutes. Then, operations similar to those in steps S104 to S105 are performed.

[Step S107]
Step S106 is repeated until the oblique transfer path becomes empty.

FIG. 4 is a configuration diagram of a conventional pixel peripheral recording type imaging apparatus.
Reference numeral 1 denotes an ISIS_CCD that is an image sensor.
Reference numeral 2 denotes a timing generator that gives the above-described pulses to the ISIS_CCD1.
Reference numeral 3 denotes a CDS (Correlated Double Sampling) amplifier that performs correlated double sampling on the signal from the FDA of ISIS_CCD1 and amplifies the signal at a predetermined amplification factor.
4 is an ADC (Analog) for quantizing the signal from the CDS amplifier 3.
to Digital Converter).
Reference numeral 5 denotes a rearrangement processing unit that rearranges signals read out from ISIS_CCD1 in terms of time and space into signals in units of frames.
Reference numeral 6 denotes an SDRAM (Synchronous Dynamic Random Access Memory) that stores a signal being rearranged by the rearrangement processing unit 5 and a frame image after the rearrangement.
US Pat. No. 5,355,165 JP 2000-165750 A Kazuya Kitamura, 10 others, "300,000-pixel ultra-high-speed high-sensitivity camera", general symposium 2005-2-1 (2005) on high-speed photography and photonics, Internet <URL: http: //mars.rist.u -tokai.ac.jp/2-1.pdf>

  As described above, since the number of stages of the vertical and horizontal transfer paths is fixed in ISIS_CCD, when the transfer path is filled with charges corresponding to the number of stages, it must be output to the outside of ISIS_CCD once. The arrangement of the pixel signals at this time is an arrangement for each frame.

  However, the charges output from the FDA are easily affected by adjacent charges. In particular, the first charge on the horizontal transfer path (G110 in FIGS. 1 and 2) is affected by the preceding empty transfer path (no charge). Thus, the level is lowered during FDA output, resulting in a black video signal. In addition, for example, at the stage of transfer other than the first charge, if the information of the h frame of the first row and the h stage is mixed in the first frame of the second row and the first stage due to the influence of G11h, the R120 cross Talk occurs. Such crosstalk that is not temporally or spatially adjacent (low correlation) is difficult to remove even using signal processing.

As a general phenomenon in the CCD, a phenomenon occurs in which an electric signal corresponding to the first pixel output from the horizontal transfer path via the FDA is lower in level than the subsequent signal every horizontal transfer. This is because the transfer path through which the first charge is transferred is empty, that is, a black signal, and the level drops due to the influence.
In the case of ISIS_CCD in which the horizontal transfer path is divided into a plurality of parts and the reading operation is performed in parallel, the level drop appears as point noise for each reading channel, and separation at a later stage is difficult.

  The present invention has been made in view of the above circumstances, and eliminates the effects of rearrangement processing, inter-frame crosstalk, lower level of the initial transfer, and the like caused by transferring charges that are not the same frame information adjacent to each other. An object of the present invention is to provide a pixel peripheral recording type imaging device.

N × M photodiodes arranged in N cycles in the vertical direction and M cycles in the horizontal direction, N photodiodes arranged vertically in each cycle in the horizontal direction, and v (v is an integer of 2 or more) M vertical transfer paths of v × N stages or more connected directly or indirectly at stage intervals and one end of each of the M vertical transfer paths are connected at h (h is an integer of 2 or more) stage intervals. A pixel peripheral recording type imaging device using an ISIS_CCD that reads out charges from the plurality of photodiodes through the horizontal transfer path.
Pixel peripheral recording type imaging, wherein the charges of M photodiodes arranged horizontally are read out from the horizontal transfer path for each vertical period of the arrangement while maintaining the horizontal arrangement order. apparatus.

Each of the M vertical transfer paths performs a v-stage transfer operation each time charge is received from a connected photodiode, and transfers imaging charges corresponding to one photodiode to the horizontal transfer path.
2. The pixel peripheral recording according to claim 1, wherein the horizontal transfer path performs line reading by performing transfer of h × M stages or more with the transferred imaging charge maintained at an interval of h stages. Type imaging device.

2. A DC regeneration unit that generates a black signal using a charge signal transferred in a stage between the imaging charges at the h-stage interval and subtracts the black signal from the imaging charge. 2. A pixel peripheral recording type imaging device according to 2.

The array of the M periods in the horizontal direction is further provided in such a manner that the array of photodiodes has a periodicity of L × M periods in the lateral direction, and is read out in parallel from the L horizontal transfer paths. The pixel peripheral recording type imaging device according to claim 2.

An s (s is an integer of 2 or more) stage memory transfer path is provided between the N photodiodes and the vertical transfer path, and the memory transfer path is operated at a higher speed than the vertical transfer path. The pixel peripheral recording type imaging device according to claim 2, wherein high-speed moving image shooting of s frames is performed.

According to the present invention,
1) The rearrangement of signals read from ISIS_CCD is not necessary.
2) Inter-frame crosstalk does not occur.
3) Dot noise that lowers the level of the first signal of horizontal transfer does not occur.
4) It is possible to suppress fluctuations in the black signal due to transfer for each pixel.

  5 and 6 are schematic diagrams for explaining pixel readout in the high-speed camera according to the present embodiment, and correspond to FIGS. 1 and 2 which are conventional schematic diagrams, respectively.

FIG. 5 shows a state immediately after the photographing period ends, and shows a state in which signal charges photoelectrically converted by each photodiode are stored in the memory / transfer path. However, it differs from the conventional FIG. 1 in that only one stage of charge is stored instead of the entire vertical transfer path.
The charge for one stage stored in the vertical transfer path is the first frame signal charge photoelectrically converted by each photodiode.

FIG. 6 shows a state in which the vertical transfer path is transferred by v stages from the state of FIG. 3 and stored in the horizontal transfer path. At this time, the charge stored in the horizontal transfer path is the signal charge of the first frame. In this state, since the signal charges on the horizontal transfer path are separated from each other by h stages, there is no influence by the adjacent charges.
Further, since the charges on the horizontal transfer path are signal charges of the same frame photoelectrically converted by spatially adjacent photodiodes, there is no need to rearrange in the temporal order when output via the FDA.

  The first horizontal transfer is the signal charge of the first frame that is photoelectrically converted by the photodiodes in the first row. Next, the charge transferred through the horizontal transfer path is the signal charge in the first frame photoelectrically converted by the photodiodes in the second row. Similarly, by repeating the third row, the fourth row,..., The Nth row, the signals of the first frame of all the pixels can be extracted. That is, horizontal transfer corresponds to line reading when the photodiodes arranged in the horizontal direction are taken as one line.

  When all the charges in the vertical transfer path are output, the charges in the oblique transfer paths in each stage are transferred to the vertical transfer path by one stage. This charge becomes the signal charge of the second frame that has been photoelectrically converted by each photodiode. Thereafter, if vertical and horizontal transfer is performed in the same manner, signals of all frames can be read out for each line and each frame.

  As described above, since the signal charges on the horizontal transfer path have an interval corresponding to h stages of the horizontal transfer path, after being output as an electrical signal via the FDA, h−1 charges between the signals. The average value of the black signal can be obtained by sampling the empty signal portion corresponding to. By taking the difference between this value and the electric signal corresponding to the original charge photoelectrically converted by the photodiode to be sampled next, it is possible to suppress the fluctuation of the black signal in the transfer.

FIG. 7 is a timing chart of pixel readout in the high-speed camera of this example. Recording is completed within the recording period, and reading is performed during the reading period.
[Step S201]
In the recording period, first, the same operation as in the conventional step S101 is performed.

[Step S202]
After step S201, oblique transfer and vertical transfer are performed only once. In other words, the A pulse and the B pulse that were given v times in S102 are given only once. A TG pulse having the same waveform as the B4 pulse is also given. FIG. 5 corresponds to the state at this time.

[Step S203]
In the readout period, the horizontal transfer pulses C1 to C4 (and TG pulse) are driven by one pulse every time one vertical transfer pulse B1 to B4 is driven as in the conventional case, and the charges stored in the vertical transfer path are transferred horizontally. Drive to the road. However, the number of pulses to be given is not h times but v times. The frequency of the pulse is lower than the recording period (assuming ultra-high speed shooting).
As described above, since the signal charge is present only in the first stage of the v-th vertical transfer path, even if v ≧ h, even if v-number of charges are transferred to the horizontal transfer path, the adjacent column as shown in FIG. Is not mixed with the electric charge from, and there is always an interval of h steps. That is, the relationship between v and h can be arbitrarily selected.

[Step S204]
After step S203, the same operation as step S104 is performed. That is, the C1 to C4 pulses are driven (h × M) + e times, and M charges transferred to the horizontal transfer path of each column are output to the outside via the FDA.
As a result, the signal output to the outside does not have the charge signals arranged for each pixel as in the prior art, but the charge signals imaged at intervals of h stages in the horizontal transfer path appear. The empty part between the captured charge signals is used as a black signal as described later.

[Step S205]
Steps S203 and S204 are repeated until all the N charges on the vertical transfer path have been transferred.

[Step S206]
When the vertical transfer path becomes empty in step S205, the same operation as in step S202 is performed again, and the A1-A4 pulse is driven once from the oblique transfer path connected to each photodiode, and the vertical transfer path becomes empty. The remaining charge is transferred by one stage to the transfer path. At this time, N rows of charges are simultaneously transferred to the vertical transfer path. Thereafter, operations similar to those in steps S203 to S205 are performed.

[Step S108]
Step S206 is repeated until the oblique transfer path becomes empty.

  Note that when performing continuous continuous shooting instead of ultra-high-speed shooting (memory recording) in which the number of frames is limited to the longest s + v, steps S201 to S205 may be repeated. At this time, in S201, the PG pulse is given once and the A pulse is given s times.

FIG. 8 is a pixel readout timing chart showing an example of a method using a TG pulse.
In this example, the gate is opened with a TG pulse only when charges are transferred from the vertical transfer path to the horizontal transfer path. That is, since the charges in the vertical transfer path are transferred to the horizontal transfer path only when the gate is opened by the TG pulse, the horizontal transfer path may be driven only when the charge is output.

Therefore, FIG. 8 is the same as FIG. 7 except for the TG pulse waveform and the horizontal transfer pulse in step S203.
Even when the TG pulse is used, the horizontal transfer pulses C1 to C4 may be given in the same manner as in FIG.
In the present embodiment (FIGS. 7 and 8), it is not necessary to transfer charges of the number of s frames captured by ultra-high-speed shooting to the vertical and horizontal transfer paths at high speed. It can be easily realized.

  As another modification, the charge interval at the time of horizontal transfer may be h / n (n is an integer of 2 or more), and information for n lines may be transferred by one horizontal transfer. In FIG. 7, if the horizontal transfer pulse driving is performed v times while the pulse driving of B1 to B4 for transferring the charges from the vertical to the horizontal in step S203 is performed v × N times, the horizontal transfer path is h / n. Charges are transferred at intervals.

FIG. 9 is a configuration diagram of the high-speed camera according to the present embodiment. The same components as those in the past are denoted by the same reference numerals and description thereof is omitted.
Instead of the timing generator 2, a timing generator 22 for generating pulses as shown in FIGS. 7 and 8 is provided. Further, in place of the rearrangement processing unit 5, a delay unit 23 and an adder 24 as DC regeneration means are newly provided.
Note that the ADC 4 performs A / D conversion at the same sample rate as the horizontal pulse as in the conventional case.

The delay unit 23 stores one or a plurality of signals that have been A / D converted at a timing at which charges captured by the photodiode are not included, and outputs the signals as black signals. This signal is generated from one or a plurality of signals in the vicinity of the imaging charge signal appearing at h sample intervals, and represents the black level for the charge signal. For example, a black signal can be obtained by arithmetically averaging a plurality of signals immediately before the imaging charge signal. In addition, the linearity can be improved by adding a few samples (including afterimage charges) immediately after the imaging charge signal, but the black signal used at that time has a gain corresponding to the number of added samples. To do.
The adder 24 regenerates the original DC component by subtracting the black signal output from the delay unit 23 from the imaging charge signal output from the ADC at the h sample period.

In the embodiment described above, only one horizontal transfer path is provided. However, for example, the configuration of FIG. 5 is repeated L (L is an integer) times in the horizontal direction so that parallel reading is performed from the L horizontal transfer paths. May be. The direct current reproducing means can eliminate the influence of the level reduction at the initial stage of reading, and can seamlessly synthesize the images read in parallel.

Diagram explaining conventional pixel readout of ISIS_CCD (immediately after shooting) Diagram explaining conventional pixel readout (during horizontal transfer) of ISIS_CCD Timing chart of pixel readout explained in FIG. 1 and FIG. Configuration diagram of conventional pixel peripheral recording type imaging device The figure explaining the pixel read-out (immediately after imaging | photography) of ISIS_CCD of embodiment of this invention The figure explaining pixel reading (during horizontal transfer) of ISIS_CCD of the embodiment of the present invention Timing chart of pixel readout explained in FIG. 5 and FIG. Pixel readout timing chart according to another embodiment Configuration diagram of a high-speed camera according to an embodiment of the present invention

Explanation of symbols

1: ISIS_CCD,
2, 22: Timing generator,
3: CDS amplifier,
4: ADC,
5: rearrangement processing unit,
6: SDRAM,
23: delay device, 24: adder.

Claims (5)

N × M photodiodes arranged in N cycles in the vertical direction and M cycles in the horizontal direction, N photodiodes arranged vertically in each cycle in the horizontal direction, and v (v is an integer of 2 or more) M vertical transfer paths of v × N stages or more connected directly or indirectly at stage intervals and one end of each of the M vertical transfer paths are connected at h (h is an integer of 2 or more) stage intervals. A pixel peripheral recording type imaging device using an ISIS_CCD that reads out charges from the plurality of photodiodes through the horizontal transfer path.
Pixel peripheral recording type imaging, wherein the charges of M photodiodes arranged horizontally are read out from the horizontal transfer path for each vertical period of the arrangement while maintaining the horizontal arrangement order. apparatus. Each of the M vertical transfer paths performs a v-stage transfer operation each time charge is received from a connected photodiode, and transfers imaging charges corresponding to one photodiode to the horizontal transfer path.
2. The pixel peripheral recording according to claim 1, wherein the horizontal transfer path performs line reading by performing transfer of h × M stages or more with the transferred imaging charge maintained at an interval of h stages. Type imaging device. 2. A DC regeneration unit that generates a black signal using a charge signal transferred in a stage between the imaging charges at the h-stage interval and subtracts the black signal from the imaging charge. 2. A pixel peripheral recording type imaging device according to 2. The array of the M periods in the horizontal direction is further provided in such a manner that the array of photodiodes has a periodicity of L × M periods in the lateral direction, and is read out in parallel from the L horizontal transfer paths. The pixel peripheral recording type imaging device according to claim 2. An s (s is an integer of 2 or more) stage memory transfer path is provided between the N photodiodes and the vertical transfer path, and the memory transfer path is operated at a higher speed than the vertical transfer path. The pixel peripheral recording type imaging device according to claim 2, wherein high-speed moving image shooting of s frames is performed.

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