JP2009218526A - Clock wiring structure, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure and a semiconductor device for effectively suppressing the variation of wiring shape. <P>SOLUTION: A wiring structure is provided with: clock wiring 11; a pair of first shield wirings 12 formed at the both sides of the clock wiring 11 along the clock wiring 11 in the same layer as that of the clock wiring 11; second shield wiring 13 formed so that the faced region of the clock wiring 11 and the pair of first shield wirings 12 can be covered in a layer different from that of the clock wiring 11 through the insulating layer; and an MIM capacity 30 in which a pair of electrodes (upper electrode 17 and lower electrode 18) is arranged so as to be faced through the insulating layer. At least one of the pair of electrodes of the MIM capacity 30 is formed in the same layer as that of the second shield wiring 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clock wiring structure of a semiconductor integrated circuit, a semiconductor device, and a method for manufacturing the semiconductor device.

  In large-scale and high-performance LSIs, a special clock distribution method such as a tree structure or a mesh structure with equal-length wiring is used to suppress clock skew and jitter. If wiring is randomly arranged in the upper and lower layers or the same layer adjacent to the clock wiring, it is difficult to accurately estimate the parasitic capacitance and the parasitic inductance. And it becomes difficult to accurately estimate waveform rounding and crosstalk. In order to solve this problem, a technique has been devised in which shield wiring is provided on the top, bottom, left and right of the clock wiring (for example, Patent Documents 1 and 2).

  FIG. 6 is a partial perspective view showing a conventional clock wiring structure disclosed in Patent Document 2. As shown in FIG. In FIG. 6, a pair of first shield wirings 102 are arranged in parallel on both sides of the clock wiring 101. The pair of first shield wirings 102 is formed in the same layer as the clock wiring 101. Under the clock wiring 101 and the first shield wiring 102, a second shield wiring 103 of a thick wiring is arranged. The second shield wiring 103 is a single wide wiring that covers at least portions corresponding to the clock wiring 101 and the pair of first shield wirings 102. The second shield wiring 103 is formed by a wiring layer below the clock wiring 101. The second shield wiring 103 is formed of a wiring layer that is higher than the signal wiring 104 of the other wiring layer.

  The pair of first shield wirings 102 and the second shield wirings 103 having a wide line width are electrically connected via via wirings (not shown) connecting the wiring layers. Both the first shield wiring 102 and the second shield wiring 103 are connected to the ground (ground) potential. In this way, by forming the second shield wiring 103 having a wide line width in the wiring layer between the signal wiring 104 and the clock wiring 101, clock skew caused by crosstalk with the signal wiring 104 is reduced. be able to.

The lower second shield wiring 103 can be formed as a wiring having a line width comparable to that of the clock wiring 101. However, by forming a plate-like thick wiring as shown in FIG. A microstrip structure is formed. Thereby, the effect of skew reduction can be enhanced. In this case, the second shield wiring 103 needs to cover at least a region facing the target clock wiring 101 and the shield wirings 102 on both sides thereof.
JP-A-8-274167 JP 2003-158186 A

  In the clock wiring structure disclosed in Patent Document 2 shown in FIG. 6, the second shield wiring 103 having a thick line width is disposed in a predetermined region facing the target clock wiring 101. Therefore, when the second shield wiring 103 is formed of Cu (copper) used as a normal wiring, another normal wiring can be provided in the same layer as the second shield wiring 103. That is, the other region of the wiring layer in which the second shield wiring 103 is formed is used as a wiring layer for normal signals and power supplies other than the clock wiring 101.

  However, it is difficult to accurately form a normal wiring in the same layer as the second shield wiring 103 having a thick line width. That is, it is difficult to form both the second shield wiring 103 having a large line width and a large pattern area and the normal wiring having a small line width and a small pattern area in the same layer with the same Cu. Due to the difference in density between the patterns, a proximity effect at the time of lithography, a microloading effect at the time of etching, dishing (wiring dent) in the CMP process, and the like occur, and the wiring shape varies. In order to avoid the above, a dedicated wiring layer for the second shield wiring 103 having a thick line width is provided separately from the normal wiring, and this is formed by sputtering a metal different from Cu, for example, TiN or TaN. For example, a thick shield wiring having a large area can be formed without affecting other normal wiring during lithography or etching, but the introduction of such a dedicated wiring layer causes an increase in manufacturing cost. In other words, with the conventional clock wiring structure, it has been difficult to achieve high performance and low cost.

  The wiring structure according to the present invention includes a clock wiring, a pair of first shield wirings provided on both sides along the clock wiring in the same layer as the clock wiring, and different through the clock wiring and an insulating layer. A second shield wiring provided so as to cover the clock wiring and the pair of first shield wirings facing each other, and a MIM capacitor in which a pair of electrodes are arranged to face each other with an insulating layer interposed therebetween. At least one of the pair of electrodes of the MIM capacitor is provided in the same layer as the second shield wiring. With such a configuration, the second shield wiring of the thick wiring can be formed in a wiring layer different from the normal wiring. Therefore, the second shield wiring having a large pattern area can be formed without affecting other normal wiring during lithography or etching. Furthermore, by sharing the wiring layer with the electrode of the MIM capacitor formed as a decoupling capacitor, an increase in manufacturing cost can be suppressed.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a clock wiring and an MIM capacitor, and is provided on a substrate along the clock wiring and both sides of the clock wiring. And a pair of electrodes of the MIM capacitor and at least one of the pair of electrodes before or after forming the clock line and the pair of first shield lines. A second shield wiring provided in a layer and covering a region where the clock wiring and the pair of first shield wirings are opposed to each other is formed in a different layer via the clock wiring and an insulating layer. Thereby, the second shield wiring of the thick wiring can be formed in a wiring layer different from the normal wiring. Therefore, the second shield wiring having a large pattern area can be formed without affecting other normal wiring during lithography or etching. Furthermore, by sharing the wiring layer with the electrode of the MIM capacitor formed as a decoupling capacitor, an increase in manufacturing cost can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the wiring structure which can suppress the dispersion | variation in wiring shape effectively, a semiconductor device, and the manufacturing method of a semiconductor device can be provided at low cost.

  The preferred embodiments of the present invention will be described below. The following description explains the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and description is abbreviate | omitted suitably.

Embodiment 1 FIG.
First, the semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 1 is a partial perspective view showing a clock wiring structure according to the first embodiment. FIG. 2 is a top view showing the clock wiring structure according to the first embodiment. In FIG. 1, only a part of each component is cut and described.

  1 and 2, the semiconductor device 1 according to the present embodiment includes a wiring substrate (not shown) provided with a wiring structure including a clock wiring 11, an MIM capacitor 30, and a signal wiring 14.

  A pair of first shield wires 12 are arranged in parallel on both sides of the clock wire 11. The pair of first shield lines 12 are formed in the same layer as the clock line 11. Each first shield wiring 12 is provided along the clock wiring 11. A clock wiring 11 is disposed between one first shield wiring 12 and the other first shield wiring 12. The clock wiring 11 is provided apart from each first shield wiring 12.

  Under the clock wiring 11 and the first shield wiring 12, a second shield wiring 13 of a thick wiring is arranged. The second shield wiring 13 is a single wiring having a large width so as to cover at least the area where the clock wiring 11 and the pair of first shield wirings 12 face each other. The second shield wiring 13 is formed by a wiring layer below the clock wiring 11. In other words, the second shield wiring 13 is disposed on the clock wiring 11 and the pair of first shield wirings 12 through an insulating layer (not shown). The second shield wiring 13 is formed by a wiring layer above the wiring layer provided with the signal wiring 14. Accordingly, the second shield wiring 13 is formed in the wiring layer between the signal wiring 14 and the clock wiring 11. The second shield wiring 13 and the signal wiring 14 are insulated from each other by an insulating layer (not shown) provided therebetween.

  As shown in FIG. 2, the pair of first shield wirings 12 is electrically connected to the second shield wiring 13 having a wide line width via a via wiring 19 connecting the wiring layers. The via wiring 19 is a conductive layer embedded in a through hole formed in an insulating layer (not shown) between the shield wiring 12 and the shield wiring 13. The first shield wiring 12 and the second shield wiring 13 are connected to a ground (ground) potential.

  In the clock wiring structure configured as described above, the first shield wiring 12 and the second shield wiring 13 can function as a noise shield of the clock wiring 11. That is, the second shield wiring 13 can reduce clock skew caused by crosstalk with other wirings provided below the second shield wiring 13 such as the signal wiring 14. In addition, the first shield wiring 12 reduces clock skew caused by crosstalk with other wirings formed in the same layer as the clock wiring 11 such as a power wiring 15 and a ground wiring 16 described later.

  Further, the semiconductor device 1 according to the present embodiment is provided with an MIM (Metal-Insulator-Metal) capacitor 30 as a decoupling capacitor for reducing power supply noise. The MIM capacitor 30 has two plate-like electrodes (upper electrode 17 and lower electrode 18) arranged to face each other via an insulating layer (not shown). Of the two electrodes, the upper electrode 17 formed on the upper side is connected to the power supply wiring 15 via the Via wiring 20, as shown in FIG. The lower electrode 18 formed on the lower side is connected to the ground wiring 16 via the Via wiring 21.

  Here, in the present embodiment, as shown in FIG. 1, the second shield wiring 13 of the clock wiring 11 and the lower electrode 18 of the MIM capacitor 30 are provided in the same layer. That is, the second shield wiring 13 having a thick wiring is formed by the same wiring layer as the lower electrode 18 of the MIM capacitor 30. The plate-like electrode of the MIM capacitor 30 may be formed as a thin film using a metal different from normal wiring such as TaN, as “Application of on-chip MIM decoupling capacitor for 90 nm SOI microprocessor”, D. Roberts et al., IEDM 2005, Pages 72-75. Therefore, in the present embodiment, the second shield wiring 13 is formed of a metal different from the same normal wiring as the lower electrode 18. Here, the clock wiring 11, the shield wiring 12, the signal wiring 14, the power supply wiring 15, and the ground wiring 16 are made of, for example, Cu as a metal used for the normal wiring. On the other hand, the second shield wiring 13, the upper electrode 17, and the lower electrode 18 are formed of, for example, TiN as a metal different from the normal wiring.

  Then, the manufacturing method of the semiconductor device 1 concerning this Embodiment is demonstrated. First, the signal wiring 14 is formed on a wiring substrate such as a wafer. Cu wiring is formed as the signal wiring 14 through processes such as a groove etching process, a plating process, and a CMP process.

  Next, after forming an insulating layer on the signal wiring 14, a material to be the second shield wiring 13 and the lower electrode 18 is formed on the entire surface of the wiring substrate by sputtering. In the present embodiment, a metal different from the normal wiring is used as a material for the second shield wiring 13 and the lower electrode 18. For example, here, TiN is deposited as a material for the second shield wiring 13 and the lower electrode 18. Then, through processes such as a photolithography process, an etching process, and a resist removal process, the formed material is patterned into a predetermined shape to form the second shield wiring 13 and the lower electrode 18.

  Further, after forming an insulating layer covering these, a material to be the upper electrode 17 is formed again on the entire surface of the wiring substrate by sputtering. Here, as the material for the upper electrode 17, similarly, TiN which is a metal different from the normal wiring is formed. Then, the upper electrode 17 is formed by patterning the deposited material through processes such as a photolithography process, an etching process, and a resist removal process.

  Next, after forming an insulating layer covering the upper electrode 17, a through hole is opened in the insulating film on the second shield wiring 13, the upper electrode 17, and the lower electrode 18. As a result, through holes reaching the second shield wiring 13, the upper electrode 17, and the lower electrode 18 are formed, and the surfaces of the second shield wiring 13, the upper electrode 17, and the lower electrode 18 are exposed. Then, via wirings 19, 20, and 21 are formed in the through holes.

  Thereafter, Cu wiring is formed as the clock wiring 11, the first shield wiring 12, the power supply wiring 15, and the ground wiring 16 through processes such as a groove etching process, a plating process, and a CMP process. Thus, the first shield wiring 12 that is electrically connected to the second shield wiring via the via wiring 19 is formed. Further, the power supply wiring 15 that is electrically connected to the upper electrode 17 through the Via wiring 20 is formed. Further, a ground wiring 16 that is electrically connected to the lower electrode 18 via the Via wiring 21 is formed. Through the above steps, the semiconductor device 1 according to the present embodiment is completed.

  In the above description, the second shield wiring 13 is formed in the same wiring layer as the lower electrode 18 of the MIM capacitor 30, but may be formed in the same wiring layer as the upper electrode 17 of the MIM capacitor 30. In addition, the second shield wiring 13 is not limited to a single layer structure constituted by one wiring layer, and the second shield wiring 13 is formed of a wiring layer that is the same as the upper electrode 17 and a wiring layer that is the same as the lower electrode 18. Both may be formed into a double structure.

  As described above, in the present embodiment, the second shield wiring 13 of the wide wiring is formed in the same layer as at least one of the electrodes of the MIM capacitor 30. That is, by forming the second shield wiring 13 having a large line width and a large pattern area in the same layer as the upper electrode 17 and the lower electrode 18 having the same pattern area, the difference in pattern density can be reduced. Thereby, in the formation of the second shield wiring 13 and the MIM capacitor 30, it is possible to suppress the occurrence of the proximity effect during lithography and the microloading effect during etching due to the difference in density between the patterns. Further, by sharing the wiring layer with the electrode of the MIM capacitor 30 formed as the decoupling capacitor, the second shield wiring 13 can suppress an increase in manufacturing cost.

  Further, the second shield wiring 13 is formed of a dedicated wiring layer different from the normal wiring. Thereby, both the normal wiring and the second shield wiring 13 can be formed under optimum process conditions. Therefore, the second shield wiring 13 having a large pattern area can be formed without affecting the normal wiring. Further, the material to be the second shield wiring 13 is formed by sputtering. As a result, the second shield wiring 13 having a uniform film thickness can be formed without going through the CMP process, so that dishing does not occur. From the above, according to the present embodiment, it is possible to provide a wiring structure, a semiconductor device, and a manufacturing method of the semiconductor device that can effectively suppress variations in the wiring shape at a low cost.

  In the present embodiment, the case where the second shield wiring 13 is formed apart from the MIM capacitor 30 has been exemplarily described. However, the second shield wiring 13 is formed extending from the MIM capacitor 30. Is also possible. FIG. 3 is a partial perspective view showing a clock wiring structure according to another example of the first embodiment. As shown in FIG. 3, the second shield wiring 13 may be formed extending from the lower electrode 18. That is, as shown in FIGS. 1 and 2, the second shield wiring 13 and the lower electrode 18 may be formed separately as separate patterns, or as shown in FIG. The electrode 18 may be integrally formed as one pattern. FIG. 4 is a partial perspective view showing a clock wiring structure according to still another example of the first embodiment. As shown in FIG. 4, the second shield wiring 13 may be formed extending from both the upper electrode 17 and the lower electrode 18.

Other embodiments.
The clock wiring is not limited to the above wiring structure. FIG. 5 is a partial perspective view showing a clock wiring structure according to another embodiment. Although the MIM capacitor 30 is not shown in FIG. 5, the second shield wiring 13 is formed in the same layer as the lower electrode 18 of the MIM capacitor 30 as in the semiconductor device 1 shown in FIG. In the semiconductor device 2 shown in FIG. 5, a differential clock pair wiring is formed by two clock wirings 11. A pair of first shield wirings 12 are arranged outside these two clock wirings 11. In the wiring layer between the clock wiring 11 and the signal wiring 14, a second shield wiring 13 having a thick wiring is formed so as to cover the opposing portions of the clock wiring 11 and the first shield wiring 12. Although not shown in FIG. 5, the second shield wiring 13 is provided in the same wiring layer as the lower electrode 18 of the MIM capacitor. Therefore, the second shield wiring 13 is formed of a metal different from normal wiring such as the clock wiring 11, the first shield wiring 12, and the signal wiring 14.

  As in the first embodiment, the second shield wiring 13 of the differential clock pair wiring is not limited to the same wiring layer as the lower electrode 18, but may be the same wiring layer as the upper electrode 17 of the MIM capacitor 30. Good. The second shield wiring 13 may have a double structure formed by both the same wiring layer as the upper electrode 17 and the same wiring layer as the lower electrode 18. Further, the second shield wiring may be extended from the upper electrode 17, the lower electrode 18, or both of them. Thus, if the second shield wiring 13 of the differential clock pair wiring is a wiring structure formed in the same layer as at least one of the electrodes of the MIM capacitor 30 and in a wiring layer different from the normal wiring, The same effects as in the first mode can be obtained. Thus, the second shield wiring 13 having a large pattern area can be formed without affecting the normal wiring. Therefore, as in the first embodiment, it is possible to provide a wiring structure, a semiconductor device, and a method for manufacturing the semiconductor device that can effectively suppress variations in the wiring shape at a low cost.

  The second shield wiring 13 is not limited to the above wiring structure provided in the lower layer of the clock wiring 11. It goes without saying that the second shield wiring 13 may be provided in the upper layer of the clock wiring 11 or both the upper layer and the lower layer along the clock wiring 11 and the first shield wiring 12.

  1, 3, and 4, the second shield wiring 13, the signal wiring 14, and the upper electrode 17 are provided below the clock wiring 11, the first shield wiring 12, the power supply wiring 15, and the ground wiring 16. , And the lower electrode 18 are filled with an insulating layer, but the insulating layer is omitted in the figure. In FIG. 2, the signal wiring 14 shown in FIG. 1 is omitted. In FIG. 5, similarly, an insulating layer is filled below the clock wiring 11 and the first shield wiring 12 except for the second shield wiring 13 and the signal wiring 14. Is omitted.

  Moreover, in FIGS. 1-5, only a part of each component is cut | disconnected and described. In general, the clock wiring 11 extends long and often includes a bent portion and a branched portion in the middle. However, if the clock wiring 11 is bent, the first shield wiring 12 is bent accordingly, and the clock wiring 11 is branched. If so, it branches in accordance with this and is arranged along the clock wiring 11. Similarly, the second shield wiring 13 is disposed along the clock wiring 11 and the first shield wiring 12.

  The above description describes the embodiment of the present invention, and the present invention is not limited to the above embodiment. Moreover, those skilled in the art can easily change, add, and convert each element of the above embodiment within the scope of the present invention.

3 is a partial perspective view showing a clock wiring structure according to the first embodiment. FIG. FIG. 3 is a top view showing a clock wiring structure according to the first embodiment. FIG. 10 is a partial perspective view showing a clock wiring structure according to another example of the first embodiment. FIG. 10 is a partial perspective view showing a clock wiring structure according to still another example of the first embodiment. It is a fragmentary perspective view which shows the clock wiring structure which concerns on other embodiment. It is a fragmentary perspective view which shows the conventional clock wiring structure.

Explanation of symbols

1, 2 semiconductor device, 11 clock wiring,
12 1st shield wiring, 13 2nd shield wiring,
14 signal wiring, 15 power wiring, 16 ground wiring,
17 upper electrode, 18 lower electrode, 30 MIM capacity,
101 clock wiring, 102 first shield wiring,
103 Second shield wiring, 104 Signal wiring

Claims (8)

Clock wiring,
A pair of first shield wirings provided on both sides of the clock wiring in the same layer as the clock wiring;
A second shield wiring provided so as to cover a region where the clock wiring and the pair of first shield wirings are opposed to each other in different layers through the clock wiring and an insulating layer;
A pair of electrodes and an MIM capacitor disposed opposite to each other with an insulating layer interposed therebetween,
A wiring structure in which at least one of the pair of electrodes of the MIM capacitor is provided in the same layer as the second shield wiring.   The wiring structure according to claim 1, wherein the second shield wiring is formed of a metal different from the clock wiring and the first shield wiring.   The wiring structure according to claim 1, wherein the second shield wiring has a double structure provided in the same layer as both of the pair of electrodes of the MIM capacitor.   The wiring structure according to claim 1, wherein the second shield wiring is formed to extend from the electrode of the MIM capacitor.   A semiconductor device provided with the wiring structure according to claim 1. A method of manufacturing a semiconductor device having a clock wiring and an MIM capacitor,
Forming a clock wiring and a pair of first shield wirings provided on both sides of the clock wiring on the substrate;
Before or after the clock wiring and the pair of first shield wirings are formed, the pair of electrodes of the MIM capacitor and at least one of the pair of electrodes are provided in the same layer, and the clock wiring and the pair of first shield wirings A method of manufacturing a semiconductor device, wherein a second shield wiring that covers a region where one shield wiring is opposed is formed in a different layer through the clock wiring and an insulating layer. At least one of the pair of electrodes of the MIM capacitor and the second shield wiring are
A metal different from the clock wiring and the first shield wiring is formed by sputtering,
The method of manufacturing a semiconductor device according to claim 6, wherein the formed metal is patterned by etching. Clock wiring,
A first shield wiring that is in the same layer as the clock wiring and is adjacent to the extending direction of the clock wiring;
A second shield wiring disposed in a layer different from the clock wiring and at least under the clock wiring;
A semiconductor device comprising: an MIM capacitor in which the second shield wiring is an upper electrode or a lower electrode.

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