JP2009218441A - Multilayer circuit board, and method for manufacturing the same - Google Patents

Multilayer circuit board, and method for manufacturing the same Download PDF

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JP2009218441A
JP2009218441A JP2008061740A JP2008061740A JP2009218441A JP 2009218441 A JP2009218441 A JP 2009218441A JP 2008061740 A JP2008061740 A JP 2008061740A JP 2008061740 A JP2008061740 A JP 2008061740A JP 2009218441 A JP2009218441 A JP 2009218441A
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circuit board
chip component
multilayer circuit
resin film
insulating material
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Hiroteru Kamiya
博輝 神谷
Motonori Shimizu
元規 清水
Koji Kondo
宏司 近藤
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Denso Corp
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Denso Corp
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<P>PROBLEM TO BE SOLVED: To provide a multilayer circuit board in which cracks are hardly generated in an insulating base existing around a chip component, and to provide a method for manufacturing the multilayer circuit board. <P>SOLUTION: In the multilayer circuit board 100, the insulating base 1 is formed by sticking resin films composed of thermoplastic resin and the chip component is buried in the insulating base 1. intermediate insulating materials 5a, 5b of which the coefficient of thermal expansion in a base thickness direction (Z direction) is a middle between that of the insulating base 1 and that of the chip component 3 are arranged so as to be abutted on the side face of the chip component 3 in the base thickness direction (Z direction). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板およびその製造方法に関する。   The present invention relates to a multilayer circuit board in which resin films made of a thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material, and a method for manufacturing the same.

熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板が、例えば特開2006−73763号公報(特許文献1)に開示されている。   A multilayer circuit board in which resin films made of thermoplastic resin are bonded to each other to form an insulating base material and chip components are embedded in the insulating base material is disclosed in, for example, Japanese Patent Application Laid-Open No. 2006-73763 (Patent Document 1). ).

図10は、上記従来の多層回路基板の一例を示す図で、図10(a)は、多層回路基板90を模式的に示した上面図である。また、図10(b)と図10(c)は、それぞれ、図10(a)における一点鎖線A−Aと二点鎖線B−Bの断面を実物の写真で示した図である。   FIG. 10 is a view showing an example of the conventional multilayer circuit board, and FIG. 10A is a top view schematically showing the multilayer circuit board 90. FIG. 10B and FIG. 10C are cross-sectional views of the dashed-dotted line AA and the alternate long and two short dashes line BB in FIG.

図10に示す多層回路基板90は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材1が形成され、該絶縁基材1中にチップ部品3が埋め込まれてなる多層回路基板である。尚、図10(b)と図10(c)における符号2の部分は、銅からなる導体パターンであり、符号4の部分は、導電ペーストを焼結させた接続導体の部分である。   A multilayer circuit board 90 shown in FIG. 10 is a multilayer circuit board in which resin films made of thermoplastic resin are bonded to each other to form an insulating base material 1 and chip components 3 are embedded in the insulating base material 1. is there. In FIG. 10B and FIG. 10C, reference numeral 2 represents a conductor pattern made of copper, and reference numeral 4 represents a connection conductor portion obtained by sintering conductive paste.

抵抗やコンデンサ等の電気回路素子を多層回路基板の絶縁基材1中に内蔵する場合には、上記のようなチップ部品3に限らず、薄膜や厚膜技術により形成して絶縁基材1中に埋め込むことも可能である。しかしながら、複数枚の樹脂フィルムを熱プレスにより一括して接着させる上記多層回路基板の製造においては、その抵抗値や容量値の形成範囲および形成精度から、前者のチップ部品3を該多層回路基板に内蔵させる場合が多い。
特開2006−73763号公報
When an electric circuit element such as a resistor or a capacitor is built in the insulating base 1 of the multilayer circuit board, the insulating base 1 is not limited to the chip component 3 as described above but is formed by a thin film or thick film technique. It is also possible to embed in However, in the production of the multilayer circuit board in which a plurality of resin films are bonded together by hot pressing, the former chip component 3 is attached to the multilayer circuit board from the formation range and formation accuracy of the resistance value and the capacitance value. Often built-in.
JP 2006-73763 A

図11は、図10の多層回路基板90について、チップ部品3の周りの絶縁基材1にかかる応力をシミュレートした結果の一例である。図11(a)は、1/4解析モデルの斜視図であり、図11(b)は、そのシミュレーション結果を等応力線で示した図である。尚、図11(a)中の破線は、絶縁基材1を構成する接着前の樹脂フィルムの境界を示している。   FIG. 11 is an example of a result of simulating the stress applied to the insulating base material 1 around the chip component 3 for the multilayer circuit board 90 of FIG. FIG. 11A is a perspective view of the ¼ analysis model, and FIG. 11B is a diagram showing the simulation result by isostress lines. In addition, the broken line in Fig.11 (a) has shown the boundary of the resin film before the adhesion which comprises the insulating base material 1. FIG.

図11(b)に示すように、シミュレーション結果によれば、絶縁基材1におけるチップ部品3の厚さ方向の中央部付近に当接した部分が応力集中部となり、25〜30MPa程度の応力が発生する。実際に製造した多層回路基板90においても、特に30MPa程度の最大応力がかかるチップ部品3の長辺側の絶縁基材1においては、経時変化等で亀裂が発生し易い。   As shown in FIG. 11 (b), according to the simulation result, the portion of the insulating substrate 1 that is in contact with the vicinity of the central portion in the thickness direction of the chip component 3 becomes a stress concentration portion, and a stress of about 25 to 30 MPa is applied. appear. Even in the actually manufactured multilayer circuit board 90, cracks are likely to occur due to changes over time in the insulating base material 1 on the long side of the chip component 3 to which the maximum stress of about 30 MPa is applied.

そこで本発明は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板およびその製造方法であって、チップ部品の周りの絶縁基材に亀裂が発生し難い多層回路基板およびその製造方法を提供することを目的としている。   Accordingly, the present invention provides a multilayer circuit board in which resin films made of a thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material, and a method for manufacturing the same. An object of the present invention is to provide a multilayer circuit board in which cracks are unlikely to occur in an insulating base material around a component and a method for manufacturing the same.

請求項1に記載の多層回路基板は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板において、基板厚さ方向における熱膨張率が前記絶縁基材の熱膨張率と前記チップ部品の熱膨張率の中間にある中間絶縁材が、チップ部品の基板厚さ方向における側面に当接するようにして配置されてなることを特徴としている。   The multilayer circuit board according to claim 1, wherein a resin film made of a thermoplastic resin is bonded to each other to form an insulating base material, and a chip component is embedded in the insulating base material. An intermediate insulating material whose thermal expansion coefficient in the thickness direction is intermediate between the thermal expansion coefficient of the insulating base material and the thermal expansion coefficient of the chip component is disposed so as to contact the side surface of the chip component in the substrate thickness direction. It is characterized by.

熱可塑性樹脂からなる複数枚の樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる従来の多層回路基板においては、複数枚の樹脂フィルムからなる絶縁基材とチップ部品とが、直接当接した構造となっている。該構造の従来の多層回路基板についてシミュレーションを行ったところ、絶縁基材におけるチップ部品の厚さ方向の中央部付近に当接した部分が応力集中部となり、25〜30MPa程度の応力が発生する。このため、実際に製造した従来の多層回路基板においても、特に30MPa程度の最大応力がかかるチップ部品の長辺側の絶縁基材においては、経時変化等で亀裂が発生し易い。   In a conventional multilayer circuit board in which a plurality of resin films made of a thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material, The insulating base material and the chip component are in direct contact with each other. When a simulation was performed on a conventional multilayer circuit board having such a structure, a portion of the insulating base material in contact with the vicinity of the central portion in the thickness direction of the chip component becomes a stress concentration portion, and a stress of about 25 to 30 MPa is generated. For this reason, even in a conventional multilayer circuit board actually manufactured, cracks are likely to occur due to changes over time or the like, particularly in the insulating base on the long side of a chip component to which a maximum stress of about 30 MPa is applied.

上記応力を分析した結果、以下の要因で上記応力が発生しているという結論に至った。すなわち、抵抗やコンデンサ等のチップ部品は、一般的に厚みが0.1mm以上あることが多く、またセラミック系の材料で構成されていることが多いため、線膨張率が10ppm以下と低い傾向がある。これに対して、上記多層回路基板の熱可塑性樹脂からなる複数枚の樹脂フィルムが相互に接着された絶縁基材は、基板面内の線膨張率を銅からなる導体パターンの線膨張率である17ppmと同程度に合わせているが、厚さ方向の線膨張率は、一般的に基板面内の線膨張率の数倍から数十倍ある場合が多い。このため、多層回路基板におけるチップ部品と絶縁基材の厚さ方向の線膨張率差で、絶縁基材におけるチップ部品の厚さ方向の中央部付近に当接した部分が応力集中部となり、25〜30MPa程度の応力が発生している。   As a result of analyzing the stress, it was concluded that the stress was generated due to the following factors. That is, chip parts such as resistors and capacitors generally have a thickness of 0.1 mm or more, and are often made of a ceramic material. Therefore, the linear expansion coefficient tends to be as low as 10 ppm or less. is there. On the other hand, the insulating base material in which a plurality of resin films made of the thermoplastic resin of the multilayer circuit board are bonded to each other has the linear expansion coefficient of the conductor pattern made of copper as the linear expansion coefficient in the substrate surface. The linear expansion coefficient in the thickness direction is generally several times to several tens of times larger than the linear expansion coefficient in the substrate surface. For this reason, due to the difference in linear expansion coefficient in the thickness direction between the chip component and the insulating substrate in the multilayer circuit board, the portion in contact with the vicinity of the central portion in the thickness direction of the chip component in the insulating substrate becomes a stress concentration portion, A stress of about 30 MPa is generated.

そこで、請求項1に記載の多層回路基板においては、基板厚さ方向における熱膨張率が絶縁基材の熱膨張率とチップ部品の熱膨張率の中間にある中間絶縁材を、チップ部品の基板厚さ方向における側面に当接するようにして配置している。これによって、チップ部品と絶縁基材の厚さ方向の線膨張率差を該中間絶縁材で緩和して、チップ部品の周りの絶縁基材にかかる応力を低減することができる。シミュレーションによれば、例えば上記線膨張率が10ppmのチップ部品に対して、線膨張率が17ppmの中間絶縁材を絶縁基材との間に介在させることで、チップ部品の周りの絶縁基材にかかる応力を13〜16MPa程度まで低減することができる。このため、実際に製造する該多層回路基板においても、経時変化等で亀裂が発生し難く、該多層回路基板は、高い信頼性を有した多層回路基板となっている。   Accordingly, in the multilayer circuit board according to claim 1, an intermediate insulating material having a thermal expansion coefficient in the substrate thickness direction between the thermal expansion coefficient of the insulating base and the thermal expansion coefficient of the chip component is used as the substrate of the chip component. It arrange | positions so that it may contact | abut on the side surface in the thickness direction. As a result, the difference in linear expansion coefficient between the chip component and the insulating base material in the thickness direction can be relaxed by the intermediate insulating material, and the stress applied to the insulating base material around the chip part can be reduced. According to the simulation, for example, with respect to the chip component having a linear expansion coefficient of 10 ppm, an intermediate insulating material having a linear expansion coefficient of 17 ppm is interposed between the insulating base material and the insulating base material around the chip component. Such stress can be reduced to about 13 to 16 MPa. For this reason, even in the multilayer circuit board that is actually manufactured, cracks are unlikely to occur due to changes over time, and the multilayer circuit board is a highly reliable multilayer circuit board.

以上のようにして、上記多層回路基板は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板であって、チップ部品の周りの絶縁基材に亀裂が発生し難い多層回路基板とすることができる。   As described above, the multilayer circuit board is a multilayer circuit board in which resin films made of a thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material. Thus, a multilayer circuit board in which cracks are unlikely to occur in the insulating base material around the chip component can be obtained.

上記多層回路基板において、請求項2に記載のように、前記チップ部品が、略直方体形状である場合には、前記中間絶縁材が、前記チップ部品の基板厚さ方向における4つの側面に当接するようにして配置されてなることが好ましい。特に、請求項3に記載のように、前記中間絶縁材が、前記チップ部品の基板厚さ方向における4つの側面を取り囲むようにして配置されてなる構成が好適である。これによって、チップ部品の周りの絶縁基材にかかる応力を、4つの側面の周りで均等に低減することができる。   In the multilayer circuit board, as described in claim 2, when the chip component has a substantially rectangular parallelepiped shape, the intermediate insulating material abuts on four side surfaces in the substrate thickness direction of the chip component. It is preferable that they are arranged in this manner. In particular, a configuration in which the intermediate insulating material is disposed so as to surround four side surfaces in the substrate thickness direction of the chip component is preferable. Thereby, the stress applied to the insulating base material around the chip component can be reduced evenly around the four side surfaces.

上記多層回路基板においては、請求項4に記載のように、前記中間絶縁材が、前記チップ部品の側面における厚さ方向の中央部を含んだ1/3以上の厚さ領域に当接するようにして配置されてなることが好ましい。シミュレーションによれば、前述したチップ部品と絶縁基材の厚さ方向の線膨張率差で発生する応力は、チップ部品の厚さ方向の中央部付近が応力集中部となる。従って、上記のようにチップ部品の側面における厚さ方向の中央部を含んだ1/3以上の厚さ領域に当接するように中間絶縁材を配置することで、該中間絶縁材による応力低減効果を効果的に発揮させることができる。特に、請求項5に記載のように、前記中間絶縁材が、前記チップ部品の側面の全領域に当接するようにして配置されてなる構成とすると効果的である。   In the multilayer circuit board, as described in claim 4, the intermediate insulating material abuts on a thickness region of 1/3 or more including a central portion in a thickness direction on a side surface of the chip component. Are preferably arranged. According to the simulation, the stress generated by the difference in linear expansion coefficient in the thickness direction between the chip component and the insulating base described above becomes a stress concentration portion near the center in the thickness direction of the chip component. Therefore, by arranging the intermediate insulating material so as to contact the thickness region of 1/3 or more including the central portion in the thickness direction on the side surface of the chip component as described above, the stress reducing effect by the intermediate insulating material Can be effectively exhibited. In particular, as described in claim 5, it is effective if the intermediate insulating material is arranged so as to be in contact with the entire region of the side surface of the chip component.

また、上記多層回路基板においては、請求項6に記載のように、基板面内における前記中間絶縁材の幅が、前記チップ部品の厚さの1/10以上であること好ましい。応力低減効果だけみれば上記中間絶縁材の幅は厚いほど望ましいが、シミュレーションによれば、中間絶縁材の幅を上記のようにチップ部品の厚さの1/10以上とすることで、顕著な応力低減効果を得ることができる。   In the multilayer circuit board, it is preferable that the width of the intermediate insulating material in the substrate surface is 1/10 or more of the thickness of the chip component. From the viewpoint of the stress reduction effect, it is desirable that the width of the intermediate insulating material is thicker. However, according to the simulation, it is remarkable that the width of the intermediate insulating material is 1/10 or more of the thickness of the chip component as described above. A stress reduction effect can be obtained.

上記多層回路基板は、特に、請求項7に記載のように構成することが好ましい。すなわち、上記多層回路基板において、前記樹脂フィルムを構成している繊維状分子が、該樹脂フィルムのフィルム面内において、前記繊維状分子の長軸方向を略平行にして並んで配列し、前記繊維状分子の長軸方向を平均した該樹脂フィルムの方向をMDとし、前記MDに垂直な該樹脂フィルムの方向をTDとしたとき、前記樹脂フィルムが、前記MDと前記TDとで線膨張率または強度に差がある異方性フィルムであり、前記樹脂フィルムのMDが基板厚さ方向となるようにして、前記樹脂フィルムが前記チップ部品の基板厚さ方向における側面に当接するようにして配置されてなり、前記樹脂フィルムが、前記中間絶縁材として利用されてなる構成とする。   The multilayer circuit board is particularly preferably configured as described in claim 7. That is, in the multilayer circuit board, the fibrous molecules constituting the resin film are arranged in the film plane of the resin film so that the major axis directions of the fibrous molecules are substantially parallel to each other, and the fibers When the direction of the resin film obtained by averaging the major axis directions of the molecular molecules is MD and the direction of the resin film perpendicular to the MD is TD, the resin film has a linear expansion coefficient between the MD and the TD or It is an anisotropic film having a difference in strength, and is arranged so that the MD of the resin film is in the substrate thickness direction and the resin film is in contact with the side surface of the chip component in the substrate thickness direction. Thus, the resin film is used as the intermediate insulating material.

熱可塑性樹脂からなる複数枚の樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる上記多層回路基板において、絶縁基材を構成する樹脂フィルムは、通常、ローラ等を用いたシート成形機で製造されたシート素材から切り出されて使用される。また、熱可塑性樹脂の微細組織は、一般的に、該熱可塑性樹脂の構成成分である繊維状分子の集合体となっている。このことから、上記シート素材では、繊維状分子がシート成形機におけるシート素材の流れる方向に長軸方向を略平行にして並んで配列するようになり、シート成形機においてシート素材の流れる方向(MD、Machine Direction)とシート素材の幅方向(TD、Traverse Direction)とで、上記繊維状分子の配向性を反映した異方性のあるシート素材となる。従って、該シート素材に対して任意の方向で切り出された多層回路基板の構成要素の樹脂フィルムにおいても、該樹脂フィルムのフィルム面内で、繊維状分子が長軸方向を略平行にして並んで配列しており、繊維状分子の長軸方向を平均した該樹脂フィルムの方向を上記MDとし、MDに垂直な該樹脂フィルムの方向を上記TDとして、該樹脂フィルムが一般的にMDとTDとで線膨張率や強度に方向差がある異方性フィルムとなる。尚、言うまでもなく、樹脂フィルム(シート素材)の厚さ方向ZDについても、線膨張率や強度は、MDおよびTDと異なる値となっている。該樹脂フィルムのMDとZDの線膨張率の実測例では、MDの線膨張率が約18ppmであったのに対し、ZDの線膨張率は約200ppmであった。また、該樹脂フィルムのMDとZDの引っ張り強度の実測例では、MDの引っ張り強度が約140MPaであったのに対し、ZDの引っ張り強度は20〜35MPaであった。   A resin film constituting an insulating substrate in the multilayer circuit board in which a plurality of resin films made of thermoplastic resin are bonded to each other to form an insulating substrate, and chip parts are embedded in the insulating substrate. Is usually cut out from a sheet material manufactured by a sheet forming machine using a roller or the like. In addition, the microstructure of the thermoplastic resin is generally an aggregate of fibrous molecules that are constituent components of the thermoplastic resin. Therefore, in the sheet material, the fibrous molecules are arranged side by side with the major axis direction being substantially parallel to the flow direction of the sheet material in the sheet forming machine, and the sheet material flowing direction (MD , Machine Direction) and the width direction (TD, Traverse Direction) of the sheet material, the sheet material has anisotropy reflecting the orientation of the fibrous molecules. Therefore, even in the resin film of the component of the multilayer circuit board cut out in an arbitrary direction with respect to the sheet material, the fibrous molecules are aligned with the major axis direction being substantially parallel within the film surface of the resin film. The direction of the resin film averaged in the long axis direction of the fibrous molecules is MD, the direction of the resin film perpendicular to MD is the TD, and the resin film is generally MD and TD. Thus, an anisotropic film having a direction difference in linear expansion coefficient and strength is obtained. Needless to say, the linear expansion coefficient and strength are different from those in MD and TD in the thickness direction ZD of the resin film (sheet material). In the measurement example of the linear expansion coefficient of MD and ZD of the resin film, the linear expansion coefficient of MD was about 18 ppm, whereas the linear expansion coefficient of ZD was about 200 ppm. Moreover, in the measurement example of the tensile strength of MD and ZD of the resin film, the tensile strength of MD was about 140 MPa, whereas the tensile strength of ZD was 20 to 35 MPa.

上記請求項7に記載の構成の多層回路基板においては、同じシート素材から絶縁基材を構成する樹脂フィルムと中間絶縁材として利用する樹脂フィルムを切り出すことができ、同じ材料であるため、熱可塑性樹脂からなる該樹脂フィルムを加熱加圧して相互に接着する場合にも、均質な接合部を形成することができる。また、中間絶縁材として上記方位関係を持たせて該樹脂フィルムを配置することで、前述した熱膨張差の緩和による応力低減効果を持たせることが可能である。さらには、中間絶縁材として上記方位関係を持たせた該樹脂フィルムの配置は、上記熱膨張差によって発生する応力を引っ張り強度の高いMDで受ける配置ともなっている。   In the multilayer circuit board having the structure according to claim 7, the resin film constituting the insulating base material and the resin film used as the intermediate insulating material can be cut out from the same sheet material, and are the same material. Even when the resin films made of resin are heated and pressed to be bonded to each other, a uniform joint can be formed. Moreover, it is possible to give the stress reduction effect by relaxation of the thermal expansion difference mentioned above by arrange | positioning this resin film with the said orientation relationship as an intermediate | middle insulating material. Furthermore, the arrangement of the resin film having the azimuth relationship as an intermediate insulating material is an arrangement in which the stress generated by the difference in thermal expansion is received by an MD having high tensile strength.

以上のようにして、上記多層回路基板は、いずれも、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板であって、チップ部品の周りの絶縁基材に亀裂が発生し難い多層回路基板とすることができる。   As described above, each of the multilayer circuit boards is a multilayer circuit in which resin films made of thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material. It is a board | substrate, Comprising: It can be set as the multilayer circuit board which a crack does not generate | occur | produce easily in the insulation base material around a chip component.

請求項8〜11に記載の発明は、上記多層回路基板の製造方法に関する。   The invention described in claims 8 to 11 relates to a method of manufacturing the multilayer circuit board.

請求項8に記載の発明は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板において、基板厚さ方向における熱膨張率が前記絶縁基材の熱膨張率と前記チップ部品の熱膨張率の中間にある中間絶縁材が、チップ部品の基板厚さ方向における側面に当接するようにして配置されてなる多層回路基板の製造方法であって、前記チップ部品と前記中間絶縁材を挿入するための貫通孔が形成された前記樹脂フィルムを準備する樹脂フィルム準備工程と、前記樹脂フィルムを複数枚積層する樹脂フィルム積層工程と、前記貫通孔内に前記チップ部品と前記中間絶縁材を挿入配置するチップ部品配置工程と、前記積層した樹脂フィルムの積層体を両面から加圧しつつ加熱して、各樹脂フィルムを相互に接着して前記絶縁基材を形成すると共に、前記貫通孔内に挿入配置した前記チップ部品と前記中間絶縁材を前記絶縁基材中に埋め込む加熱加圧工程とを有してなることを特徴としている。   The invention according to claim 8 is a multilayer circuit board in which resin films made of thermoplastic resin are bonded to each other to form an insulating base material, and chip parts are embedded in the insulating base material. An intermediate insulating material whose thermal expansion coefficient in the direction is intermediate between the thermal expansion coefficient of the insulating base material and the thermal expansion coefficient of the chip component is arranged so as to contact the side surface of the chip component in the substrate thickness direction. A method for manufacturing a multilayer circuit board, comprising: a resin film preparation step for preparing the resin film in which a through hole for inserting the chip component and the intermediate insulating material is formed; and a resin for laminating a plurality of the resin films A film laminating step, a chip component arranging step of inserting and arranging the chip component and the intermediate insulating material in the through hole, and pressing the laminated body of the laminated resin films from both sides Heating and pressurizing step of embedding the chip part inserted in the through hole and the intermediate insulating material in the insulating base material while heating and bonding the resin films to each other to form the insulating base material It is characterized by having.

これによって、上記請求項1に記載の多層回路基板を安価に製造することができる。尚、これによって製造される多層回路基板の効果については上述したとおりであり、その説明は省略する。   Thus, the multilayer circuit board according to the first aspect can be manufactured at low cost. The effect of the multilayer circuit board manufactured by this is as described above, and the description thereof is omitted.

特に請求項9に記載の製造方法によって請求項7に記載の多層回路基板を製造する場合には、例えば請求項10に記載のように、前記チップ部品配置工程において、前記中間絶縁材を前記貫通孔内に挿入配置するにあたって、前記貫通孔の上方または下方に配置された前記樹脂フィルムの一部を該貫通孔内に折り曲げるようにして挿入配置することで製造することができる。また、請求項11に記載のように、前記チップ部品配置工程において、前記中間絶縁材を前記貫通孔内に挿入配置するにあたって、前記樹脂フィルムのMDが前記チップ部品の基板厚さ方向となるように、該樹脂フィルムを前記チップ部品の側面に巻きつけた状態で、前記貫通孔内に挿入配置するようにしてもよい。   In particular, when the multilayer circuit board according to claim 7 is manufactured by the manufacturing method according to claim 9, for example, according to claim 10, in the chip component arranging step, the intermediate insulating material is passed through the through-hole. In inserting and arranging in the hole, it can be manufactured by inserting and arranging a part of the resin film arranged above or below the through hole so as to be bent into the through hole. Further, according to the eleventh aspect, in the chip component arranging step, when the intermediate insulating material is inserted and arranged in the through hole, the MD of the resin film is in the substrate thickness direction of the chip component. In addition, the resin film may be inserted and disposed in the through hole in a state where the resin film is wound around the side surface of the chip component.

以下、本発明を実施するための最良の形態を、図に基づいて説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

図1(a),(b)は、それぞれ、本発明に係る多層回路基板の例を示した図で、多層回路基板100,101におけるチップ部品3の周りを拡大して示した模式的な部分断面斜視図である。図1(a),(b)における一点鎖線X−X,Y−Y,Z−Zは、チップ部品3の対称軸であり、図1(a),(b)は、多層回路基板100,101におけるチップ部品3の周りを断面XY,断面YZ,断面ZXで分割して示した1/8の図となっている。   FIGS. 1A and 1B are diagrams showing examples of multilayer circuit boards according to the present invention, respectively, and are schematic portions showing the periphery of the chip component 3 in the multilayer circuit boards 100 and 101 in an enlarged manner. It is a cross-sectional perspective view. Dotted lines XX, YY, and ZZ in FIGS. 1A and 1B are axes of symmetry of the chip component 3, and FIGS. 1A and 1B show the multilayer circuit board 100, The figure shows a 1/8 view in which the periphery of the chip component 3 in 101 is divided into a cross section XY, a cross section YZ, and a cross section ZX.

また、図2は、図1(a)の多層回路基板100について、チップ部品3の周りの絶縁基材1にかかる応力をシミュレートした結果の一例である。図2(a)は、図1(a)に較べてより広範囲の領域まで含めた1/8解析モデルの斜視図であり、図2(b)は、チップ部品3の側面の周りにおいて、絶縁基材1にかかる応力のシミュレーション結果を等応力線で示した図である。   FIG. 2 is an example of a result of simulating the stress applied to the insulating base material 1 around the chip component 3 for the multilayer circuit board 100 of FIG. FIG. 2A is a perspective view of the 1/8 analysis model including a wider range than that in FIG. 1A. FIG. 2B is an insulating view around the side surface of the chip part 3. FIG. It is the figure which showed the simulation result of the stress concerning the base material 1 by the iso-stress line.

尚、図1と図2に示す多層回路基板100,101において、図10と図11に示した多層回路基板90と同様の部分については、同じ符号を付した。また、図2(a)中の破線は、絶縁基材1を構成する接着前の樹脂フィルムの境界を示している。   In the multilayer circuit boards 100 and 101 shown in FIGS. 1 and 2, the same parts as those in the multilayer circuit board 90 shown in FIGS. 10 and 11 are denoted by the same reference numerals. Moreover, the broken line in Fig.2 (a) has shown the boundary of the resin film before the adhesion which comprises the insulating base material 1. FIG.

図1(a),(b)に示す多層回路基板100,101は、いずれも、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材1が形成され、該絶縁基材1中にチップ部品3が埋め込まれてなる多層回路基板である。図1(a),(b)の多層回路基板100,101では、いずれも、チップ部品3の基板厚さ方向(Z方向)における側面に当接するようにして、中間絶縁材5a〜5cが配置されている。中間絶縁材5a〜5cは、基板厚さ方向(Z方向)における熱膨張率が絶縁基材1の熱膨張率とチップ部品3の熱膨張率の中間にある絶縁材である。図1(a),(b)の多層回路基板100,101のチップ部品3は略直方体形状であり、図1(a)の多層回路基板100では、中間絶縁材5a,5bが、チップ部品3の基板厚さ方向(Z方向)における4つの側面に当接するようにして配置されている。特に、図1(b)の多層回路基板101では、中間絶縁材5cが、チップ部品3の基板厚さ方向における4つの側面を取り囲むようにして配置されている。   The multilayer circuit boards 100 and 101 shown in FIGS. 1A and 1B are both formed by bonding resin films made of a thermoplastic resin to form an insulating base material 1. This is a multilayer circuit board in which the chip component 3 is embedded. In the multilayer circuit boards 100 and 101 of FIGS. 1A and 1B, the intermediate insulating materials 5a to 5c are arranged so as to be in contact with the side surfaces of the chip component 3 in the substrate thickness direction (Z direction). Has been. The intermediate insulating materials 5 a to 5 c are insulating materials having a thermal expansion coefficient in the substrate thickness direction (Z direction) between the thermal expansion coefficient of the insulating base material 1 and the thermal expansion coefficient of the chip component 3. The chip parts 3 of the multilayer circuit boards 100 and 101 in FIGS. 1A and 1B have a substantially rectangular parallelepiped shape. In the multilayer circuit board 100 in FIG. 1A, the intermediate insulating materials 5 a and 5 b are the chip parts 3. Are arranged so as to contact four side surfaces in the substrate thickness direction (Z direction). In particular, in the multilayer circuit board 101 of FIG. 1B, the intermediate insulating material 5c is arranged so as to surround four side surfaces of the chip component 3 in the board thickness direction.

図10と図11に示したように、熱可塑性樹脂からなる複数枚の樹脂フィルムが相互に接着されて絶縁基材1が形成され、該絶縁基材1中にチップ部品3が埋め込まれてなる従来の多層回路基板90においては、複数枚の樹脂フィルムからなる絶縁基材1とチップ部品3とが、直接当接した構造となっている。該構造の従来の多層回路基板90についてシミュレーションを行ったところ、図11に示したように、絶縁基材1におけるチップ部品3の厚さ方向の中央部付近に当接した部分が応力集中部となり、25〜30MPa程度の応力が発生していた。このため、実際に製造した従来の多層回路基板90においても、特に30MPa程度の最大応力がかかるチップ部品の長辺側の絶縁基材1においては、経時変化等で亀裂が発生し易い状態にあった。   As shown in FIGS. 10 and 11, a plurality of resin films made of thermoplastic resin are bonded to each other to form an insulating base material 1, and a chip component 3 is embedded in the insulating base material 1. The conventional multilayer circuit board 90 has a structure in which the insulating base 1 made of a plurality of resin films and the chip component 3 are in direct contact with each other. When a simulation was performed on the conventional multilayer circuit board 90 having this structure, as shown in FIG. 11, the portion of the insulating base material 1 that was in contact with the vicinity of the central portion in the thickness direction of the chip component 3 became a stress concentration portion. A stress of about 25 to 30 MPa was generated. For this reason, even in the conventional multilayer circuit board 90 actually manufactured, the insulating base material 1 on the long side of the chip component to which the maximum stress of about 30 MPa is applied is likely to be cracked due to changes over time. It was.

そこで、多層回路基板90の図11に示す応力を分析した結果、以下の要因で上記応力が発生しているという結論に至った。すなわち、抵抗やコンデンサ等のチップ部品3は、一般的に厚みが0.1mm以上あることが多く、またセラミック系の材料で構成されていることが多いため、線膨張率が10ppm以下と低い傾向がある。これに対して、多層回路基板90の熱可塑性樹脂からなる複数枚の樹脂フィルムが相互に接着された絶縁基材1は、基板面内の線膨張率を銅からなる導体パターン2の線膨張率である17ppmと同程度に合わせているが、厚さ方向の線膨張率は、一般的に基板面内の線膨張率の数倍から数十倍ある場合が多い。このため、多層回路基板90におけるチップ部品3と絶縁基材1の厚さ方向の線膨張率差で、絶縁基材1におけるチップ部品3の厚さ方向の中央部付近に当接した部分が応力集中部となり、25〜30MPa程度の応力が発生していることが判明した。   Therefore, as a result of analyzing the stress shown in FIG. 11 of the multilayer circuit board 90, it was concluded that the stress is generated due to the following factors. That is, the chip component 3 such as a resistor or a capacitor generally has a thickness of 0.1 mm or more in general and is often made of a ceramic material, so that the linear expansion coefficient tends to be as low as 10 ppm or less. There is. On the other hand, in the insulating base material 1 in which a plurality of resin films made of thermoplastic resin of the multilayer circuit board 90 are bonded to each other, the linear expansion coefficient in the substrate surface is the linear expansion coefficient of the conductor pattern 2 made of copper. The linear expansion coefficient in the thickness direction is generally several times to several tens of times the linear expansion coefficient in the substrate surface. For this reason, the portion of the insulating base material 1 that is in contact with the vicinity of the central portion in the thickness direction of the chip component 3 due to the difference in linear expansion coefficient between the chip component 3 and the insulating base material 1 in the multilayer circuit board 90 is stressed. It became a concentrated part, and it was found that a stress of about 25 to 30 MPa was generated.

このため、図1(a),(b)に示す多層回路基板100,101においては、基板厚さ方向(Z方向)における熱膨張率が絶縁基材1の熱膨張率とチップ部品3の熱膨張率の中間にある中間絶縁材5a〜5cを、チップ部品3の基板厚さ方向(Z方向)における側面に当接するようにして配置している。これによって、チップ部品3と絶縁基材1の厚さ方向の線膨張率差を該中間絶縁材5a〜5cで緩和して、チップ部品3の周りの絶縁基材1にかかる応力を低減することができる。図2の多層回路基板100で例示したように、シミュレーションによれば、例えば上記線膨張率が10ppmのチップ部品3に対して、線膨張率が17ppm〜20ppmの中間絶縁材5a,5bを絶縁基材1との間に介在させることで、チップ部品3の周りの絶縁基材1にかかる応力を13〜16MPa程度まで低減することができる。このため、実際に製造する該多層回路基板100においても、経時変化等で亀裂が発生し難く、該多層回路基板100は、高い信頼性を有した多層回路基板となっている。   For this reason, in the multilayer circuit boards 100 and 101 shown in FIGS. 1A and 1B, the thermal expansion coefficient in the board thickness direction (Z direction) is the thermal expansion coefficient of the insulating base material 1 and the heat of the chip component 3. The intermediate insulating materials 5 a to 5 c that are in the middle of the expansion rate are arranged so as to contact the side surface of the chip component 3 in the substrate thickness direction (Z direction). Accordingly, the difference in linear expansion coefficient between the chip component 3 and the insulating base material 1 in the thickness direction is relaxed by the intermediate insulating materials 5a to 5c, and the stress applied to the insulating base material 1 around the chip component 3 is reduced. Can do. As exemplified in the multilayer circuit board 100 of FIG. 2, according to the simulation, for example, the intermediate insulating materials 5a and 5b having a linear expansion coefficient of 17 ppm to 20 ppm are insulated from the chip component 3 having the linear expansion coefficient of 10 ppm. By interposing it with the material 1, the stress applied to the insulating base 1 around the chip component 3 can be reduced to about 13 to 16 MPa. For this reason, even in the multilayer circuit board 100 that is actually manufactured, cracks are unlikely to occur due to changes over time, and the multilayer circuit board 100 is a highly reliable multilayer circuit board.

以上のようにして、図1(a),(b)に示す多層回路基板100,101は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材1が形成され、該絶縁基材1中にチップ部品3が埋め込まれてなる多層回路基板であって、チップ部品3の周りの絶縁基材1に亀裂が発生し難い多層回路基板とすることができる。   As described above, in the multilayer circuit boards 100 and 101 shown in FIGS. 1A and 1B, the insulating base material 1 is formed by bonding the resin films made of thermoplastic resin to each other. 1 is a multilayer circuit board in which the chip component 3 is embedded, and the insulating substrate 1 around the chip component 3 is less likely to crack.

尚、図1(a),(b)の多層回路基板100,101では、中間絶縁材5a,5bが略直方体形状のチップ部品3における4つの側面に当接するように、あるいは中間絶縁材5cがチップ部品3の4つの側面を取り囲むようにして配置されていた。これによって、チップ部品3の周りの絶縁基材1にかかる応力を、4つの側面の周りで均等に低減することができる。しかしながらこれに限らず、例えば中間絶縁材をチップ部品3の対向する長辺側の2つの側面だけに配置するようにしてもよい。また、略直方体形状のチップ部品3に限らず、例えば円筒形状のチップ部品についても、基板厚さ方向における側面に当接するようにして中間絶縁材を配置しても、同様の応力低減効果を得ることができる。   In the multilayer circuit boards 100 and 101 of FIGS. 1A and 1B, the intermediate insulating materials 5a and 5b are in contact with four side surfaces of the substantially rectangular parallelepiped chip component 3, or the intermediate insulating material 5c is The chip parts 3 are arranged so as to surround the four side surfaces. As a result, the stress applied to the insulating substrate 1 around the chip component 3 can be evenly reduced around the four side surfaces. However, the present invention is not limited to this. For example, the intermediate insulating material may be disposed only on the two long side surfaces of the chip component 3 facing each other. Further, not only the substantially rectangular chip part 3 but also a cylindrical chip part, for example, even if an intermediate insulating material is disposed so as to contact the side surface in the substrate thickness direction, a similar stress reduction effect is obtained. be able to.

また、図1(a),(b)の多層回路基板100,101では、中間絶縁材5a〜5cが、チップ部品3の側面の全領域に当接するようにして配置されていた。しかしながら、中間絶縁材は、必ずしもチップ部品3の側面の全領域に当接する必要はない。   Further, in the multilayer circuit boards 100 and 101 of FIGS. 1A and 1B, the intermediate insulating materials 5 a to 5 c are arranged so as to be in contact with the entire region of the side surface of the chip component 3. However, the intermediate insulating material does not necessarily have to contact the entire area of the side surface of the chip component 3.

図3は、別の多層回路基板の例を示した図で、多層回路基板102におけるチップ部品3の周りを拡大して示した模式的な部分断面斜視図である。図3も、図1(a),(b)と同様に、多層回路基板102におけるチップ部品3の周りを断面XY,断面YZ,断面ZXで分割して示した1/8の図となっている。   FIG. 3 is a diagram showing an example of another multilayer circuit board, and is a schematic partial cross-sectional perspective view showing the periphery of the chip component 3 in the multilayer circuit board 102 in an enlarged manner. FIG. 3 is also a 1/8 diagram in which the periphery of the chip component 3 in the multilayer circuit board 102 is divided into a cross section XY, a cross section YZ, and a cross section ZX, as in FIGS. Yes.

図3の多層回路基板102においては、中間絶縁材5dが、チップ部品3の側面における厚さ方向(Z方向)の中央部(断面XY)を含んだ1/3以上の厚さ領域に当接するようにして配置されている。言い換えれば、図3中に示したように、チップ部品3の高さ(厚さ)をhとし、中間絶縁材5dの高さをdとしたとき、中間絶縁材5dが、チップ部品3の中央部(断面XY)を含んでd≧h/3となるように配置されている。例えば、チップ部品3の高さhが300μmであれば、高さdが100μm以上の中間絶縁材5dを、チップ部品3の中央部(断面XY)を含むようにして、その側面に当接するように配置する。   In the multilayer circuit board 102 of FIG. 3, the intermediate insulating material 5 d abuts on a thickness region of 1/3 or more including the central portion (cross section XY) in the thickness direction (Z direction) on the side surface of the chip component 3. It is arranged like that. In other words, as shown in FIG. 3, when the height (thickness) of the chip component 3 is h and the height of the intermediate insulating material 5d is d, the intermediate insulating material 5d is located at the center of the chip component 3. It arrange | positions so that it may become d> = h / 3 including a part (cross section XY). For example, if the height h of the chip component 3 is 300 μm, the intermediate insulating material 5d having a height d of 100 μm or more is disposed so as to contact the side surface so as to include the central portion (cross section XY) of the chip component 3. To do.

図2(b)および図11(b)のシミュレーション結果に示したように、前述したチップ部品3と絶縁基材1の厚さ方向の線膨張率差で発生する応力は、チップ部品3の厚さ方向の中央部(断面XY)付近が応力集中部となる。このため、シミュレーションによれば、図3に示す多層回路基板102のように、中間絶縁材5dをチップ部品3の側面における厚さ方向の中央部を含んだ1/3以上の厚さ領域に当接するようにして配置するだけでも顕著な応力低減効果が得られる。   As shown in the simulation results of FIG. 2B and FIG. 11B, the stress generated by the difference in linear expansion coefficient between the chip component 3 and the insulating base 1 in the thickness direction is the thickness of the chip component 3. The vicinity of the central portion (cross section XY) in the vertical direction is a stress concentration portion. Therefore, according to the simulation, as shown in the multilayer circuit board 102 shown in FIG. 3, the intermediate insulating material 5d is applied to a thickness region of 1/3 or more including the central portion in the thickness direction on the side surface of the chip component 3. Even if it arrange | positions so that it may contact, the remarkable stress reduction effect is acquired.

また、上記多層回路基板においては、基板面内における中間絶縁材の幅は、チップ部品の厚さの1/10以上であることが好ましい。すなわち、図3の多層回路基板102で例示したように、中間絶縁材5dの幅tは、チップ部品3の高さhに対して、t≧h/10であること好ましい。例えば、チップ部品3の高さが300μmであれば、中間絶縁材5dの幅tを30μm以上とする。応力低減効果だけみれば上記中間絶縁材の幅tは厚いほど望ましいが、シミュレーションによれば、中間絶縁材の幅tを上記のようにチップ部品の厚さの1/10以上とすることで、顕著な応力低減効果を得ることができる。   In the multilayer circuit board, the width of the intermediate insulating material in the substrate surface is preferably 1/10 or more of the thickness of the chip component. That is, as exemplified in the multilayer circuit board 102 of FIG. 3, the width t of the intermediate insulating material 5 d is preferably t ≧ h / 10 with respect to the height h of the chip component 3. For example, if the height of the chip part 3 is 300 μm, the width t of the intermediate insulating material 5d is set to 30 μm or more. From the viewpoint of the stress reduction effect, it is desirable that the width t of the intermediate insulating material is thicker. However, according to the simulation, by setting the width t of the intermediate insulating material to 1/10 or more of the thickness of the chip component as described above, A remarkable stress reduction effect can be obtained.

図4も、別の多層回路基板の例を示した図で、多層回路基板103におけるチップ部品3の周りを拡大して示した1/8の模式的な部分断面斜視図である。尚、図1と図3の多層回路基板100〜102では、絶縁基材1を構成する接着前の樹脂フィルムを明示していなかったが、図4の多層回路基板103では、絶縁基材1を構成する接着前の樹脂フィルム1a〜1dを明示し、その境界を破線で示している。   FIG. 4 is also a diagram showing an example of another multilayer circuit board, and is a schematic partial cross-sectional perspective view of 1/8 showing the periphery of the chip component 3 in the multilayer circuit board 103 in an enlarged manner. In FIG. 1 and FIG. 3, the multilayer circuit boards 100 to 102 did not clearly show the resin film before bonding that constitutes the insulating base 1, but in the multilayer circuit board 103 of FIG. The resin films 1a to 1d before bonding to be configured are clearly shown, and boundaries thereof are indicated by broken lines.

図4に示す多層回路基板103は、チップ部品3の側面に当接して配置され、基板厚さ方向において絶縁基材1とチップ部品3の中間の熱膨張率を有している中間絶縁材5e,5fとして、絶縁基材1を構成している樹脂フィルム1a〜1dと同じ樹脂フィルムを用いるものである。   The multilayer circuit board 103 shown in FIG. 4 is disposed in contact with the side surface of the chip component 3, and has an intermediate insulating material 5e having a thermal expansion coefficient intermediate between the insulating base material 1 and the chip component 3 in the substrate thickness direction. , 5f, the same resin film as the resin films 1a to 1d constituting the insulating base material 1 is used.

最初に、図4に示す多層回路基板103の構成要素である樹脂フィルム1a〜1dについて、図5と図6を用いて、詳しく説明しておく。   First, resin films 1a to 1d, which are constituent elements of the multilayer circuit board 103 shown in FIG. 4, will be described in detail with reference to FIGS.

図5は、樹脂フィルム1a〜1dの切り出し材料であるシート素材10を示す図で、図5(a)は、ロール状の先端が引き出されたシート素材10の外観を示す図であり、図5(b)は、シート素材10の微細構造を模式的に示した斜視図である。   FIG. 5 is a view showing a sheet material 10 that is a cut material of the resin films 1a to 1d, and FIG. 5 (a) is a view showing an appearance of the sheet material 10 from which a roll-shaped tip is drawn. FIG. 2B is a perspective view schematically showing the fine structure of the sheet material 10.

また、図6(a)は、シート素材10からの樹脂フィルム1a〜1dの切り出し状態の一例を示した図であり、図6(b)は、樹脂フィルム1aの断面における繊維状分子FMの配向性を示した展開図である。尚、図6において符号H3で示した部分は、図4に示したチップ部品3と中間絶縁材5e,5fを挿入するための樹脂フィルム1a,1bに形成した貫通孔である。   Moreover, Fig.6 (a) is a figure which showed an example of the cut-out state of resin film 1a-1d from the sheet | seat raw material 10, and FIG.6 (b) is orientation of the fibrous molecule FM in the cross section of the resin film 1a. It is the expanded view which showed sex. 6 is a through hole formed in the resin films 1a and 1b for inserting the chip component 3 and the intermediate insulating materials 5e and 5f shown in FIG.

図4の多層回路基板103において絶縁基材1を構成する樹脂フィルム1a〜1dは、通常、ローラ等を用いたシート成形機で製造された図5(a)に示すシート素材10から切り出されて使用される。また、熱可塑性樹脂の微細構造は、一般的に、該熱可塑性樹脂の構成成分である繊維状分子FMの集合体となっている。このことから、上記ローラ等を用いて製造されるシート素材10では、図5(b)に示すように、繊維状分子FMがシート成形機におけるシート素材10の流れる方向に長軸方向を略平行にして並んで配列するようになる。従って、ローラ等を用いて製造されたシート素材10は、シート成形機において該シート素材10の流れる方向(MD、Machine Direction)と該シート素材10の幅方向(TD、Traverse Direction)とで、上記繊維状分子FMの配向性を反映した異方性のあるシート素材となる。従って、該シート素材10に対して任意の方向で切り出された多層回路基板の構成要素の樹脂フィルムにおいても、該樹脂フィルムのフィルム面内で、繊維状分子FMが長軸方向を略平行にして並んで配列しており、繊維状分子FMの長軸方向を平均した該樹脂フィルムの方向を上記MDとし、MDに垂直な該樹脂フィルムの方向を上記TDとして、該樹脂フィルムが一般的にMDとTDとで線膨張率や強度に方向差がある異方性フィルムとなる。尚、言うまでもなく、樹脂フィルム(シート素材)の厚さ方向ZDについても、線膨張率または強度は、MDおよびTDと異なる値となっている。   In the multilayer circuit board 103 of FIG. 4, the resin films 1a to 1d constituting the insulating base material 1 are usually cut out from the sheet material 10 shown in FIG. 5 (a) manufactured by a sheet molding machine using a roller or the like. used. Further, the microstructure of the thermoplastic resin is generally an aggregate of fibrous molecules FM that are constituent components of the thermoplastic resin. Therefore, in the sheet material 10 manufactured using the roller or the like, as shown in FIG. 5B, the long axis direction is substantially parallel to the direction in which the fibrous molecules FM flow in the sheet forming machine. Will be arranged side by side. Accordingly, the sheet material 10 manufactured using a roller or the like is the above in the sheet forming machine in the flow direction (MD, Machine Direction) and the width direction (TD, Traverse Direction) of the sheet material 10 in the sheet forming machine. It becomes an anisotropic sheet material reflecting the orientation of the fibrous molecule FM. Therefore, even in the resin film of the constituent elements of the multilayer circuit board cut out in any direction with respect to the sheet material 10, the fibrous molecules FM are arranged so that the major axis direction is substantially parallel within the film plane of the resin film. The resin film is generally arranged in a line, and the direction of the resin film, which is the average of the major axis directions of the fibrous molecules FM, is MD, and the direction of the resin film perpendicular to MD is the TD. And TD are anisotropic films having a direction difference in linear expansion coefficient and strength. Needless to say, also in the thickness direction ZD of the resin film (sheet material), the linear expansion coefficient or strength is a value different from MD and TD.

具体的に、例えば図6の樹脂フィルム1a〜1dでは、繊維状分子FMが該樹脂フィルム1a〜1dの短辺方向にその長軸方向を略平行にして並んで配列している。このように、繊維状分子FMが長軸方向を略平行にして並んで配列した樹脂フィルム1a〜1dにおいては、該樹脂フィルム1a〜1dのフィルム面内における方向として、前述したように、繊維状分子FMの長軸方向を平均したMDと、該MDに垂直な方向のTDを定義できる。また、図6(b)に示すように、樹脂フィルム1a〜1dの断面として、MDで切断され断面内に繊維状分子FMの長軸方向が含まれるMD断面と、TDで切断され断面内で繊維状分子FMの長軸方向が垂直に交わるTD断面を定義することができる。従って、図6(b)からわかるように、樹脂フィルム1a,1bに形成されたチップ部品3と中間絶縁材5e,5fの貫通孔H3では、長辺側がMD断面となり、短辺側がTD断面となる。   Specifically, for example, in the resin films 1a to 1d of FIG. 6, the fibrous molecules FM are arranged side by side with the major axis direction substantially parallel to the short side direction of the resin films 1a to 1d. As described above, in the resin films 1a to 1d in which the fibrous molecules FM are arranged so that the major axis directions thereof are substantially parallel to each other, the direction in the film plane of the resin films 1a to 1d is as described above. MD which averaged the major axis direction of molecule | numerator FM and TD of the direction perpendicular | vertical to this MD can be defined. Moreover, as shown in FIG.6 (b), as a cross section of resin film 1a-1d, the MD cross section cut | disconnected by MD and including the major axis direction of the fibrous molecule FM in a cross section, and the cross section cut | disconnected by TD A TD cross section in which the major axis directions of the fibrous molecules FM intersect perpendicularly can be defined. Therefore, as can be seen from FIG. 6B, in the chip part 3 formed in the resin films 1a and 1b and the through holes H3 of the intermediate insulating materials 5e and 5f, the long side is the MD cross section and the short side is the TD cross section. Become.

樹脂フィルム1a〜1dのMDとZDの線膨張率の実測例では、MDの線膨張率が約18ppmであったのに対し、ZDの線膨張率は約200ppmであった。尚、TDの線膨張率は約20ppmであった。また、該樹脂フィルム1a〜1dのMDとZDの引っ張り強度の実測例では、MDの引っ張り強度が約140MPaであったのに対し、ZDの引っ張り強度は20MPa(TD断面)〜35MPa(MD断面)であった。   In the measurement examples of the MD and ZD linear expansion coefficients of the resin films 1a to 1d, the linear expansion coefficient of MD was about 18 ppm, whereas the linear expansion coefficient of ZD was about 200 ppm. The linear expansion coefficient of TD was about 20 ppm. Moreover, in the measurement example of the tensile strength of MD and ZD of the resin films 1a to 1d, the tensile strength of MD was about 140 MPa, whereas the tensile strength of ZD was 20 MPa (TD cross section) to 35 MPa (MD cross section). Met.

上記樹脂フィルム1a〜1dの異方性を利用して、図4の多層回路基板103では、中間絶縁材5e,5fとして樹脂フィルム1a〜1dと同じシート素材10から切り出された樹脂フィルムを利用し、該樹脂フィルムのMDが基板厚さ方向(Z方向)となるようにして、チップ部品3の側面に当接するようにして配置している。   By utilizing the anisotropy of the resin films 1a to 1d, the multilayer circuit board 103 of FIG. 4 uses a resin film cut out from the same sheet material 10 as the resin films 1a to 1d as the intermediate insulating materials 5e and 5f. The resin film MD is arranged so as to be in contact with the side surface of the chip component 3 so that the MD of the resin film is in the substrate thickness direction (Z direction).

図7(a),(b)に、図4に示した多層回路基板103と図11に示した従来の多層回路基板90について、チップ部品3の周りにおける各樹脂フィルムの配向性の違いを、該樹脂フィルムを構成している繊維状分子FMを使って比較して示した。   7 (a) and 7 (b), the difference in the orientation of each resin film around the chip component 3 in the multilayer circuit board 103 shown in FIG. 4 and the conventional multilayer circuit board 90 shown in FIG. Comparison was made using the fibrous molecules FM constituting the resin film.

図4の多層回路基板103においては、同じシート素材10から絶縁基材1を構成する樹脂フィルム1a〜1dと中間絶縁材5e,5fとして利用する樹脂フィルムを切り出すことができ、同じ材料であるため、熱可塑性樹脂からなる該樹脂フィルムを加熱加圧して相互に接着する場合にも、均質な接合部を形成することができる。また、中間絶縁材5e,5fとして上記方位関係を持たせて該樹脂フィルムを配置することで、前述した熱膨張差の緩和による応力低減効果を持たせることが可能である。さらには、中間絶縁材5e,5fとして上記方位関係を持たせた該樹脂フィルムの配置は、上記熱膨張差によって発生する応力を引っ張り強度の高いMDで受ける配置ともなっている。   In the multilayer circuit board 103 of FIG. 4, since the resin films 1a to 1d constituting the insulating base material 1 and the resin films used as the intermediate insulating materials 5e and 5f can be cut out from the same sheet material 10, they are the same material. Even when the resin films made of a thermoplastic resin are heated and pressed to adhere to each other, a uniform joint can be formed. Further, by arranging the resin film with the above azimuth relationship as the intermediate insulating materials 5e and 5f, it is possible to have the stress reduction effect due to the relaxation of the thermal expansion difference described above. Furthermore, the arrangement of the resin film having the orientation relationship as the intermediate insulating materials 5e and 5f is an arrangement in which the stress generated by the difference in thermal expansion is received by the MD having high tensile strength.

以上のようにして、上記した多層回路基板100〜103は、いずれも、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材1が形成され、該絶縁基材1中にチップ部品3が埋め込まれてなる多層回路基板であって、チップ部品の周りの絶縁基材1に亀裂が発生し難い多層回路基板とすることができる。   As described above, in each of the multilayer circuit boards 100 to 103, the insulating base material 1 is formed by bonding the resin films made of thermoplastic resin to each other, and the chip component 3 is formed in the insulating base material 1. Is a multilayer circuit board in which cracks are unlikely to occur in the insulating base material 1 around the chip component.

次に、図4の多層回路基板103を例にして、上記多層回路基板の製造方法について説明する。図8(a),(b)は、それぞれ、製造途中にある図4の多層回路基板103の各状態を示した模式的な部分断面斜視図である。   Next, the method for manufacturing the multilayer circuit board will be described using the multilayer circuit board 103 of FIG. 4 as an example. FIGS. 8A and 8B are schematic partial cross-sectional perspective views showing states of the multilayer circuit board 103 of FIG. 4 being manufactured.

図4の多層回路基板103を製造するにあたっては、最初に、図6(a)に示したように、樹脂フィルム準備工程において、チップ部品3と中間絶縁材5e,5fを挿入するための貫通孔H3が形成された樹脂フィルム1a,1bを準備する。次に、図8(a)に示すように、樹脂フィルム積層工程において、準備した複数枚の樹脂フィルム1a,1bを積層する。次に、図8(b)に示すように、チップ部品配置工程において、貫通孔H3内にチップ部品3と中間絶縁材5e,5fを挿入配置する。次に、図8(b)の積層体に樹脂フィルム1c,1dを積層した後、最後の加熱加圧工程において、積層した樹脂フィルム1a〜1dの積層体を両面から加圧しつつ加熱して、各樹脂フィルム1a〜1dを相互に接着して絶縁基材1を形成すると共に、貫通孔H3内に挿入配置したチップ部品3と中間絶縁材5e,5fを絶縁基材1中に埋め込む。これによって、図4の多層回路基板103を製造することができる。   In manufacturing the multilayer circuit board 103 of FIG. 4, first, as shown in FIG. 6A, in the resin film preparation process, through-holes for inserting the chip component 3 and the intermediate insulating materials 5e and 5f are inserted. Resin films 1a and 1b on which H3 is formed are prepared. Next, as shown in FIG. 8A, in the resin film laminating step, a plurality of prepared resin films 1a and 1b are laminated. Next, as shown in FIG. 8B, in the chip component arranging step, the chip component 3 and the intermediate insulating materials 5e and 5f are inserted and arranged in the through hole H3. Next, after laminating the resin films 1c and 1d on the laminate of FIG. 8B, in the final heating and pressing step, the laminate of the laminated resin films 1a to 1d is heated while being pressed from both sides, The resin films 1 a to 1 d are bonded to each other to form the insulating base 1, and the chip component 3 and the intermediate insulating materials 5 e and 5 f inserted and disposed in the through hole H 3 are embedded in the insulating base 1. Thereby, the multilayer circuit board 103 of FIG. 4 can be manufactured.

上記多層回路基板の製造方法は、樹脂フィルム1a〜1d同士の接着やチップ部品3と中間絶縁材5e,5fの埋め込みを一度の加熱加圧により一括して行うことができるため、該多層回路基板を安価に製造することができる。   Since the method for manufacturing the multilayer circuit board can perform bonding of the resin films 1a to 1d and embedding of the chip component 3 and the intermediate insulating materials 5e and 5f all at once by one heating and pressurization, the multilayer circuit board Can be manufactured at low cost.

尚、上記した多層回路基板の製造方法において、中間絶縁材を所定の貫通孔内に挿入配置するにあたっては、種々の方法が可能である。例えば、図8(b)のチップ部品配置工程において、中間絶縁材となる樹脂フィルムのMDがチップ部品3の基板厚さ方向(Z方向)となるように、該樹脂フィルムをチップ部品3の側面に巻きつけた状態で、所定の貫通孔内に挿入配置するようにしてもよい。これによれば、図1(b)に示した多層回路基板101と同様の多層回路基板を製造することができる。また、例えば所定の貫通孔内にチップ部品3を挿入配置した状態で、中間絶縁材となる材料を流し込むようにして挿入配置することも可能である。   In the above-described multilayer circuit board manufacturing method, various methods can be used to insert and arrange the intermediate insulating material in the predetermined through hole. For example, in the chip component arranging step of FIG. 8B, the resin film is placed on the side surface of the chip component 3 so that the MD of the resin film serving as an intermediate insulating material is in the substrate thickness direction (Z direction) of the chip component 3. You may make it insert and arrange | position in a predetermined through-hole in the state wound around. According to this, a multilayer circuit board similar to the multilayer circuit board 101 shown in FIG. 1B can be manufactured. Further, for example, in a state where the chip component 3 is inserted and arranged in a predetermined through-hole, it is also possible to insert and arrange the material as an intermediate insulating material.

図9は、図4に示した多層回路基板103と同様の多層回路基板104について、そのの製造方法を示した図である。図9(a),(b)は、それぞれ、製造途中にある多層回路基板104の各状態を示した模式的な部分断面斜視図である。   FIG. 9 is a diagram showing a method for manufacturing a multilayer circuit board 104 similar to the multilayer circuit board 103 shown in FIG. FIGS. 9A and 9B are schematic partial cross-sectional perspective views showing states of the multilayer circuit board 104 in the middle of manufacture.

図9(a),(b)に示した多層回路基板104の製造方法では、チップ部品配置工程において、積層された樹脂フィルム1e〜1iの貫通孔H4内に中間絶縁材5g、5hを挿入配置するにあたって、貫通孔H4の上方または下方に配置された樹脂フィルム1h,1iの一部をチップ部品3で貫通孔H4内に折り曲げるようにして挿入配置している。これによって、樹脂フィルム1h,1iの折り曲げ部分のMDが基板厚さ方向(Z方向)となり、これが中間絶縁材5g、5hとして利用された多層回路基板104を製造することができる。   In the method of manufacturing the multilayer circuit board 104 shown in FIGS. 9A and 9B, the intermediate insulating materials 5g and 5h are inserted and arranged in the through holes H4 of the laminated resin films 1e to 1i in the chip component arranging step. In doing so, a part of the resin films 1h and 1i disposed above or below the through hole H4 is inserted and disposed so as to be bent by the chip component 3 into the through hole H4. As a result, the MD of the bent portions of the resin films 1h and 1i becomes the substrate thickness direction (Z direction), and the multilayer circuit board 104 used as the intermediate insulating materials 5g and 5h can be manufactured.

以上のようにして、上記多層回路基板およびその製造方法は、熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板およびその製造方法であって、チップ部品の周りの絶縁基材に亀裂が発生し難い多層回路基板およびその製造方法となっている。   As described above, the multilayer circuit board and the method for manufacturing the multilayer circuit board are multilayer films in which resin films made of thermoplastic resin are bonded to each other to form an insulating base material, and chip components are embedded in the insulating base material. A circuit board and a manufacturing method thereof are a multilayer circuit board and a manufacturing method thereof in which cracks are unlikely to occur in an insulating base material around a chip component.

(a),(b)は、それぞれ、本発明に係る多層回路基板の例を示した図で、多層回路基板100,101におけるチップ部品3の周りを拡大して示した模式的な部分断面斜視図である。(A), (b) is the figure which showed the example of the multilayer circuit board which concerns on this invention, respectively, The typical partial cross-section perspective view which expanded the periphery of the chip components 3 in the multilayer circuit boards 100 and 101, and was shown. FIG. 図1(a)の多層回路基板100について、チップ部品3の周りの絶縁基材1にかかる応力をシミュレートした結果の一例である。(a)は、図1(a)に較べてより広範囲の領域まで含めた1/8解析モデルの斜視図であり、(b)は、チップ部品3の側面の周りにおいて、絶縁基材1にかかる応力のシミュレーション結果を等応力線で示した図である。FIG. 3 is an example of a result of simulating stress applied to the insulating base material 1 around the chip component 3 for the multilayer circuit board 100 of FIG. (A) is a perspective view of a 1/8 analysis model including a wider range than that in FIG. 1 (a), and (b) is an insulating substrate 1 around the side surface of the chip component 3. It is the figure which showed the simulation result of this stress by the iso-stress line. 別の多層回路基板の例を示した図で、多層回路基板102におけるチップ部品3の周りを拡大して示した模式的な部分断面斜視図である。FIG. 10 is a diagram showing an example of another multilayer circuit board, and is a schematic partial cross-sectional perspective view showing an enlargement of the periphery of the chip component 3 in the multilayer circuit board 102. 別の多層回路基板の例を示した図で、多層回路基板103におけるチップ部品3の周りを拡大して示した1/8の模式的な部分断面斜視図である。FIG. 10 is a diagram showing another example of the multilayer circuit board, and is a schematic partial cross-sectional perspective view of 1/8 showing the periphery of the chip component 3 in the multilayer circuit board 103 in an enlarged manner. 樹脂フィルム1a〜1dの切り出し材料であるシート素材10を示す図で、(a)は、ロール状の先端が引き出されたシート素材10の外観を示す図であり、(b)は、シート素材10の微細構造を模式的に示した斜視図である。It is a figure which shows the sheet raw material 10 which is the cutting material of resin film 1a-1d, (a) is a figure which shows the external appearance of the sheet raw material 10 by which the roll-shaped front-end | tip was pulled out, (b) is a sheet raw material 10 It is the perspective view which showed typically the fine structure. (a)は、シート素材10からの樹脂フィルム1a〜1dの切り出し状態の一例を示した図であり、(b)は、樹脂フィルム1aの断面における繊維状分子FMの配向性を示した展開図である。(A) is the figure which showed an example of the cut-out state of resin film 1a-1d from the sheet | seat raw material 10, (b) is the expanded view which showed the orientation of the fibrous molecule FM in the cross section of the resin film 1a. It is. (a),(b)は、図4に示した多層回路基板103と図11に示した従来の多層回路基板90について、チップ部品3の周りにおける各樹脂フィルムの配向性の違いを、該樹脂フィルムを構成している繊維状分子FMを使って比較して示した図である。(A), (b) shows the difference in orientation of each resin film around the chip component 3 between the multilayer circuit board 103 shown in FIG. 4 and the conventional multilayer circuit board 90 shown in FIG. It is the figure shown in comparison using the fibrous molecule | numerator FM which comprises the film. (a),(b)は、それぞれ、製造途中にある図4の多層回路基板103の各状態を示した模式的な部分断面斜視図である。(A), (b) is the typical partial cross-sectional perspective view which showed each state of the multilayer circuit board 103 of FIG. 4 in the middle of manufacture, respectively. 図4に示した多層回路基板103と同様の多層回路基板104について、そのの製造方法を示した図で、(a),(b)は、それぞれ、製造途中にある多層回路基板104の各状態を示した模式的な部分断面斜視図である。FIGS. 5A and 5B are diagrams illustrating a method of manufacturing a multilayer circuit board 104 similar to the multilayer circuit board 103 illustrated in FIG. 4. FIGS. 5A and 5B are diagrams illustrating states of the multilayer circuit board 104 in the process of manufacturing. It is the typical fragmentary sectional perspective view which showed. 従来の多層回路基板の一例を示す図で、(a)は、多層回路基板90を模式的に示した上面図である。また、(b)と(c)は、それぞれ、(a)における一点鎖線A−Aと二点鎖線B−Bの断面を実物の写真で示した図である。It is a figure which shows an example of the conventional multilayer circuit board, (a) is the top view which showed the multilayer circuit board 90 typically. Moreover, (b) and (c) are the figures which respectively showed the cross section of the dashed-dotted line AA and the dashed-two dotted line BB in (a) with the photograph of the real thing. 図10の多層回路基板90について、チップ部品3の周りの絶縁基材1にかかる応力をシミュレートした結果の一例である。(a)は、1/4解析モデルの斜視図であり、(b)は、そのシミュレーション結果を等応力線で示した図である。FIG. 11 is an example of a result of simulating the stress applied to the insulating base material 1 around the chip component 3 for the multilayer circuit board 90 of FIG. 10. (A) is a perspective view of a 1/4 analysis model, (b) is the figure which showed the simulation result by the iso-stress line.

符号の説明Explanation of symbols

90,100〜104 多層回路基板
1 絶縁基材
1a〜1i 樹脂フィルム
3 チップ部品
5a〜5g 中間絶縁材
10 シート素材
FM 繊維状分子
H3,H4 貫通孔
90, 100 to 104 Multilayer circuit board 1 Insulating substrate 1a to 1i Resin film 3 Chip component 5a to 5g Intermediate insulating material 10 Sheet material FM Fibrous molecule H3, H4 Through hole

Claims (11)

熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板において、
基板厚さ方向における熱膨張率が前記絶縁基材の熱膨張率と前記チップ部品の熱膨張率の中間にある中間絶縁材が、チップ部品の基板厚さ方向における側面に当接するようにして配置されてなることを特徴とする多層回路基板。
In a multilayer circuit board in which resin films made of thermoplastic resin are bonded to each other to form an insulating base, and chip components are embedded in the insulating base,
Arranged so that an intermediate insulating material whose thermal expansion coefficient in the substrate thickness direction is intermediate between the thermal expansion coefficient of the insulating base and the thermal expansion coefficient of the chip component contacts the side surface of the chip component in the substrate thickness direction. A multilayer circuit board characterized by being made.
前記チップ部品が、略直方体形状であり、
前記中間絶縁材が、前記チップ部品の基板厚さ方向における4つの側面に当接するようにして配置されてなることを特徴とする請求項1に記載の多層回路基板。
The chip component has a substantially rectangular parallelepiped shape;
2. The multilayer circuit board according to claim 1, wherein the intermediate insulating material is disposed so as to abut on four side surfaces of the chip component in the substrate thickness direction.
前記中間絶縁材が、前記チップ部品の基板厚さ方向における4つの側面を取り囲むようにして配置されてなることを特徴とする請求項2に記載の多層回路基板。   3. The multilayer circuit board according to claim 2, wherein the intermediate insulating material is disposed so as to surround four side surfaces of the chip component in the substrate thickness direction. 前記中間絶縁材が、前記チップ部品の側面における厚さ方向の中央部を含んだ1/3以上の厚さ領域に当接するようにして配置されてなることを特徴とする請求項1乃至3のいずれかに一項に記載の多層回路基板。   4. The intermediate insulating material according to claim 1, wherein the intermediate insulating material is disposed so as to abut on a thickness region of 1/3 or more including a central portion in a thickness direction on a side surface of the chip component. The multilayer circuit board according to any one of the above. 前記中間絶縁材が、前記チップ部品の側面の全領域に当接するようにして配置されてなることを特徴とする請求項4に記載の多層回路基板。   5. The multilayer circuit board according to claim 4, wherein the intermediate insulating material is disposed so as to be in contact with an entire region of a side surface of the chip component. 基板面内における前記中間絶縁材の幅が、前記チップ部品の厚さの1/10以上であることを特徴とする請求項1乃至5のいずれかに一項に記載の多層回路基板。   6. The multilayer circuit board according to claim 1, wherein a width of the intermediate insulating material in the substrate surface is 1/10 or more of a thickness of the chip component. 7. 前記樹脂フィルムを構成している繊維状分子が、該樹脂フィルムのフィルム面内において、前記繊維状分子の長軸方向を略平行にして並んで配列し、
前記繊維状分子の長軸方向を平均した該樹脂フィルムの方向をMDとし、前記MDに垂直な該樹脂フィルムの方向をTDとしたとき、
前記樹脂フィルムが、前記MDと前記TDとで線膨張率または強度に差がある異方性フィルムであり、
前記樹脂フィルムのMDが基板厚さ方向となるようにして、前記樹脂フィルムが前記チップ部品の基板厚さ方向における側面に当接するようにして配置されてなり、
前記樹脂フィルムが、前記中間絶縁材として利用されてなることを特徴とする請求項1乃至6のいずれかに一項に記載の多層回路基板。
In the film surface of the resin film, the fibrous molecules constituting the resin film are arranged side by side with the major axis direction of the fibrous molecules being substantially parallel,
When the direction of the resin film averaged in the long axis direction of the fibrous molecule is MD, and the direction of the resin film perpendicular to the MD is TD,
The resin film is an anisotropic film having a difference in linear expansion coefficient or strength between the MD and the TD,
The resin film is arranged so that the MD of the resin film is in the substrate thickness direction, and the resin film is in contact with the side surface of the chip component in the substrate thickness direction,
The multilayer circuit board according to claim 1, wherein the resin film is used as the intermediate insulating material.
熱可塑性樹脂からなる樹脂フィルムが相互に接着されて絶縁基材が形成され、該絶縁基材中にチップ部品が埋め込まれてなる多層回路基板において、
基板厚さ方向における熱膨張率が前記絶縁基材の熱膨張率と前記チップ部品の熱膨張率の中間にある中間絶縁材が、チップ部品の基板厚さ方向における側面に当接するようにして配置されてなる多層回路基板の製造方法であって、
前記チップ部品と前記中間絶縁材を挿入するための貫通孔が形成された前記樹脂フィルムを準備する樹脂フィルム準備工程と、
前記樹脂フィルムを複数枚積層する樹脂フィルム積層工程と、
前記貫通孔内に前記チップ部品と前記中間絶縁材を挿入配置するチップ部品配置工程と、
前記積層した樹脂フィルムの積層体を両面から加圧しつつ加熱して、各樹脂フィルムを相互に接着して前記絶縁基材を形成すると共に、前記貫通孔内に挿入配置した前記チップ部品と前記中間絶縁材を前記絶縁基材中に埋め込む加熱加圧工程とを有してなることを特徴とする多層回路基板の製造方法。
In a multilayer circuit board in which resin films made of thermoplastic resin are bonded to each other to form an insulating base, and chip components are embedded in the insulating base,
Arranged so that an intermediate insulating material whose thermal expansion coefficient in the substrate thickness direction is intermediate between the thermal expansion coefficient of the insulating base and the thermal expansion coefficient of the chip component contacts the side surface of the chip component in the substrate thickness direction. A method for producing a multilayer circuit board, comprising:
A resin film preparing step of preparing the resin film in which a through hole for inserting the chip component and the intermediate insulating material is formed;
A resin film laminating step for laminating a plurality of the resin films;
A chip component arranging step of inserting and arranging the chip component and the intermediate insulating material in the through hole;
The laminated body of the laminated resin films is heated while being pressurized from both sides, and the resin films are bonded to each other to form the insulating base material, and the chip component inserted and disposed in the through hole and the intermediate A method of manufacturing a multilayer circuit board, comprising: a heating and pressing step of embedding an insulating material in the insulating base material.
前記樹脂フィルムを構成している繊維状分子が、該樹脂フィルムのフィルム面内において、前記繊維状分子の長軸方向を略平行にして並んで配列し、
前記繊維状分子の長軸方向を平均した該樹脂フィルムの方向をMDとし、前記MDに垂直な該樹脂フィルムの方向をTDとしたとき、
前記樹脂フィルムが、前記MDと前記TDとで線膨張率または強度に差がある異方性フィルムであり、
前記多層回路基板が、
前記樹脂フィルムのMDが基板厚さ方向となるようにして、前記樹脂フィルムが前記チップ部品の基板厚さ方向における側面に当接するようにして配置されてなり、
前記樹脂フィルムが、前記中間絶縁材として利用されてなる多層回路基板であることを特徴とする請求項8に記載の多層回路基板の製造方法。
In the film surface of the resin film, the fibrous molecules constituting the resin film are arranged side by side with the major axis direction of the fibrous molecules being substantially parallel,
When the direction of the resin film averaged in the long axis direction of the fibrous molecule is MD, and the direction of the resin film perpendicular to the MD is TD,
The resin film is an anisotropic film having a difference in linear expansion coefficient or strength between the MD and the TD,
The multilayer circuit board comprises:
The resin film is arranged so that the MD of the resin film is in the substrate thickness direction, and the resin film is in contact with the side surface of the chip component in the substrate thickness direction,
The method for producing a multilayer circuit board according to claim 8, wherein the resin film is a multilayer circuit board used as the intermediate insulating material.
前記チップ部品配置工程において、前記中間絶縁材を前記貫通孔内に挿入配置するにあたって、
前記貫通孔の上方または下方に配置された前記樹脂フィルムの一部を該貫通孔内に折り曲げるようにして挿入配置することを特徴とする請求項9に記載の多層回路基板の製造方法。
In the chip component placement step, in placing the intermediate insulating material in the through hole,
10. The method for manufacturing a multilayer circuit board according to claim 9, wherein a part of the resin film disposed above or below the through hole is inserted and disposed so as to be bent into the through hole.
前記チップ部品配置工程において、前記中間絶縁材を前記貫通孔内に挿入配置するにあたって、
前記樹脂フィルムのMDが前記チップ部品の基板厚さ方向となるように、該樹脂フィルムを前記チップ部品の側面に巻きつけた状態で、前記貫通孔内に挿入配置することを特徴とする請求項9に記載の多層回路基板の製造方法。
In the chip component placement step, in placing the intermediate insulating material in the through hole,
The resin film is inserted and disposed in the through hole in a state where the resin film is wound around a side surface of the chip component so that the MD of the resin film is in the substrate thickness direction of the chip component. A method for producing a multilayer circuit board according to claim 9.
JP2008061740A 2008-03-11 2008-03-11 Multilayer circuit board, and method for manufacturing the same Pending JP2009218441A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012137626A1 (en) * 2011-04-01 2012-10-11 株式会社村田製作所 Resin substrate having built-in component and method for producing same
JP2013179144A (en) * 2012-02-28 2013-09-09 Murata Mfg Co Ltd Component built-in resin multilayer substrate and manufacturing method therefor
CN105828529A (en) * 2015-01-22 2016-08-03 三星电机株式会社 Printed circuit board and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012137626A1 (en) * 2011-04-01 2012-10-11 株式会社村田製作所 Resin substrate having built-in component and method for producing same
US10555421B2 (en) 2011-04-01 2020-02-04 Murata Manufacturing Co., Ltd. Component-embedded resin substrate and method for manufacturing same
JP2013179144A (en) * 2012-02-28 2013-09-09 Murata Mfg Co Ltd Component built-in resin multilayer substrate and manufacturing method therefor
CN105828529A (en) * 2015-01-22 2016-08-03 三星电机株式会社 Printed circuit board and method of manufacturing the same
US10448512B2 (en) 2015-01-22 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

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