JP2009217566A - Control method for overvoltage suppression by reversed phase control - Google Patents

Control method for overvoltage suppression by reversed phase control Download PDF

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JP2009217566A
JP2009217566A JP2008060874A JP2008060874A JP2009217566A JP 2009217566 A JP2009217566 A JP 2009217566A JP 2008060874 A JP2008060874 A JP 2008060874A JP 2008060874 A JP2008060874 A JP 2008060874A JP 2009217566 A JP2009217566 A JP 2009217566A
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value
deviation
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JP5121514B2 (en
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Koji Tenma
耕司 天満
Takaaki Shimonosono
隆明 下之園
Tadayuki Wada
忠幸 和田
Takehiko Aketani
武彦 明谷
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Chubu Electric Power Co Inc
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To enable a power conversion device to resume operation at high speed while performing overvoltage suppression and suppressing overcurrent in resuming operation in a voltage unbalance status of a power system. <P>SOLUTION: Voltage amplitude of a phase to become overvoltage is suppressed, and overcurrent is suppressed by: providing an overcurrent suppression dead zone implement 115 which has first operation thresholds Vth1 and Φth1 and an overvoltage suppression dead zone implement 116 which has second operation thresholds Vth2 and Φth2 to make Vth1>Vth2; correcting voltage instruction value Va*-Vc* of a power inverter circuit 1, when either of an amplitude deviation ΔVa-ΔVc or phase deviation ΦVa-ΦVc exceeds Vth1 or Vth2; and controlling the power inverter circuit 1 by a signal of a pulse width modulator 107 which inputs this corrected value. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は、交流電力系統の電圧が、事故発生時あるいは平常時に不平衡となり系統過電圧が発生した場合、その系統過電圧を抑制する逆相制御による過電圧抑制制御方式に関するものである。   The present invention relates to an overvoltage suppression control method by reverse phase control that suppresses system overvoltage when the voltage of an AC power system is unbalanced at the time of occurrence of an accident or during normal times and a system overvoltage is generated.

電力系統に接続されて、交流電力と直流電力を双方向に変換し、直流側の電圧をパルス幅変調する電力変換装置は、電力系統の有効電力、無効電力を制御することができ、電力系統の電力融通や電圧の安定化、変動補償に利用されている。
従来の電力変換装置として、系統事故が発生すると電力変換器の可制御素子を停止状態とし、系統電流を停止させるに必要な最小限の時間だけ停止状態を継続し、その状態で装置内の電力変換器の可制御素子を動作させて電流の通電を可能な状態にする技術が示されている(例えば、特許文献1)。
また他の電力変換器の制御装置では、非特許文献1である、例えば文献Y.Jiang,Å.Ekstrom,”Applying PWM to Control Overcurrents at Unbalanced Faults of Forced-Commutated VSCs Used as Static Var Compensators”,IEEE Transactions on Power Delivery,Vol.12,No.1,pp.273-278,January 1997に開示されているように、多相交流電圧を正相成分と逆相成分に分解した後、電力変換器の各相電圧出力指令の大きさと位相を演算して電力変換器を制御するようにしている(図6)。そして、正相成分と逆相成分の分離には、多相交流電圧を直交2相交流電圧に変換し、その1/4周期遅れ信号とから演算するように構成されている(図2)。
A power converter connected to the power system to convert AC power and DC power bidirectionally and to pulse width modulate the DC voltage can control the active power and reactive power of the power system. It is used for power interchange, voltage stabilization, and fluctuation compensation.
As a conventional power conversion device, when a grid fault occurs, the controllable element of the power converter is stopped, and the stop state is continued for the minimum time necessary to stop the system current. A technique is disclosed in which a controllable element of a converter is operated so that current can be passed (for example, Patent Document 1).
In another power converter control device, Non-Patent Document 1, for example, Document Y. Jiang, Å. Ekstrom, “Applying PWM to Control Overcurrents at Unbalanced Faults of Forced-Commutated VSCs Used as Static Var Compensators”, IEEE Transactions on Power Delivery, Vol. 12, no. 1, pp. As disclosed in 273-278, January 1997, the multiphase AC voltage is decomposed into a positive phase component and a negative phase component, and then the magnitude and phase of each phase voltage output command of the power converter is calculated to convert the power. The device is controlled (FIG. 6). In order to separate the positive phase component and the negative phase component, the multiphase AC voltage is converted into a quadrature two-phase AC voltage and is calculated from the 1/4 cycle delay signal (FIG. 2).

特開平06−175741号公報(図1、図2)Japanese Patent Laid-Open No. 06-175741 (FIGS. 1 and 2) IEEE Transactions on Power Delivery,Vol.12,No.1,pp. 273-278,January 1997IEEE Transactions on Power Delivery, Vol. 12, no. 1, pp. 273-278, January 1997

特許文献1に開示された従来の電力変換装置にあっては、電力系統の電流を再度通電可能な状態にするとき、電力系統の事故が継続し、電力変換装置は電力系統の多相交流電圧が不平衡となっている状態の場合がある。このため、その状態で可制御素子を動作させ電力変換装置の運転を再開しても、電力系統に対する過電圧抑制効果はないという問題点がある。
また非特許文献1に示された電力変換器の制御装置では、多相交流電圧を正相分と逆相分に分離するために、少なくとも1/4周期の遅れが発生し、1/4周期以下では電力系統の電圧を正しく得ることができず、過渡的な逆相電圧の発生に対して逆相電圧を抑制できないという問題点がある。
In the conventional power conversion device disclosed in Patent Document 1, when the current of the power system is re-energized, the power system accident continues, and the power conversion device is a multiphase AC voltage of the power system. May be in an unbalanced state. For this reason, there is a problem that even if the controllable element is operated in this state and the operation of the power converter is restarted, there is no overvoltage suppression effect on the power system.
Further, in the control device for the power converter shown in Non-Patent Document 1, in order to separate the multiphase AC voltage into a normal phase component and a reverse phase component, a delay of at least 1/4 cycle occurs, and a 1/4 cycle occurs. In the following, there is a problem that the voltage of the power system cannot be obtained correctly, and the negative phase voltage cannot be suppressed against the generation of a transient negative phase voltage.

この発明は上記のような課題を解決するためになされたものであり、交流電力系統が電圧不平衡になり過渡的に逆相電圧による過電圧が発生した場合でも、電力変換回路の過電流を抑制しつつ、高速に過電圧を抑制し運転することができる逆相制御による過電圧抑制制御方式を得ることを目的とする。   The present invention has been made to solve the above-described problems, and suppresses overcurrent of the power conversion circuit even when the AC power system becomes unbalanced and an overvoltage due to a reverse phase voltage transiently occurs. However, an object of the present invention is to obtain an overvoltage suppression control system based on reverse phase control that can suppress overvoltage and operate at high speed.

この発明は、電力系統に接続され、交流電力と直流電力を双方向に変換し、直流側の電圧をパルス幅変調制御する電力変換回路と、電力系統の電圧を検出する交流電圧検出器と、電力変換回路から電力系統に流れる電流を検出する交流電流検出器と、交流電圧検出器の検出値から基準位相を検出する位相検出器と、交流電流検出器の検出値と位相検出器の検出した基準位相から、有効電流成分Idと無効電流成分Iqとを検出する電流成分検出器と、有効電流指令値Id*と有効電流成分Id、および無効電流指令値Iq*と無効電流成分Iqとの偏差を増幅しその出力を電力変換回路の電圧指令値として電力変換回路の出力交流電流をフィードバック制御する増幅器と、交流電圧検出器の検出値から各相の電圧振幅と位相とを検出する電圧振幅位相検出器と、この電圧振幅位相検出器の検出する各相の電圧振幅と位相から、電力系統の電圧振幅平均値Vm、および位相平均値Φmを演算するとともに、この電圧振幅平均値Vm、位相平均値Φmを第1の座標変換器で変換して、平均電圧成分Vdm、Vqmを演算する平均値演算手段と、この平均値演算手段の出力値を加算して、増幅器の出力する電力変換回路の電圧指令値を補正し、補正後の電圧指令Vd*、Vq*を交流3相系統電圧値に演算する第2の座標変換器と、電圧振幅位相検出器の検出値と、電圧振幅平均値Vmおよび位相平均値Φmの振幅偏差および位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcを演算する偏差演算手段と、前記振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcを入力するとともに、この振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcに対する第1の動作しきい値Vth1、Φth1を有し電力変換回路の出力する過電流を抑制する過電流抑制不感帯器、および偏差に対する第2の動作しきい値Vth2、Φth2を有し、電力変換回路の出力する過電圧を抑制する過電圧抑制不感帯器とを備えた逆相制御による過電圧抑制制御方式において、Vth1>Vth2と設定し、過電流抑制不感帯器は、振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcのいずれかが、第1の動作しきい値Vth1、Φth1を超えた場合に、偏差と同値の過電流抑制不感帯器出力値ΔVa〜ΔVc、ΔΦa〜ΔΦcを出力し、過電圧抑制不感帯器は、振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcのいずれかが、第2の動作しきい値Vth2、Φth2を超えた場合に、過電圧抑制不感帯器出力値ΔVva〜ΔVvc、ΔΦva〜ΔΦvcを出力するとともに、この過電圧抑制不感帯器出力値の内の偏差ΔVva〜ΔVvcを、過電流抑制不感帯器出力の内の偏差ΔVa〜ΔVcからそれぞれ減算して補正電圧偏差ΔVd〜ΔVfとし、さらに、過電圧抑制不感帯器出力値の内の偏差ΔΦva〜ΔΦvcを、過電流抑制不感帯器出力値の内の偏差ΔΦa〜ΔΦcからそれぞれ減算して補正位相偏差ΔΦd〜ΔΦfとしこの値を正弦波信号に演算し、この正弦波信号と補正電圧偏差ΔVd〜ΔVfとを乗算器で演算出力の電圧指令補正値ΔVa*〜ΔVc*と、第2の座標変換器の出力とを加算器で加算して電力変換回路の電圧指令値とし、この電圧指令値を入力するパルス幅変調器を介して電力変換回路を逆相制御による過電圧抑制制御方式である。   The present invention is connected to a power system, converts AC power and DC power bidirectionally, a power conversion circuit that performs pulse width modulation control on the DC voltage, an AC voltage detector that detects the voltage of the power system, AC current detector that detects the current flowing from the power conversion circuit to the power system, a phase detector that detects the reference phase from the detected value of the AC voltage detector, and the detected value of the AC current detector and the phase detector A current component detector that detects the active current component Id and the reactive current component Iq from the reference phase, a deviation between the active current command value Id * and the active current component Id, and the reactive current command value Iq * and the reactive current component Iq An amplifier that feedback-controls the output alternating current of the power conversion circuit using the output as a voltage command value of the power conversion circuit, and a voltage that detects the voltage amplitude and phase of each phase from the detection value of the AC voltage detector The voltage amplitude average value Vm and the phase average value Φm of the power system are calculated from the width phase detector and the voltage amplitude and phase of each phase detected by the voltage amplitude phase detector, and the voltage amplitude average value Vm, The phase average value Φm is converted by the first coordinate converter, the average value calculating means for calculating the average voltage components Vdm and Vqm, and the output value of the average value calculating means is added to convert the power output from the amplifier. A second coordinate converter that corrects the voltage command value of the circuit and calculates the corrected voltage commands Vd * and Vq * to AC three-phase system voltage values, a detected value of the voltage amplitude phase detector, and a voltage amplitude average A deviation calculating means for calculating the amplitude deviation and phase deviations ΔVa to ΔVc, ΔΦa to ΔΦc of the value Vm and the phase average value Φm, and the amplitude and phase deviations ΔVa to ΔVc and ΔΦa to ΔΦc are input, and the amplitude and phase deviation are input. ΔVa ~ An overcurrent suppression dead band device having first operation threshold values Vth1 and Φth1 for ΔVc and ΔΦa to ΔΦc and suppressing an overcurrent output from the power conversion circuit, and second operation threshold values Vth2 and Φth2 for deviations In the overvoltage suppression control system by the reverse phase control including the overvoltage suppression dead band suppressor that suppresses the overvoltage output from the power conversion circuit, Vth1> Vth2 is set, and the overcurrent suppression dead band has an amplitude and phase deviation ΔVa. When ΔVc, ΔΦa to ΔΦc exceed the first operating threshold values Vth1 and Φth1, overcurrent suppression dead band output values ΔVa to ΔVc and ΔΦa to ΔΦc that are equal to the deviation are output, and overvoltage The suppression dead band is an overvoltage suppression dead band when any of the amplitude and phase deviations ΔVa to ΔVc and ΔΦa to ΔΦc exceeds the second operation threshold values Vth2 and Φth2. Output values ΔVva to ΔVvc and ΔΦva to ΔΦvc are output, and deviations ΔVva to ΔVvc of the overvoltage suppression dead zone output values are subtracted from deviations ΔVa to ΔVc of the overcurrent suppression dead zone output, respectively. Deviations ΔVd to ΔVf, and deviations ΔΦva to ΔΦvc in the overvoltage suppression dead zone output values are subtracted from deviations ΔΦa to ΔΦc in the overcurrent suppression dead zone output values to obtain corrected phase deviations ΔΦd to ΔΦf. The value is calculated as a sine wave signal, and the sine wave signal and the correction voltage deviations ΔVd to ΔVf are multiplied by a multiplier, and the voltage command correction values ΔVa * to ΔVc * of the operation output are added to the output of the second coordinate converter. This is an overvoltage suppression control method based on reverse phase control of the power conversion circuit via a pulse width modulator that inputs the voltage command value by adding the voltage to a voltage command value of the power conversion circuit.

この発明に係る逆相制御による過電圧抑制制御方式は、電力系統の電圧を検出する交流電圧検出器と、電力変換回路から電力系統に流れる電流を検出する交流電流検出器と、交流電圧検出器の検出値から基準位相を検出する位相検出器と、交流電流検出器の検出値と前記位相検出器の検出した基準位相から、有効電流成分Idと無効電流成分Iqとを検出する電流成分検出器と、有効電流指令値Id*と有効電流成分Id、および無効電流指令値Iq*と無効電流成分Iqとの偏差を増幅しその出力を電力変換回路の電圧指令値として電力変換回路の出力交流電流をフィードバック制御する増幅器と、交流電圧検出器の検出値から各相の電圧振幅と位相とを検出する電圧振幅位相検出器と、この電圧振幅位相検出器の検出する各相の電圧振幅と位相から、電力系統の電圧振幅平均値Vm、および位相平均値Φmを演算するとともに、この電圧振幅平均値Vm、位相平均値Φmを第1の座標変換器で変換して、平均電圧成分Vdm、Vqmを演算する平均値演算手段と、この平均値演算手段の出力値を加算して、増幅器の出力する電力変換回路の電圧指令値を補正し、補正後の電圧指令Vd*、Vq*を交流3相系統電圧値に演算する第2の座標変換器と、電圧振幅位相検出器の検出値と、電圧振幅平均値Vmおよび位相平均値Φmの振幅偏差および位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcを演算する偏差演算手段と、振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcを入力するとともに、この振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcに対する第1の動作しきい値Vth1、Φth1を有し電力変換回路の出力する過電流を抑制する過電流抑制不感帯器、および偏差に対する第2の動作しきい値Vth2、Φth2を有し、電力変換回路の出力する過電圧を抑制する過電圧抑制不感帯器とを備えた逆相制御による過電圧抑制制御方式において、Vth1>Vth2と設定し、過電流抑制不感帯器は、振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcのいずれかが、第1の動作しきい値Vth1、Φth1を超えた場合に、偏差と同値の過電流抑制不感帯器出力値ΔVa〜ΔVc、ΔΦa〜ΔΦcを出力し、過電圧抑制不感帯器は、振幅、位相偏差ΔVa〜ΔVc、ΔΦa〜ΔΦcのいずれかが、第2の動作しきい値Vth2、Φth2を超えた場合に、過電圧抑制不感帯器出力値ΔVva〜ΔVvc、ΔΦva〜ΔΦvcを出力するとともに、この過電圧抑制不感帯器出力値の内の偏差ΔVva〜ΔVvcを、過電流抑制不感帯器出力の内の偏差ΔVa〜ΔVcからそれぞれ減算して補正電圧偏差ΔVd〜ΔVfとし、さらに、過電圧抑制不感帯器出力値の内の偏差ΔΦva〜ΔΦvcを、過電流抑制不感帯器出力値の内の偏差ΔΦa〜ΔΦcからそれぞれ減算して補正位相偏差ΔΦd〜ΔΦfとしこの値を正弦波信号に演算し、この正弦波信号と補正電圧偏差ΔVd〜ΔVfとを乗算器で演算出力の電圧指令補正値ΔVa*〜ΔVc*と、第2の座標変換器の出力とを加算器で加算して電力変換回路の電圧指令値とし、この電圧指令値を入力するパルス幅変調器を介して電力変換回路を制御するので、事故時などに発生する電力系統の電圧不平衡を平衡に近づけるように制御することが可能となり、過渡的な交流過電圧に対しても過電流を抑制しつつ、高速な応答で抑制することができるという効果がある。   An overvoltage suppression control method using reverse phase control according to the present invention includes an AC voltage detector that detects a voltage of a power system, an AC current detector that detects a current flowing from the power conversion circuit to the power system, and an AC voltage detector. A phase detector for detecting a reference phase from the detection value; a current component detector for detecting an active current component Id and a reactive current component Iq from the detection value of the AC current detector and the reference phase detected by the phase detector; The deviation between the active current command value Id * and the active current component Id, the reactive current command value Iq * and the reactive current component Iq is amplified, and the output is the voltage command value of the power conversion circuit, and the output AC current of the power conversion circuit is An amplifier for feedback control, a voltage amplitude phase detector for detecting the voltage amplitude and phase of each phase from the detection value of the AC voltage detector, and the voltage amplitude of each phase detected by this voltage amplitude phase detector From the phase, the voltage amplitude average value Vm and the phase average value Φm of the power system are calculated, and the voltage amplitude average value Vm and the phase average value Φm are converted by the first coordinate converter to obtain an average voltage component Vdm, The average value calculating means for calculating Vqm and the output value of the average value calculating means are added to correct the voltage command value of the power conversion circuit output from the amplifier, and the corrected voltage commands Vd * and Vq * are exchanged. The second coordinate converter for calculating the three-phase system voltage value, the detected value of the voltage amplitude phase detector, the amplitude deviation of the voltage amplitude average value Vm and the phase average value Φm, and the phase deviations ΔVa to ΔVc, ΔΦa to ΔΦc Deviation calculation means for calculating and input amplitude and phase deviations ΔVa to ΔVc, ΔΦa to ΔΦc, and have first operation threshold values Vth1 and Φth1 for the amplitudes and phase deviations ΔVa to ΔVc, ΔΦa to ΔΦc. An overcurrent suppression dead band suppressor that suppresses overcurrent output from the power conversion circuit, and an overvoltage suppression dead band suppressor that has second operation threshold values Vth2 and Φth2 for deviation and suppresses the overvoltage output from the power conversion circuit. In the overvoltage suppression control method based on the reverse phase control provided, Vth1> Vth2 is set, and the overcurrent suppression dead zone device has any one of the amplitude, the phase deviations ΔVa to ΔVc, and ΔΦa to ΔΦc as the first operation threshold value Vth1. , Φth1 is exceeded, the overcurrent suppression dead band output values ΔVa to ΔVc and ΔΦa to ΔΦc which are the same as the deviation are output. Output overvoltage suppression dead band output values ΔVva to ΔVvc and ΔΦva to ΔΦvc when the second operating threshold value Vth2 and Φth2 are exceeded. The deviations ΔVva to ΔVvc in the pressure suppression dead band output value are subtracted from the deviations ΔVa to ΔVc in the over current suppression dead band output, respectively, to obtain correction voltage deviations ΔVd to ΔVf, and further the overvoltage suppression dead band output value Deviations ΔΦva to ΔΦvc are subtracted from the deviations ΔΦa to ΔΦc of the overcurrent suppression dead zone output values to obtain corrected phase deviations ΔΦd to ΔΦf, which are calculated into sine wave signals, and the sine wave signals and corrections The voltage deviations ΔVd to ΔVf are calculated by the multiplier and the voltage command correction values ΔVa * to ΔVc * of the operation output are added to the output of the second coordinate converter by the adder to obtain the voltage command value of the power conversion circuit. Since the power conversion circuit is controlled via the pulse width modulator that inputs the voltage command value, it is possible to control the power system voltage imbalance that occurs in the event of an accident, etc. It is possible to suppress the overcurrent against a high AC overvoltage while suppressing the overcurrent with a high-speed response.

実施の形態1.
以下、この発明の実施の形態1を図に基づいて説明する。
図1は、実施の形態1の逆相制御による過電圧抑制制御方式に係る電力変換装置200を示す構成図である。図1において、電力変換回路1の交流側はリアクトル2を介して電力系統4に接続されており、直流側はコンデンサ3に接続されている。電力系統4の電圧は、交流電圧検出器6によって検出され、その位相θは位相検出器7で検出する。電力変換回路1から電力系統4に流れる電流は、交流電流検出器5で検出され、電流成分検出器101によって位相θを基準とした回転座標系へ変換されて、有効電流成分Idと無効電流成分Iqとが検出される。
前記各電流成分Id、Iqは、減算器102a、102bによりその指令値Id*、Iq*との偏差を演算され、増幅器103a、103bでその偏差を増幅する。
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram illustrating a power conversion device 200 according to an overvoltage suppression control method based on reverse phase control according to the first embodiment. In FIG. 1, the AC side of the power conversion circuit 1 is connected to a power system 4 via a reactor 2, and the DC side is connected to a capacitor 3. The voltage of the power system 4 is detected by the AC voltage detector 6, and the phase θ is detected by the phase detector 7. The current flowing from the power conversion circuit 1 to the power system 4 is detected by the AC current detector 5 and converted by the current component detector 101 into a rotating coordinate system with the phase θ as a reference, and the effective current component Id and the reactive current component. Iq is detected.
The respective current components Id and Iq are calculated with respect to their command values Id * and Iq * by the subtracters 102a and 102b, and are amplified by the amplifiers 103a and 103b.

加算器109a、109bは、位相検出器7で検出した位相θと、電力系統4の3相電圧の位相差に相当する固定値ΦvとΦwを加算する。電圧振幅位相検出器108a〜108cは、交流電圧検出器6で検出した各相の電圧と、前記加算器109a、109bの出力値とから電圧振幅Va〜Vcと位相Φa〜Φcを検出する。電圧振幅加算器110aは前記電圧振幅Va〜Vcを加算し、その値を入力するゲイン111aは電力系統4の3相電圧振幅の平均値Vmを演算する。
また、位相加算器110bは前記位相Φa〜Φcを加算し、その値を入力するゲイン111bは位相平均値Φmを演算する。そして第1の座標変換器114では、前記電圧振幅平均値Vmと、位相平均値Φmを極座標から直交座標に変換し、平均電圧成分VdmとVqmを演算する。
The adders 109 a and 109 b add the phase θ detected by the phase detector 7 and the fixed values Φv and Φw corresponding to the phase difference between the three-phase voltages of the power system 4. The voltage amplitude phase detectors 108a to 108c detect the voltage amplitudes Va to Vc and the phases Φa to Φc from the voltages of the respective phases detected by the AC voltage detector 6 and the output values of the adders 109a and 109b. The voltage amplitude adder 110a adds the voltage amplitudes Va to Vc, and the gain 111a for inputting the value calculates the average value Vm of the three-phase voltage amplitudes of the power system 4.
The phase adder 110b adds the phases [Phi] a to [Phi] c, and the gain 111b for inputting the values calculates the phase average value [Phi] m. Then, the first coordinate converter 114 converts the voltage amplitude average value Vm and the phase average value Φm from polar coordinates to orthogonal coordinates, and calculates average voltage components Vdm and Vqm.

加算器104a、104bは、前記増幅器103a、103bで電流偏差を増幅した信号と、前記平均電圧成分Vdm、Vqmとを加算して電圧指令Vd*、Vq*とし、これを入力する第2の座標変換器105によって直交座標から3相座標に変換される。
減算器112a〜112cは、前記電圧振幅Va〜Vcと電圧振幅平均値Vmとから電圧差振幅偏差ΔVa〜ΔVcを演算する。減算器113a〜113cは、前記位相Φa〜Φcと位相平均値Φmとから位相偏差ΔΦa〜ΔΦcを演算する。過電流抑制不感帯器115は、前記ΔVa〜ΔVc、ΔΦa〜ΔΦcを入力し、演算結果として過電流抑制不感帯器出力値ΔVa〜ΔVc、ΔΦa〜ΔΦcを出力する。また、過電圧抑制不感帯器116にも前記減算器112a〜112c、113a〜113cの演算出力値ΔVa〜ΔVcおよびΔΦa〜ΔΦcが入力され、演算結果として過電圧抑制不感帯器出力値ΔVva〜ΔVvc、ΔΦva〜ΔΦvcを出力する。
The adders 104a and 104b add the signals obtained by amplifying the current deviation by the amplifiers 103a and 103b and the average voltage components Vdm and Vqm to obtain voltage commands Vd * and Vq *, and input the second coordinates. The converter 105 converts the orthogonal coordinates into three-phase coordinates.
The subtractors 112a to 112c calculate voltage difference amplitude deviations ΔVa to ΔVc from the voltage amplitudes Va to Vc and the voltage amplitude average value Vm. The subtractors 113a to 113c calculate phase deviations ΔΦa to ΔΦc from the phases Φa to Φc and the phase average value Φm. The overcurrent suppression dead band unit 115 receives the ΔVa to ΔVc and ΔΦa to ΔΦc, and outputs overcurrent suppression dead band output values ΔVa to ΔVc and ΔΦa to ΔΦc as calculation results. Further, the calculated output values ΔVa to ΔVc and ΔΦa to ΔΦc of the subtractors 112a to 112c and 113a to 113c are also input to the overvoltage suppression dead zone device 116, and the overvoltage suppression dead zone output values ΔVva to ΔVvc and ΔΦva to ΔΦvc are calculated as the calculation results. Is output.

減算器117a〜117cは、前記過電流抑制不感帯器115の出力値ΔVa〜ΔVcと、前記過電圧抑制不感帯器116の出力値ΔVva〜ΔVvcを入力、演算して補正電圧偏差ΔVd〜ΔVfを出力する。
また、減算器117d〜117fは、前記過電流抑制不感帯器115の出力値ΔΦa〜ΔΦcと、前記過電圧抑制不感帯器116の出力値ΔΦva〜ΔΦvcを入力、演算して各相の補正位相偏差ΔΦd〜ΔΦfを出力する。正弦波器118は、位相検出器7の検出する位相θと、前記補正位相偏差ΔΦd〜ΔΦfを入力して正弦波信号に演算する。乗算器119a〜119cは、前記正弦波器118の演算出力と前記補正電圧偏差ΔVd〜ΔVfとを入力し、演算、結果として電圧指令補正値ΔVa*〜ΔVc*を出力する。
The subtractors 117a to 117c input and calculate the output values ΔVa to ΔVc of the overcurrent suppression dead zone device 115 and the output values ΔVva to ΔVvc of the overvoltage suppression dead zone device 116, and output corrected voltage deviations ΔVd to ΔVf.
Further, the subtractors 117d to 117f receive and calculate the output values ΔΦa to ΔΦc of the overcurrent suppression dead zone 115 and the output values ΔΦva to ΔΦvc of the overvoltage suppression dead zone 116, and correct phase deviations ΔΦd to ΔΦf is output. The sine wave device 118 receives the phase θ detected by the phase detector 7 and the corrected phase deviations ΔΦd to ΔΦf and calculates them into a sine wave signal. The multipliers 119a to 119c receive the calculation output of the sine wave generator 118 and the correction voltage deviations ΔVd to ΔVf, and output the voltage command correction values ΔVa * to ΔVc * as a result.

加算器106a〜106cは、前記第2の座標変換器105の出力と、前記電圧指令補正値ΔVa*〜ΔVc*とを入力、演算して、電圧指令値Va*〜Vc*を出力する。パルス幅変調器107は、前記電圧指令値Va*〜Vc*を入力し、電力変換回路1内の半導体素子のON/OFF信号を出力する。   The adders 106a to 106c input and calculate the output of the second coordinate converter 105 and the voltage command correction values ΔVa * to ΔVc *, and output voltage command values Va * to Vc *. The pulse width modulator 107 receives the voltage command values Va * to Vc * and outputs an ON / OFF signal of a semiconductor element in the power conversion circuit 1.

次に動作について説明する。
交流電流検出器5は、電力変換回路1が出力する交流電流を検出し、電流成分検出器101で前記交流電流を有効電流成分Idと無効電流成分Iqに分ける。この電流成分検出器101は、電力系統4の位相を基準とするため、交流電圧検出器6で検出した電力系統電圧の基準相、例えばa相と同期した位相を検出する位相検出器7が出力する位相θを用いる。
減算器102a、102bは、前記有効電流成分Id、無効電流成分Iqをそれぞれに入力するとともに、有効電流指令値Id*と無効電流指令値Iq*との偏差を演算し、それぞれの偏差を増幅器103a、103bに出力する。この増幅器103a、103bは、前記偏差を入力、増幅して電力変換回路1の電圧指令値を生成し、電流制御系としてフィードバック制御を行って、電力変換装置200が出力する電流が指令値に一致するように動作する。
加算器104a、104bは、前記増幅器103a、103bの出力と、電力系統4の交流三相電圧のdq成分の平均値である平均電圧成分Vdm、Vqmを加算、演算し、電圧指令Vd*、Vq*を出力する。第2の座標変換器105は、前記電圧指令Vd*、Vq*をdq座標系から交流三相系に演算する。後に詳説する乗算器119a〜119cの出力する電圧指令補正値ΔVa*〜ΔVc*と、第2の座標変換器105の出力は加算器106a〜106cによって加算、演算され、電圧指令値Va*〜Vc*を出力する。パルス幅変調器107は、電圧指令値Va*〜Vc*に応じた電圧が電力変換回路1から出力されるようにゲートパルスを生成し電力変換回路1の半導体素子へ与える。電力変換回路1はゲートパルスに従ってスイッチングを行ない、電力系統4側に電圧指令値Va*〜Vc*に応じた電圧を出力する。
Next, the operation will be described.
The alternating current detector 5 detects the alternating current output from the power conversion circuit 1, and the current component detector 101 divides the alternating current into an effective current component Id and a reactive current component Iq. Since the current component detector 101 is based on the phase of the power system 4, the phase detector 7 that detects the phase synchronized with the reference phase of the power system voltage detected by the AC voltage detector 6, for example, the a phase, is output. The phase θ to be used is used.
The subtractors 102a and 102b receive the effective current component Id and the reactive current component Iq, respectively, calculate the deviation between the active current command value Id * and the reactive current command value Iq *, and calculate the respective deviations by the amplifier 103a. , 103b. The amplifiers 103a and 103b input and amplify the deviation to generate a voltage command value for the power conversion circuit 1, perform feedback control as a current control system, and the current output from the power conversion device 200 matches the command value. To work.
The adders 104a and 104b add and calculate the output of the amplifiers 103a and 103b and the average voltage components Vdm and Vqm, which are average values of the dq components of the AC three-phase voltage of the power system 4, and calculate the voltage commands Vd * and Vq. * Is output. The second coordinate converter 105 calculates the voltage commands Vd * and Vq * from the dq coordinate system to an AC three-phase system. The voltage command correction values ΔVa * to ΔVc * output from the multipliers 119a to 119c, which will be described in detail later, and the output of the second coordinate converter 105 are added and calculated by the adders 106a to 106c to obtain the voltage command values Va * to Vc. * Is output. The pulse width modulator 107 generates a gate pulse so that a voltage corresponding to the voltage command values Va * to Vc * is output from the power conversion circuit 1, and supplies the gate pulse to the semiconductor element of the power conversion circuit 1. The power conversion circuit 1 performs switching according to the gate pulse, and outputs a voltage corresponding to the voltage command values Va * to Vc * to the power system 4 side.

前記電圧指令補正値ΔVa*〜ΔVc*が、前記乗算器119a〜119cによって出力されるまでの経過を以下に詳説する。
電圧振幅位相検出器108a〜108cは、電圧検出器6が検出する各相の電力系統4の電圧と、位相検出器7が出力する交流電圧の基準位相θとから、各相の電力系統電圧の振幅Va〜Vcと位相Φa〜Φcをそれぞれ検出する。電圧振幅加算器110aによって、前記各相の電力系統電圧振幅Va〜Vcは加算され、その加算結果がゲイン111aにより1/3倍されることで、各相の電力系統電圧振幅の平均値Vmが演算される。同様に前記各相の電力系統電圧位相Φa〜Φcは、位相加算器110bによって加算され、その加算結果がゲイン111bにより1/3倍されることで、各相の電力系統位相の平均値Φmが演算される。第1の座標変換器114によって前記Vm、Φmの極座標からdq軸座標Vdm、Vqmに変換される。
また、減算器112a〜112cによって前記各相の電力系統電圧振幅Va〜Vcと、前記電力系統電圧振幅の平均値Vmとから電圧差振幅偏差ΔVa〜ΔVcが演算される。同様に、減算器113a〜113cによって前記各相の電力系統電圧位相Φa〜Φcと、前記電力系統位相の平均値Φmとから位相偏差ΔΦa〜ΔΦcが演算される。
The process until the voltage command correction values ΔVa * to ΔVc * are output by the multipliers 119a to 119c will be described in detail below.
The voltage amplitude phase detectors 108a to 108c determine the power system voltage of each phase from the voltage of the power system 4 of each phase detected by the voltage detector 6 and the reference phase θ of the AC voltage output from the phase detector 7. Amplitudes Va to Vc and phases Φa to Φc are detected, respectively. The voltage amplitude adder 110a adds the power system voltage amplitudes Va to Vc of each phase, and the addition result is multiplied by 1/3 by the gain 111a, so that the average value Vm of the power system voltage amplitude of each phase is obtained. Calculated. Similarly, the power system voltage phases Φa to Φc of each phase are added by the phase adder 110b, and the addition result is multiplied by 1/3 by the gain 111b, so that the average value Φm of the power system phase of each phase is obtained. Calculated. The first coordinate converter 114 converts the polar coordinates of Vm and Φm to the dq axis coordinates Vdm and Vqm.
Further, voltage difference amplitude deviations ΔVa to ΔVc are calculated from the power system voltage amplitudes Va to Vc of the respective phases and the average value Vm of the power system voltage amplitudes by the subtractors 112a to 112c. Similarly, phase deviations ΔΦa to ΔΦc are calculated from the power system voltage phases Φa to Φc of the respective phases and the average value Φm of the power system phases by the subtractors 113a to 113c.

過電流抑制不感帯器115に振幅偏差ΔVa〜ΔVc、位相偏差ΔΦa〜ΔΦcに対するそれぞれの第1の動作しきい値Vth1、Φth1を設定する。各偏差のいずれかが、第1の動作しきい値Vth1、Φth1を超えた場合、過電流抑制不感帯器115が、入力値と等しい過電流抑制不感帯器出力値ΔVa〜ΔVc、ΔΦa〜ΔΦcをそれぞれ出力する。各偏差のいずれも、第1の動作しきい値Vth1、Φth1を超えない場合、過電流抑制不感帯器115は全て零を出力する。各偏差のいずれかが第1の動作しきい値Vth1、Φth1を超えた場合、減算器117a〜117cには前記過電流抑制不感帯器出力値のΔVa〜ΔVcがそれぞれ入力されるとともに、減算器117d〜117fにはΔΦa〜ΔΦcが入力される。   The first operation threshold values Vth1 and Φth1 for the amplitude deviations ΔVa to ΔVc and the phase deviations ΔΦa to ΔΦc are set in the overcurrent suppression dead band 115. When any one of the deviations exceeds the first operation threshold values Vth1 and Φth1, the overcurrent suppression dead zone device 115 sets the overcurrent suppression dead zone output values ΔVa to ΔVc and ΔΦa to ΔΦc equal to the input values, respectively. Output. When none of the deviations exceeds the first operation threshold values Vth1 and Φth1, the overcurrent suppression dead band device 115 outputs all zeros. When any of the deviations exceeds the first operating threshold values Vth1 and Φth1, the overcurrent suppression dead band output values ΔVa to ΔVc are respectively input to the subtractors 117a to 117c, and the subtractor 117d. .DELTA..PHI.a to .DELTA..PHI.c are input to .about.117f.

過電圧抑制不感帯器116に振幅偏差ΔVa〜ΔVc、位相偏差ΔΦa〜ΔΦcに対するそれぞれの第2の動作しきい値Vth2、Φth2を設定する。ここで前記第1の動作しきい値Vth1>第2の動作しきい値Vth2と設定する。各偏差のいずれかが、第2の動作しきい値Vth2、Φth2を超えた場合、過電圧抑制不感帯器116は、過電圧抑制不感帯器出力値であるΔVva〜ΔVvc、ΔΦva〜ΔΦvcをそれぞれ出力とする。
各偏差のいずれもが、第2の動作しきい値Vth2、Φth2を超えない場合、過電圧抑制不感帯器116はすべて零を出力する。各偏差のいずれかが第2の動作しきい値Vth2、Φth2を超えた場合、減算器117a〜117fにはΔVva〜ΔVvc、ΔΦva〜ΔΦvcが入力される。前記減算器117a〜117cには、前記過電流抑制不感帯器出力値ΔVa〜ΔVcが入力されており、このΔVa〜ΔVcと前記ΔVva〜ΔVvcが演算され、補正電圧偏差ΔVd〜ΔVfを出力する。また、減算器117d〜117fには、前記過電流抑制不感帯器出力値ΔΦa〜ΔΦcが入力されており、このΔΦa〜ΔΦcと前記ΔΦva〜ΔΦvcが演算され、補正位相偏差ΔΦd〜ΔΦfを出力する。
ここで過電圧抑制不感帯器116を設置していることの重要性について述べる。
過電流抑制不感帯器115のみの構成の場合には、電力系統の多相交流電圧が不平衡となった時、電力変換回路1が出力する過電流を抑制することができるが、電力系統4に過電圧が発生し、電力変換装置200が停止する可能性がある。ところが本実施の形態では、過電圧抑制不感帯器116を設置し、前記過電流抑制に伴って発生する系統電圧を抑制するために、過電圧抑制不感帯器116を設けるとともに、過電流抑制不感帯器115に設けた第1の動作しきい値Vth1よりも小さな値の第2の動作しきい値Vth2を有しているので、上述した如き電力変換装置200が停止するケースを未然に防止することができる。
The second operation threshold values Vth2 and Φth2 for the amplitude deviations ΔVa to ΔVc and the phase deviations ΔΦa to ΔΦc are set in the overvoltage suppression dead zone 116, respectively. Here, the first operation threshold value Vth1> the second operation threshold value Vth2 is set. When any one of the deviations exceeds the second operation threshold values Vth2 and Φth2, the overvoltage suppression dead zone device 116 outputs ΔVva to ΔVvc and ΔΦva to ΔΦvc, which are overvoltage suppression dead zone output values, respectively.
When none of the deviations exceeds the second operation threshold values Vth2 and Φth2, the overvoltage suppression dead band device 116 outputs all zeros. When any of the deviations exceeds the second operation threshold values Vth2 and Φth2, ΔVva to ΔVvc and ΔΦva to ΔΦvc are input to the subtractors 117a to 117f. The subcurrentrs 117a to 117c are inputted with the overcurrent suppression dead zone output values ΔVa to ΔVc, and ΔVa to ΔVc and ΔVva to ΔVvc are calculated to output correction voltage deviations ΔVd to ΔVf. Further, the overcurrent suppression dead zone output values ΔΦa to ΔΦc are input to the subtractors 117d to 117f, and ΔΦa to ΔΦc and ΔΦva to ΔΦvc are calculated to output corrected phase deviations ΔΦd to ΔΦf.
Here, the importance of installing the overvoltage suppression dead band 116 will be described.
In the case of the configuration with only the overcurrent suppression dead band 115, the overcurrent output from the power conversion circuit 1 can be suppressed when the multiphase AC voltage of the power system becomes unbalanced. There is a possibility that an overvoltage occurs and the power conversion device 200 stops. However, in the present embodiment, an overvoltage suppression dead zone 116 is provided, and an overvoltage suppression dead zone 116 is provided and an overcurrent suppression dead zone 115 is provided in order to suppress the system voltage generated due to the overcurrent suppression. Since the second operation threshold value Vth2 is smaller than the first operation threshold value Vth1, it is possible to prevent the case where the power conversion apparatus 200 stops as described above.

正弦波器118は、前記補正位相偏差ΔΦd〜ΔΦfと、位相検出器7の検出する位相θを入力して、正弦波信号に演算する。乗算器119a〜119cは、前記補正電圧偏差ΔVd〜ΔVfと、正弦波器118の出力信号を入力して、次式
ΔVa*=ΔVd×sin(θ+ΔΦd)
ΔVb*=ΔVe×sin(θ+ΔΦe)
ΔVc*=ΔVf×sin(θ+ΔΦf)
で演算し、電圧指令補正値ΔVa*、ΔVb*、ΔVc*を出力する。
The sine wave device 118 receives the corrected phase deviations ΔΦd to ΔΦf and the phase θ detected by the phase detector 7 and calculates a sine wave signal. The multipliers 119a to 119c receive the correction voltage deviations ΔVd to ΔVf and the output signal of the sine wave device 118, and the following expression ΔVa * = ΔVd × sin (θ + ΔΦd)
ΔVb * = ΔVe × sin (θ + ΔΦe)
ΔVc * = ΔVf × sin (θ + ΔΦf)
To calculate voltage command correction values ΔVa *, ΔVb *, ΔVc *.

前述したとおり加算器106a〜106cは、前記電圧指令補正値ΔVa*、ΔVb*、ΔVc*と、前記第2の座標変換器105の出力とを入力し、電圧指令値Va*〜Vc*を演算出力し、パルス幅変調器107は、前記電圧指令値Va*〜Vc*を入力し、ゲートパルス信号で電力変換回路1の制御を行う。   As described above, the adders 106a to 106c input the voltage command correction values ΔVa *, ΔVb *, ΔVc * and the output of the second coordinate converter 105, and calculate the voltage command values Va * to Vc *. The pulse width modulator 107 receives the voltage command values Va * to Vc * and controls the power conversion circuit 1 with a gate pulse signal.

この実施の形態1の電力変換装置200を備えた逆相制御による過電圧抑制制御方式では、電力系統4に不平衡成分を含んだ過電圧が発生した場合、過電圧は不平衡により振幅が最も高くなった相に発生するが、不平衡が発生した場合、過電流抑制不感帯器115に設けた第1の動作しきい値Vth1、Φth1をΔVa〜ΔVc、ΔΦa〜ΔΦcのいずれかが超えたとき、電力変換装置200の過電流を抑制しつつ、かつ第1の動作しきい値Vth1>第2の動作しきい値Vth2とし、さらに第2の動作しきい値Vth2、Φth2を超えた場合にはΔVva〜ΔVvc、ΔΦva〜ΔΦvcにより電圧指令値Va*〜Vc*が補正されて電力系統4の電圧不平衡を抑制するように電力変換回路1の交流電圧を出力することができる。したがって電力系統4の電圧不平衡を抑制すれば、過電圧となる相の電圧振幅を抑制できるため過電圧を抑制することができる。さらに過電流抑制不感帯器115の第1の動作しきい値Vth1、Φth1、過電圧抑制不感帯器116の第2の動作しきい値Vth2、Φth2を調整することで、電力系統の状態に対応して、電力変換装置200の過電流を抑制しつつ電力系統4の過電圧を抑制することができる。   In the overvoltage suppression control method based on the reverse phase control provided with the power conversion device 200 according to the first embodiment, when an overvoltage including an unbalanced component occurs in the power system 4, the overvoltage has the highest amplitude due to the unbalance. When an unbalance occurs in the phase, but when any of ΔVa to ΔVc and ΔΦa to ΔΦc exceeds the first operating threshold Vth1 and Φth1 provided in the overcurrent suppression dead zone 115, power conversion When the overcurrent of the apparatus 200 is suppressed and the first operation threshold value Vth1> the second operation threshold value Vth2, and the second operation threshold values Vth2 and Φth2 are exceeded, ΔVva to ΔVvc The voltage command values Va * to Vc * are corrected by ΔΦva to ΔΦvc, and the AC voltage of the power conversion circuit 1 can be output so as to suppress the voltage imbalance of the power system 4. Therefore, if the voltage imbalance of the electric power system 4 is suppressed, the voltage amplitude of the phase that becomes an overvoltage can be suppressed, so that the overvoltage can be suppressed. Furthermore, by adjusting the first operation threshold Vth1, Φth1 of the overcurrent suppression dead band 115 and the second operation threshold Vth2, Φth2 of the overvoltage suppression dead band 116, according to the state of the power system, The overvoltage of the electric power grid | system 4 can be suppressed, suppressing the overcurrent of the power converter device 200. FIG.

実施の形態2.
図2は、本発明の実施の形態2の逆相制御による過電圧抑制制御方式に係る電力変換装置200を示す構成図である。図1と同じ部分は説明を省略する。
過電圧抑制不感帯器116の出力端にゲイン要素120a〜120cを設け、出力値のΔVva〜ΔVvcにゲイン120a〜120cを乗じた出力を減算器117a〜117cに入力する。
Embodiment 2. FIG.
FIG. 2 is a configuration diagram showing a power conversion device 200 according to an overvoltage suppression control method based on reverse phase control according to Embodiment 2 of the present invention. Description of the same parts as those in FIG. 1 is omitted.
Gain elements 120a to 120c are provided at the output terminals of the overvoltage suppression dead zone 116, and outputs obtained by multiplying the output values ΔVva to ΔVvc by the gains 120a to 120c are input to the subtractors 117a to 117c.

次に動作について説明する。図1と同じ動作については説明を省略する。過電圧抑制不感帯器116出力のうちΔVva〜ΔVvcはゲイン120a〜120cによって増幅され、電圧補正信号の振幅の補正度合いを変更する。   Next, the operation will be described. The description of the same operation as in FIG. 1 is omitted. Of the overvoltage suppression dead band 116 output, ΔVva to ΔVvc are amplified by gains 120a to 120c to change the degree of correction of the amplitude of the voltage correction signal.

このように動作して、ゲイン120a〜120cの値を調整することで、電圧不平衡の抑制度合いを調整できる。従って、電力系統の過電圧の抑制度合いを調整しながら、電力変換装置200の過電流を抑制しつつ交流系統の過電圧を抑制することができる。   By operating in this way and adjusting the values of the gains 120a to 120c, the degree of suppression of voltage imbalance can be adjusted. Therefore, it is possible to suppress the overvoltage of the AC system while suppressing the overcurrent of the power conversion device 200 while adjusting the degree of suppression of the overvoltage of the power system.

実施の形態3.
図3は、本発明の実施の形態3の逆相制御による過電圧抑制制御方式に係る電力変換装置200を示す構成図である。図1、図2と同じ部分は説明を省略する。
実施の形態2のゲイン120a〜120cはリミッタを設け減算器117a〜117cに出力する。
Embodiment 3 FIG.
FIG. 3 is a configuration diagram showing a power conversion device 200 according to an overvoltage suppression control method based on reverse phase control according to Embodiment 3 of the present invention. Description of the same parts as those in FIGS. 1 and 2 is omitted.
The gains 120a to 120c of the second embodiment are provided with limiters and output to the subtracters 117a to 117c.

次に動作について説明する。図1、図2と同じ動作については説明を省略する。
ゲイン120a〜120cにリミッタをかけることで、電圧不平衡を補正する電圧補正信号の振幅の補正度合いを制限する。
Next, the operation will be described. The description of the same operation as in FIGS. 1 and 2 is omitted.
By limiting the gains 120a to 120c, the degree of correction of the amplitude of the voltage correction signal for correcting the voltage imbalance is limited.

このように動作して、ゲイン120a〜120cの出力を制限することで、電力変換装置200の過電流の抑制を主動作としつつ、電力変換装置200の容量範囲内で電力系統4の過電圧を抑制するように過電圧抑制量を制限することができる。   By operating in this way and limiting the output of the gains 120a to 120c, the overcurrent of the power conversion device 200 is suppressed within the capacity range of the power conversion device 200 while suppressing the overcurrent of the power conversion device 200 as a main operation. Thus, the overvoltage suppression amount can be limited.

この発明は、電力系統に接続される系統過電圧を抑制する電力変換装置の制御方式に利用可能である。   The present invention can be used for a control method of a power converter that suppresses system overvoltage connected to the power system.

この発明の実施の形態1の電力変換装置を示す構成図である。It is a block diagram which shows the power converter device of Embodiment 1 of this invention. この発明の実施の形態2の電力変換装置を示す構成図である。It is a block diagram which shows the power converter device of Embodiment 2 of this invention. この発明の実施の形態3の電力変換装置を示す構成図である。It is a block diagram which shows the power converter device of Embodiment 3 of this invention.

符号の説明Explanation of symbols

1 電力変換回路、4 電力系統、5 交流電流検出器、6 交流電圧検出器、
7 位相検出器、101 電流成分検出器、102a〜102c 減算器、
103a〜103b 増幅器、104a〜104c 加算器、
105 第2の座標変換器、106a〜106c 加算器、107 パルス幅変調器、
108a〜108c 電圧振幅位相検出器、112a〜112c 減算器、
113a〜113c 減算器、114 第1の座標変換器、
115 過電流抑制不感帯器、116 過電圧抑制不感帯器、
117a〜117f 減算器、118 正弦波器、119a〜119c 乗算器、
120a〜120c ゲイン、121a〜121c リミッタ、200 電力変換装置、
Id 有効電流成分、Iq 無効電流成分、Id* 有効電流指令値、
Iq* 無効電流指令値、Va〜Vc 電圧振幅、Φa〜Φc 位相、
Vm 電力系統の電圧振幅平均値、Φm 電力系統の位相平均値、
Vdm,Vqm 平均電圧成分、ΔVa〜ΔVc 振幅偏差、
ΔΦa〜ΔΦc 位相偏差、ΔVva〜ΔVvc 過電圧抑制不感帯器出力値、
ΔΦva〜ΔΦvc 過電圧抑制不感帯器出力値、ΔVd〜ΔVf 補正電圧偏差、
ΔΦd〜ΔΦf 補正位相偏差、ΔVa*〜ΔVc* 電圧指令補正値、
Va*〜Vc* 電圧指令値。
1 power conversion circuit, 4 power system, 5 AC current detector, 6 AC voltage detector,
7 phase detector, 101 current component detector, 102a-102c subtractor,
103a to 103b amplifier, 104a to 104c adder,
105 second coordinate converter, 106a to 106c adder, 107 pulse width modulator,
108a-108c voltage amplitude phase detector, 112a-112c subtractor,
113a to 113c subtractor, 114 first coordinate converter,
115 Overcurrent suppression dead zone, 116 Overvoltage suppression dead zone,
117a to 117f subtractor, 118 sine wave device, 119a to 119c multiplier,
120a-120c gain, 121a-121c limiter, 200 power converter,
Id active current component, Iq reactive current component, Id * active current command value,
Iq * reactive current command value, Va to Vc voltage amplitude, Φa to Φc phase,
Vm Voltage system average value of power system, Φm Power system phase average value,
Vdm, Vqm Average voltage component, ΔVa to ΔVc amplitude deviation,
ΔΦa to ΔΦc phase deviation, ΔVva to ΔVvc overvoltage suppression dead band output value,
ΔΦva to ΔΦvc overvoltage suppression dead band output value, ΔVd to ΔVf correction voltage deviation,
ΔΦd to ΔΦf correction phase deviation, ΔVa * to ΔVc * voltage command correction value,
Va * to Vc * Voltage command value.

Claims (3)

電力系統に接続され、交流電力と直流電力を双方向に変換し、直流側の電圧をパルス幅変調制御する電力変換回路と、前記電力系統の電圧を検出する交流電圧検出器と、前記電力変換回路から前記電力系統に流れる電流を検出する交流電流検出器と、前記交流電圧検出器の検出値から基準位相を検出する位相検出器と、前記交流電流検出器の検出値と前記位相検出器の検出した基準位相から、有効電流成分(Id)と無効電流成分(Iq)とを検出する電流成分検出器と、有効電流指令値(Id*)と前記有効電流成分(Id)、および無効電流指令値(Iq*)と前記無効電流成分(Iq)との偏差を増幅しその出力を前記電力変換回路の電圧指令値として電力変換回路の出力交流電流をフィードバック制御する増幅器と、前記交流電圧検出器の検出値から各相の電圧振幅と位相とを検出する電圧振幅位相検出器と、この電圧振幅位相検出器の検出する各相の電圧振幅と位相から、電力系統の電圧振幅平均値(Vm)、および位相平均値(Φm)を演算するとともに、この電圧振幅平均値(Vm)、位相平均値(Φm)を第1の座標変換器で変換して、平均電圧成分(Vdm、Vqm)を演算する平均値演算手段と、この平均値演算手段の出力値を加算して、前記増幅器の出力する電力変換回路の電圧指令値を補正し、補正後の電圧指令(Vd*、Vq*)を交流3相系電圧値に演算する第2の座標変換器と、前記電圧振幅位相検出器の検出値と、前記電圧振幅平均値(Vm)および位相平均値(Φm)の振幅偏差および位相偏差(ΔVa〜ΔVc、ΔΦa〜ΔΦc)を演算する偏差演算手段と、前記振幅、位相偏差(ΔVa〜ΔVc、ΔΦa〜ΔΦc)を入力するとともに、この振幅、位相偏差(ΔVa〜ΔVc、ΔΦa〜ΔΦc)に対する第1の動作しきい値(Vth1、Φth1)を有し前記電力変換回路の出力する過電流を抑制する過電流抑制不感帯器、および前記偏差に対する第2の動作しきい値(Vth2、Φth2)を有し、前記電力変換回路の出力する過電圧を抑制する過電圧抑制不感帯器とを備えた逆相制御による過電圧抑制制御方式において、
前記Vth1>Vth2と設定し、前記過電流抑制不感帯器は、前記振幅、位相偏差(ΔVa〜ΔVc、ΔΦa〜ΔΦc)のいずれかが、前記第1の動作しきい値(Vth1、Φth1)を超えた場合に、前記偏差と同値の過電流抑制不感帯器出力値(ΔVa〜ΔVc、ΔΦa〜ΔΦc)を出力し、前記過電圧抑制不感帯器は、前記振幅、位相偏差(ΔVa〜ΔVc、ΔΦa〜ΔΦc)のいずれかが、前記第2の動作しきい値(Vth2、Φth2)を超えた場合に、過電圧抑制不感帯器出力値(ΔVva〜ΔVvc、ΔΦva〜ΔΦvc)を出力するとともに、この過電圧抑制不感帯器出力値の内の偏差(ΔVva〜ΔVvc)を、前記過電流抑制不感帯器出力の内の偏差(ΔVa〜ΔVc)からそれぞれ減算して補正電圧偏差(ΔVd〜ΔVf)とし、さらに、前記過電圧抑制不感帯器出力値の内の偏差(ΔΦva〜ΔΦvc)を、前記過電流抑制不感帯器出力値の内の偏差(ΔΦa〜ΔΦc)からそれぞれ減算して補正位相偏差(ΔΦd〜ΔΦf)としこの値を正弦波信号に演算し、この正弦波信号と前記補正電圧偏差(ΔVd〜ΔVf)とを乗算器で演算出力の電圧指令補正値(ΔVa*〜ΔVc*)と、前記第2の座標変換器の出力とを加算器で加算して前記電力変換回路の電圧指令値とし、この電圧指令値を入力するパルス幅変調器を介して前記電力変換回路を制御することを特徴とする逆相制御による過電圧抑制制御方式。
A power conversion circuit that is connected to the power system, converts AC power and DC power in both directions, and controls pulse width modulation of the DC voltage, an AC voltage detector that detects the voltage of the power system, and the power conversion An AC current detector that detects a current flowing from the circuit to the power system, a phase detector that detects a reference phase from a detection value of the AC voltage detector, a detection value of the AC current detector, and a phase detector A current component detector that detects an active current component (Id) and a reactive current component (Iq) from the detected reference phase, an active current command value (Id *), the effective current component (Id), and a reactive current command An amplifier for amplifying the deviation between the value (Iq *) and the reactive current component (Iq) and using the output as a voltage command value for the power conversion circuit to feedback control the output AC current of the power conversion circuit; and the AC voltage detection A voltage amplitude phase detector that detects the voltage amplitude and phase of each phase from the detected value of the voltage detector, and the voltage amplitude average value (Vm) of the power system from the voltage amplitude and phase of each phase detected by this voltage amplitude phase detector ) And the phase average value (Φm), and the voltage amplitude average value (Vm) and the phase average value (Φm) are converted by the first coordinate converter to obtain the average voltage components (Vdm, Vqm). The average value calculating means for calculating and the output value of the average value calculating means are added to correct the voltage command value of the power conversion circuit output from the amplifier, and the corrected voltage commands (Vd *, Vq *) are obtained. A second coordinate converter for calculating an AC three-phase voltage value; a detected value of the voltage amplitude phase detector; an amplitude deviation and a phase deviation of the voltage amplitude average value (Vm) and phase average value (Φm) ( ΔVa to ΔVc, ΔΦa to ΔΦc) Means, and the amplitude and phase deviation (ΔVa to ΔVc, ΔΦa to ΔΦc) are input, and the first operating threshold value (Vth1, Φth1) for the amplitude and phase deviation (ΔVa to ΔVc, ΔΦa to ΔΦc) is input. An overcurrent suppression dead zone that suppresses an overcurrent output from the power conversion circuit, and a second operating threshold (Vth2, Φth2) for the deviation, and suppresses an overvoltage output from the power conversion circuit In the overvoltage suppression control system by reverse phase control with an overvoltage suppression dead band
The Vth1> Vth2 is set, and the overcurrent suppression dead zone has any one of the amplitude and phase deviation (ΔVa to ΔVc, ΔΦa to ΔΦc) exceeding the first operating threshold value (Vth1, Φth1). Output overcurrent suppression dead zone output values (ΔVa to ΔVc, ΔΦa to ΔΦc) that are equal to the deviation, and the overvoltage suppression dead zone device outputs the amplitude and phase deviation (ΔVa to ΔVc, ΔΦa to ΔΦc). Output overvoltage suppression dead zone output values (ΔVva to ΔVvc, ΔΦva to ΔΦvc) and any overvoltage suppression dead zone output when any of the above exceeds the second operating threshold (Vth2, Φth2). The deviation (ΔVva to ΔVvc) in the value is subtracted from the deviation (ΔVa to ΔVc) in the output of the overcurrent suppression dead zone device to obtain a corrected voltage deviation (ΔVd to ΔVf), The deviation (ΔΦva to ΔΦvc) of the overvoltage suppression dead band output value is subtracted from the deviation (ΔΦa to ΔΦc) of the overcurrent suppression dead band output value to obtain a corrected phase deviation (ΔΦd to ΔΦf). A value is calculated into a sine wave signal, and the sine wave signal and the correction voltage deviation (ΔVd to ΔVf) are multiplied by a voltage command correction value (ΔVa * to ΔVc *) output by the multiplier and the second coordinate conversion is performed. The output of the converter is added by an adder to obtain a voltage command value for the power conversion circuit, and the power conversion circuit is controlled via a pulse width modulator that inputs the voltage command value. Overvoltage suppression control method.
前記過電圧抑制不感帯器の出力端に、ゲイン要素を設け、前記振幅偏差(ΔVva〜ΔVvc)にゲインを乗じ、前記振幅偏差(ΔVva〜ΔVvc)の補正の度合いを変更することを特徴とする請求項1に記載の逆相制御による過電圧抑制制御方式。 A gain element is provided at an output terminal of the overvoltage suppression dead zone device, and the amplitude deviation (ΔVva to ΔVvc) is multiplied by a gain to change the degree of correction of the amplitude deviation (ΔVva to ΔVvc). The overvoltage suppression control method by reverse phase control of 1. 前記ゲイン要素にリミッタを設けることを特徴とする請求項2に記載の逆相制御による過電圧抑制制御方式。 The overvoltage suppression control method by reverse phase control according to claim 2, wherein a limiter is provided in the gain element.
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