JP2009212387A5 - - Google Patents
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- JP2009212387A5 JP2009212387A5 JP2008055415A JP2008055415A JP2009212387A5 JP 2009212387 A5 JP2009212387 A5 JP 2009212387A5 JP 2008055415 A JP2008055415 A JP 2008055415A JP 2008055415 A JP2008055415 A JP 2008055415A JP 2009212387 A5 JP2009212387 A5 JP 2009212387A5
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- substrate
- semiconductor layer
- semiconductor
- manufacturing
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- 239000004065 semiconductor Substances 0.000 claims 27
- 239000000758 substrate Substances 0.000 claims 26
- 238000004519 manufacturing process Methods 0.000 claims 10
- 238000000034 method Methods 0.000 claims 8
- 150000002500 ions Chemical class 0.000 claims 6
- 238000011282 treatment Methods 0.000 claims 6
- 238000010438 heat treatment Methods 0.000 claims 4
- 238000005530 etching Methods 0.000 claims 2
- 230000001678 irradiating effect Effects 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 1
Claims (10)
前記ボンド基板の一表面からイオンを照射して第1の損傷領域を形成し、
第1のベース基板と前記第1の絶縁層の表面とを接触させて、前記第1のベース基板と前記ボンド基板を貼り合わせ、
第1の加熱処理を施すことにより、前記第1の損傷領域において前記ボンド基板を分離して前記第1のベース基板上に第1の半導体層を形成し、
前記第1の半導体層の表面を平坦化し、
前記第1の半導体層の一表面上に第2の絶縁層を形成し、
前記第1の半導体層の一表面からイオンを照射して第2の損傷領域を形成し、
第2のベース基板と前記第2の絶縁層の表面とを接触させて、前記第2のベース基板と前記第1の半導体層を貼り合わせ、
第2の加熱処理を施すことにより、前記第2の損傷領域において前記第1の半導体層を分離して前記第1のベース基板上に第2の半導体層を形成し、前記第2のベース基板上に第3の半導体層を形成することを特徴とする半導体基板の作製方法。 Forming a first insulating layer on one surface of the bond substrate;
Irradiating ions from one surface of the bond substrate to form a first damaged region;
Bringing the first base substrate and the surface of the first insulating layer into contact with each other, and bonding the first base substrate and the bond substrate;
Performing a first heat treatment to separate the bond substrate in the first damaged region to form a first semiconductor layer on the first base substrate;
Planarizing the surface of the first semiconductor layer;
Forming a second insulating layer on one surface of the first semiconductor layer;
Irradiating ions from one surface of the first semiconductor layer to form a second damaged region;
Bringing the second base substrate and the surface of the second insulating layer into contact with each other, and bonding the second base substrate and the first semiconductor layer together;
By performing the second heat treatment, the first semiconductor layer is separated in the second damaged region to form a second semiconductor layer on the first base substrate, and the second base substrate A method for manufacturing a semiconductor substrate, comprising forming a third semiconductor layer thereon.
前記分離されたボンド基板の表面を平坦化することで、前記ボンド基板を再利用することを特徴とする半導体基板の作製方法。 In claim 1,
Wherein the separated bonded surface of the substrate by flattening method for manufacturing a semiconductor substrate, which comprises reusing the bond substrate.
前記ボンド基板の一表面から照射されるイオンは、H+を主成分として含むことを特徴とする半導体基板の作製方法。 In claim 1 or 2 ,
Ions irradiated from one surface of the bond substrate contain H + as a main component, and a method for manufacturing a semiconductor substrate.
前記第1の半導体層の一表面から照射されるイオンは、H3 +を主成分として含むことを特徴とする半導体基板の作製方法。 In any one of Claims 1 thru | or 3 ,
Ions irradiated from one surface of the first semiconductor layer contain H 3 + as a main component, and a method for manufacturing a semiconductor substrate.
前記第1の半導体層の表面の平坦化、又は前記分離されたボンド基板の表面の平坦化は、エッチング処理、レーザ光の照射処理、加熱処理、及び研磨処理のいずれかを用いて行われることを特徴とする半導体基板の作製方法。 In any one of Claims 1 thru | or 4 ,
The planarization of the surface of the first semiconductor layer or the planarization of the surface of the separated bond substrate is performed using any one of etching treatment, laser light irradiation treatment, heat treatment, and polishing treatment. A manufacturing method of a semiconductor substrate characterized by the above.
前記第2の半導体層の表面を平坦化することを特徴とする半導体基板の作製方法。A method for manufacturing a semiconductor substrate, wherein the surface of the second semiconductor layer is planarized.
前記第3の半導体層の表面を平坦化することを特徴とする半導体基板の作製方法。A method for manufacturing a semiconductor substrate, comprising planarizing a surface of the third semiconductor layer.
前記第2の半導体層の表面の平坦化、又は前記第3の半導体層の表面の平坦化は、エッチング処理、レーザ光の照射処理、加熱処理、及び研磨処理のいずれかを用いて行われることを特徴とする半導体基板の作製方法。The planarization of the surface of the second semiconductor layer or the planarization of the surface of the third semiconductor layer is performed using any one of etching treatment, laser light irradiation treatment, heat treatment, and polishing treatment. A manufacturing method of a semiconductor substrate characterized by the above.
前記第2の半導体層又は前記第3の半導体層を用いて複数の半導体基板を作製することを特徴とする半導体基板の作製方法。 In any one of Claims 1 thru | or 8 ,
A method for manufacturing a semiconductor substrate, wherein a plurality of semiconductor substrates are manufactured using the second semiconductor layer or the third semiconductor layer.
前記イオンはイオン注入装置又はイオンドーピング装置を用いて照射されることを特徴とする半導体基板の作製方法。A method for manufacturing a semiconductor substrate, wherein the ions are irradiated using an ion implantation apparatus or an ion doping apparatus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008055415A JP2009212387A (en) | 2008-03-05 | 2008-03-05 | Method of manufacturing semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008055415A JP2009212387A (en) | 2008-03-05 | 2008-03-05 | Method of manufacturing semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009212387A JP2009212387A (en) | 2009-09-17 |
JP2009212387A5 true JP2009212387A5 (en) | 2011-03-31 |
Family
ID=41185231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008055415A Withdrawn JP2009212387A (en) | 2008-03-05 | 2008-03-05 | Method of manufacturing semiconductor substrate |
Country Status (1)
Country | Link |
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JP (1) | JP2009212387A (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2816445B1 (en) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE |
FR2855909B1 (en) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | PROCESS FOR THE CONCURRENT PRODUCTION OF AT LEAST ONE PAIR OF STRUCTURES COMPRISING AT LEAST ONE USEFUL LAYER REPORTED ON A SUBSTRATE |
JP2006303201A (en) * | 2005-04-21 | 2006-11-02 | Sumco Corp | Process for producing soi substrate |
JP4715470B2 (en) * | 2005-11-28 | 2011-07-06 | 株式会社Sumco | Release wafer reclaim processing method and release wafer regenerated by this method |
US20070281440A1 (en) * | 2006-05-31 | 2007-12-06 | Jeffrey Scott Cites | Producing SOI structure using ion shower |
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2008
- 2008-03-05 JP JP2008055415A patent/JP2009212387A/en not_active Withdrawn
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