JP2009205276A - Watchdog timer control device, watchdog timer control method, program, and cpu system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a watchdog timer control circuit and a watchdog timer control method, which improve efficiency of data transfer. <P>SOLUTION: A watchdog timer control device 20 is characterized by including: a watchdog timer section 3 which performs counting every time a cyclic signal occurs and outputs a signal showing that a CPU 1 is abnormal when the counter value reaches a predetermined counter value; an input means which inputs a request signal which requires control information from the CPU 1; a holding means for holding the control information; an output means which outputs the control information held by the holding means to the CPU 1 when the request signal is input into the input means; and a counter initialization instruction 13 which sets the counter value of the watchdog timer section 3 to a predetermined value when the request signal is input. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a watchdog timer control device, a watchdog timer control method and program, and a CPU system.

  Various functions are incorporated in the CPU as a countermeasure against runaway of the CPU incorporated in an electronic device or the like. In addition, as another method, the microcomputer often has a role as an external function of the CPU. The present invention is based on the latter technique. A watchdog timer is a CPU runaway countermeasure function, and has a function of detecting that the CPU has runaway and resetting the CPU.

  As a countermeasure when the CPU runs away or stops, for example, Patent Document 1 describes a method of efficiently storing information useful for identifying the cause of the CPU running away or stopped. The technique of Patent Document 1 detects a predetermined state that would interfere with the processing of the CPU by a failure monitoring device from the outside of the CPU, and records predetermined signals of the CPU and peripheral circuits in a nonvolatile memory. is there.

  If the set time of the watchdog timer is a constant value, if the set value is long, the runaway time of the CPU will become long and the influence of memory destruction will increase, and if the set value is short, the data transfer processing may not finish in time There is. As a countermeasure against this problem, Patent Document 2 provides means for detecting a difference between a set timer time and a data processing execution time between them, and issues an alarm based on a comparison result between the detection result and a predetermined value. Describes how appropriate measures can be taken.

  In a CPU system that controls a load drive circuit, when the CPU runs away due to an abnormality of an oscillator or the like, the load may fall into a continuous drive state or a continuous energization state. As a countermeasure for preventing this problem, for example, in Patent Document 3, the CPU is initialized and the load is deactivated every time the periodicity of the watchdog clear signal periodically output from the CPU is broken. A method is described for deactivating a load over a period of time.

  In the reset processing of the remote exchange, the reset signal processing from the master station and the reset signal processing of the watchdog timer in the remote station synchronized with the reset signal from the master station overlap, and the time longer than necessary for the reset signal processing of the remote station As a result, there is a problem that the local station cannot accept the instruction from the master station. As a countermeasure for this problem, for example, in Patent Document 4, the watchdog timer is reset by a reset signal from the master station to temporarily stop the operation, and after the reset processing of the remote exchange is completed, the watchdog timer is operated to A method for monitoring a station processor is described.

  In addition, as a countermeasure for preventing the memory contents from being destroyed, Patent Document 5 describes a method of detecting that the CPU has illegally accessed the memory and resetting the CPU.

There is a problem that the program runaway and the occurrence of system abnormality cannot be detected after the reset signal is input to the watchdog timer control circuit and before the timer is started, and the processing routine for the abnormality cannot be executed. As a countermeasure against this problem, for example, in Patent Document 6, the count start operation of the watchdog timer is controlled by data set in the setting unit, and the count of the watchdog timer is performed without adding a new input / output terminal. A method is described that allows a starting point to be selected.
JP 2004-185318 A JP 60-122436 A Japanese Patent Application Laid-Open No. 07-225695 Japanese Patent Application Laid-Open No. 07-250361 JP 11-161548 A JP 04-162150 A

  FIG. 5 is a diagram showing a configuration of a CPU system 100 that uses a watchdog timer control device of related technology. In FIG. 5, the CPU system 100 includes a CPU 101 and a microcomputer 102, which are connected by an internal bus 120. The CPU 101 controls the entire CPU system. The microcomputer 102 includes a watchdog timer unit 103, a temperature monitoring unit 107, and a data storage unit 108.

  The watchdog timer unit 103 is a hardware time measuring device. When the regular counter initial setting instruction 105 from the CPU 101 is not received, the watch dog timer unit 103 resets the CPU 101 to return to normal operation from a runaway or stopped state. return. The counter 104 in the watchdog timer unit 103 is set to an initial value by the microcomputer 102 and is subtracted for each clock signal in the microcomputer 102. When the counter 104 is decremented to 0, the microcomputer 102 outputs a CPU reset signal 106 to the CPU 101 to reset the CPU 101.

  When the CPU 101 is operating normally, the CPU 101 transmits a counter initial setting instruction 105 to the microcomputer 102 at regular time intervals, and when the microcomputer 102 receives the counter initial setting instruction 105, the counter 104 is set to an initial value. Reset it. When operating normally, the counter 104 is not decremented to 0, and the microcomputer 102 does not reset the CPU 101 by outputting the CPU reset signal 106 to the CPU 101.

  If the CPU 101 does not transmit the counter initial setting instruction 105 to the microcomputer 102 even after a certain time has elapsed due to runaway of the CPU 101, the counter 104 is decremented to zero. When the counter 104 reaches 0, the microcomputer 102 outputs a CPU reset signal 106 to reset the CPU 101 and return the CPU 101 to a normal state.

  The temperature monitoring unit 107 is a hardware temperature measuring instrument. In order to monitor the temperature of the system, the CPU 101 periodically transmits a temperature reading command 109 to the temperature monitoring unit 107 and transmits temperature information 110 as a response. The CPU 101 controls the temperature of the CPU system 100 to be within a certain range based on the result of comparison with the temperature information 110 and a determined reference value.

  The data storage unit 108 stores data and programs of the CPU system 100. The CPU 101 transmits a data transfer command and transfer data 111 and receives received data 112 from the data storage unit 108 in order to read / write data from / to the data storage unit 108.

  In FIG. 5, the counter initial setting instruction 105, the temperature reading instruction 109, the temperature information 110, the data transfer instruction, the transfer data 111, and the reception data 112 are all transmitted and received on the internal bus 120.

  In the related art watchdog timer configuration, when the load of data transfer between the CPU 101 and the data storage unit 108 (data transfer command, transfer data 111, and received data 112) increases, the data transfer is irrelevant. Such as a counter initial setting instruction 105, a temperature reading instruction 109, and temperature information 110 may cause a phenomenon that prevents data transfer. In the CPU system 100 that uses the watchdog timer control device, data transfer that must be processed with the highest priority in terms of system performance is hindered by instructions unrelated to data transfer, thereby degrading system performance.

  The present invention has been made in view of the above-described situation, and an object thereof is to provide a watchdog timer control device and a watchdog timer control method that improve the efficiency of data transfer.

In order to achieve the above object, a watchdog timer control device according to the first aspect of the present invention provides:
A watchdog timer circuit that outputs a signal indicating that the predetermined counter value has been reached when the predetermined signal value is counted each time a periodic signal occurs;
Input means for inputting a request signal for requesting control information from the CPU;
Holding means for holding the control information;
Output means for outputting control information held by the holding means to the CPU when the request signal is inputted to the input means;
Reset means for setting a counter value of the watchdog timer circuit to a predetermined value when the request signal is input;
It is characterized by providing.

A watchdog timer control method according to a second aspect of the present invention includes:
A CPU monitoring step of outputting a signal indicating that the predetermined counter value has been reached when the predetermined signal value is counted each time a periodic signal occurs;
An input step for inputting a request signal for requesting control information from the CPU;
An output step of outputting the held control information to the CPU when the request signal is input;
A resetting step of setting a value of a counter for counting the periodic signal to a predetermined value when the request signal is input;
It is characterized by providing.

According to a third aspect of the present invention, there is provided a program for outputting a signal indicating that the predetermined counter value has been reached when the computer counts each time a periodic signal occurs and reaches a predetermined counter value. A dog timer circuit;
Input means for inputting a request signal for requesting control information from the CPU;
Holding means for holding the control information;
An output means for outputting the control information held by the holding means to the CPU when the request signal is input to the input means;
When the request signal is inputted, it functions as a reset means for setting a counter value of the watchdog timer circuit to a predetermined value.

  According to the present invention, the watch dog timer counter initial setting instruction issued from the CPU is not required, and the load on the bus that prevents the data transfer between the CPU and the data storage unit can be reduced. As a result, the data transfer performance of the CPU system can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the present embodiment, a CPU system that uses a watchdog timer control device will be described.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of the configuration of a CPU system that uses the watchdog timer control apparatus according to Embodiment 1 of the present invention. In FIG. 1, a CPU system 10 includes a CPU 1 and a microcomputer 2 and is connected by an internal bus 8. The CPU 1 controls the entire CPU system. The microcomputer 2 includes a watchdog timer unit 3, a temperature monitoring unit 5, and a data storage unit 6. The watch dog timer unit 3 and the temperature monitoring unit 5 of the microcomputer 2 constitute a watch dog timer control device 20.

  The CPU 1 transmits a data transfer command and transfer data 15 to the data storage unit 6 and receives received data 16. Further, in parallel with data transmission / reception, the CPU 1 transmits a temperature reading command 11 to the temperature monitoring unit 5 and receives temperature information 12 at regular time intervals. The CPU 1 controls the temperature of the CPU system 10 to be within a certain range based on the result of comparison with the temperature information 12 and a determined reference value. For example, it is conceivable to increase the number of rotations of the CPU fan, decrease the clock frequency of the CPU system 10, or issue a temperature abnormality warning.

  The temperature monitoring unit 5 includes a hardware temperature measuring instrument. The temperature monitoring unit 5 receives a temperature reading command 11 from the CPU 1 at regular time intervals, and transmits temperature information 12 as a response thereto. Further, when the temperature monitoring unit 5 receives the temperature reading command 11, the temperature monitoring unit 5 commands the counter initial setting command 13 to the counter 4 of the watchdog timer unit 3.

  The watchdog timer unit 3 is a hardware time measuring device, and outputs a counter 0 detection signal 14 when the counter 4 reaches a predetermined value, for example, 0. For example, the counter 0 detection signal 14 is input to the CPU 1 to reset the CPU 1 and restore the normal operation from the runaway or stopped state.

  The counter 4 in the watchdog timer unit 3 is set to an initial value by the counter initial setting instruction 13 of the temperature monitoring unit 5 and is subtracted for each clock signal in the microcomputer 2. When the counter 4 is subtracted to 0, the watchdog timer unit 3 outputs a counter 0 detection signal 14 indicating that the state of the CPU 1 is abnormal (the count value of the counter 4 has become 0). The CPU 1 that has received the counter 0 detection signal 14 resets.

  Data indicating that the watchdog timer reset has been applied to the memory (particularly the non-volatile memory) may be set by the counter 0 detection signal 14, and the abnormal situation may be processed by the initialization processing of the CPU 1. For example, the CPU 1 records information necessary for investigating the cause of the abnormal situation, or transmits a signal indicating that the CPU 1 is abnormal. The counter 0 detection signal 14 may be input to a device other than the CPU 1, for example, a core dump device that saves the stored contents of the main memory (not shown) of the CPU system 10, or another monitoring device. In some cases, a lamp that indicates an abnormality of the CPU system 10 is merely lit.

  The data storage unit 6 stores data and programs of the CPU system 10. In order to read / write data from / to the data storage unit 6, the CPU 1 transmits a data transfer command and transfer data 15 and receives received data 16 from the data storage unit 6.

  The CPU 1 and the microcomputer 2 are connected by an internal bus 8. The temperature read command 11, temperature information 12, data transfer command, transfer data 15 and received data 16 in FIG. 1 are all transmitted and received on the internal bus 8.

  FIG. 2 is a flowchart showing an example of the operation of the watchdog timer control apparatus according to the first embodiment. The counter 4 in the watchdog timer unit 3 subtracts the counter value (step S102) in synchronization with the clock signal of the microcomputer 2 (step S101). When the value of the counter 4 is subtracted to 0 (step S103; YES), the counter 0 detection signal 14 indicating that the CPU 1 is abnormal is output from the watchdog timer unit 3 (step S107). The CPU 1 that has received the counter 0 detection signal 14 performs processing for an abnormal situation.

  If the value of the counter 4 is not subtracted to 0 (step S103; NO), it is determined whether the temperature reading command 11 has been received (step S104). When the temperature reading command 11 is not received (step S104; NO), the next clock signal is waited for. When the temperature reading command 11 is received (step S104; YES), the temperature monitoring unit 5 transmits the temperature information 12 (step S105), and also transmits the counter initial setting command 13, and the watchdog timer unit 3 Counter 4 is initialized (step S106), and the next clock signal is awaited.

  As long as the CPU 1 transmits the temperature reading command 11 before the count value of the counter 4 becomes 0, the microcomputer 2 receives the temperature reading command 11 from the CPU 1 before the value of the counter 4 is decremented to 0. Since the value of the counter 4 is initialized, the counter 0 detection signal 14 is not transmitted.

  Although the case where the count value of the counter 4 is 0 has been described, a signal may be output when the count value is not 0 but a constant count value. Alternatively, the initial value of the counter 4 may be set to a certain value by the counter initial setting instruction 13, the counter 4 may be added in synchronization with the clock signal, and the signal may be output when the predetermined value is reached.

  In the CPU system 10 according to the first embodiment of the present invention, since the temperature read command 11 also serves as a counter reset command, a command for directly controlling the watchdog timer unit 3 from the CPU 1 is not necessary, and the load on the internal bus 8 is reduced. can do. As a result, there is an effect of improving the efficiency of data transfer between the CPU 1 and the data storage unit 6.

(Embodiment 2)
The second embodiment is a case where the fan rotation speed is handled as control information of the CPU system 10. FIG. 3 is a block diagram showing an example of the configuration of a CPU system that uses the watchdog timer control device according to the second embodiment of the present invention. In FIG. 3, unlike the first embodiment, the CPU system 10 includes a fan rotation speed reading unit 7 instead of the temperature monitoring unit 5 of the microcomputer 2. The watchdog timer control device 20 includes a watchdog timer unit 3 and a fan rotation speed reading unit 7 of the microcomputer 2. The fan rotation speed reading unit 7 receives a fan rotation speed reading command 17 from the CPU 1, returns fan rotation speed information 18 to the CPU 1, and transmits a counter initial setting command 13 to the counter 4. Other configurations are the same as those of the first embodiment, but the function of operating the fan rotation speed reading unit 7 is different.

  The fan rotation speed reading unit 7 counts the rotation speed of the CPU fan for adjusting the heat emitted while the CPU system 10 is operating. The fan rotation speed reading unit 7 periodically receives a fan rotation speed reading command 17 from the CPU 1 and transmits fan rotation speed information 18 as a response thereto. Further, when the fan rotation number reading unit 7 receives the fan rotation number reading command 17, the fan rotation number reading unit 7 transmits a counter initial setting command 13 to the counter 4 of the watchdog timer unit 3.

  FIG. 4 is a flowchart showing an example of the operation of the watchdog timer control apparatus according to the second embodiment. The counter 4 in the watchdog timer unit 3 subtracts the counter value (step S102) in synchronization with the clock signal of the microcomputer 2 (step S101). When the value of the counter 4 is subtracted to 0 (step S103; YES), the counter 0 detection signal 14 indicating that the CPU 1 is abnormal is output from the watchdog timer unit 3 (step S107). The CPU 1 that has received the counter 0 detection signal 14 performs an abnormal situation process as in the first embodiment.

  If the value of the counter 4 is not subtracted to 0 (step S103; NO), it is determined whether the fan rotation speed read command 17 has been received (step S108). When the fan rotation speed read command 17 is not received (step S108; NO), the next clock signal is waited for. When the fan rotation speed reading command 17 is received (step S108; YES), the fan rotation speed reading unit 7 transmits the fan rotation speed information 18 (step S109) and also transmits the counter initial setting command 13 Then, the counter 4 of the watchdog timer unit 3 is initialized (step S106), and the next clock signal is awaited.

  When the CPU 1 is normal, the microcomputer 2 receives the fan rotational speed read command 17 from the CPU 1 and initializes the counter value before the counter 4 value is decremented to 0. The signal 14 is not transmitted.

  In the CPU system 10 according to the second embodiment of the present invention, since the fan rotation speed read command 17 also serves as a counter reset command, there is no need for a command to directly control the watchdog timer unit 3 from the CPU 1, and the load on the internal bus 8 Can be reduced. As a result, there is an effect of improving the efficiency of data transfer between the CPU 1 and the data storage unit 6.

  In the first embodiment, the temperature reading command 11 and the counter initial setting command 13 are combined, and in the second embodiment, the fan rotation number reading command 17 and the counter initial setting command 13 are combined to reduce the load on the internal bus 8. did. In the CPU system 10 including both the temperature monitoring unit 5 and the fan rotation speed reading unit 7, one control signal read command serves as the three signals of the temperature reading command 11, the fan rotation speed reading command 17, and the counter initial setting command 13. May be. In that case, both the temperature information 12 and the fan rotational speed information 18 are output to the CPU 1 by one information read command, and at the same time, the counter 4 is reset. In this way, the load on the internal bus 8 can be reduced.

  As described above, by using the watchdog timer control device 20 of the present invention in the CPU system 10, the load on the internal bus 8 can be reduced and data transfer can be efficiently performed between the CPU 1 and the data storage unit 6.

  Other suitable modifications of the present invention include the following configurations.

  In the watchdog timer control device according to the first aspect of the present invention, preferably, the holding means holds temperature information.

  Alternatively or additionally, the holding means may hold the fan rotation speed of the cooling device.

For the watchdog timer control method according to the second aspect of the present invention, preferably,
A step of inputting temperature information from the temperature measuring means;
The output step outputs the temperature information as the control information to the CPU when the request signal is input.

Alternatively, or in addition, a step of inputting fan rotation speed information from the fan device,
The output step may output control information including the fan rotation speed information to the CPU when the request signal is input.

  As described above, according to the present invention, it is not necessary to issue a watch dog timer counter initialization instruction from the CPU, and the load on the internal bus can be reduced. As a result, the performance of data transfer between the CPU and the data storage block can be improved.

  In addition, the hardware configuration and the flowchart described above are merely examples, and can be arbitrarily changed and modified.

  The central part for performing the watchdog timer control process can be realized by using a normal computer system, not by a dedicated system. For example, a computer program for executing the above operation is stored and distributed in a computer-readable recording medium (flexible disk, CD-ROM, DVD-ROM, etc.), and the computer program is installed in the computer. Thus, the watchdog timer control device 20 that executes the above-described processing may be configured. Further, the watchdog timer control device 20 may be configured by storing the computer program in a storage device included in a server device on a communication network such as the Internet and downloading it by a normal computer system.

  Further, when the function of the watchdog timer control device 20 is realized by sharing of an OS (operating system) and an application program, or by cooperation between the OS and the application program, only the application program portion is recorded on a recording medium or a storage device. May be stored.

  It is also possible to superimpose a computer program on a carrier wave and distribute it via a communication network. For example, the computer program may be posted on a bulletin board (BBS, Bulletin Board System) on a communication network, and the computer program distributed via the network. The computer program may be started and executed in the same manner as other application programs under the control of the OS, so that the above-described processing may be executed.

It is a block diagram which shows an example of a structure of CPU system using the watchdog timer control apparatus which concerns on Embodiment 1 of this invention. 4 is a flowchart showing an example of the operation of the watchdog timer control device according to the first embodiment. It is a block diagram which shows an example of a structure of CPU system which uses the watchdog timer control apparatus which concerns on Embodiment 2 of this invention. 6 is a flowchart illustrating an example of operation of the watchdog timer control device according to the second embodiment. It is a block diagram which shows an example of a structure of CPU system using the watchdog timer control apparatus of related technology.

Explanation of symbols

1 CPU
2 Microcomputer 3 Watchdog timer unit 4 Counter 5 Temperature monitoring unit 6 Data storage unit 7 Fan rotation speed reading unit 8 Internal bus 10 CPU system 11 Temperature reading command 12 Temperature information 13 Counter initial setting command 14 Counter 0 detection signal 15 Data transfer Command and transfer data 16 Received data 17 Fan rotation speed read command 18 Fan rotation speed information 20 Watchdog timer control device

Claims (8)

A watchdog timer circuit that outputs a signal indicating that the predetermined counter value has been reached when the predetermined signal value is counted each time a periodic signal occurs;
Input means for inputting a request signal for requesting control information from the CPU;
Holding means for holding the control information;
Output means for outputting control information held by the holding means to the CPU when the request signal is inputted to the input means;
Reset means for setting a counter value of the watchdog timer circuit to a predetermined value when the request signal is input;
A watchdog timer control device comprising:   The watchdog timer control device according to claim 1, wherein the holding unit holds temperature information.   The watchdog timer control device according to claim 1, wherein the holding unit holds the number of fan rotations of the cooling device. A CPU monitoring step of outputting a signal indicating that the predetermined counter value has been reached when the predetermined signal is counted every time a periodic signal occurs;
An input step for inputting a request signal for requesting control information from the CPU;
An output step of outputting the held control information to the CPU when the request signal is input;
A resetting step of setting a value of a counter for counting the periodic signal to a predetermined value when the request signal is input;
A watchdog timer control method comprising: A step of inputting temperature information from the temperature measuring means;
5. The watchdog timer control method according to claim 4, wherein the output step outputs the temperature information as the control information to the CPU when the request signal is input. 6. A step of inputting fan rotational speed information from the fan device;
6. The watchdog timer control method according to claim 4, wherein the output step outputs control information including the fan rotation speed information to the CPU when the request signal is input. Computer
A watchdog timer circuit that outputs a signal indicating that the predetermined counter value has been reached when the predetermined signal value is counted each time a periodic signal occurs;
Input means for inputting a request signal for requesting control information from the CPU;
Holding means for holding the control information;
An output means for outputting the control information held by the holding means to the CPU when the request signal is input to the input means;
A program which functions as a reset means for setting a counter value of the watchdog timer circuit to a predetermined value when the request signal is inputted.   A CPU system comprising the watchdog timer control device according to claim 1.

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