WO2018180664A1 - Vehicle control device - Google Patents

Vehicle control device Download PDF

Info

Publication number
WO2018180664A1
WO2018180664A1 PCT/JP2018/010701 JP2018010701W WO2018180664A1 WO 2018180664 A1 WO2018180664 A1 WO 2018180664A1 JP 2018010701 W JP2018010701 W JP 2018010701W WO 2018180664 A1 WO2018180664 A1 WO 2018180664A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
calculation unit
value
sampling
external information
Prior art date
Application number
PCT/JP2018/010701
Other languages
French (fr)
Japanese (ja)
Inventor
統宙 月舘
祐 石郷岡
一 芹沢
朋仁 蛯名
Original Assignee
日立オートモティブシステムズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Publication of WO2018180664A1 publication Critical patent/WO2018180664A1/en

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present invention relates to inter-core data communication executed via a memory area shared by a multi-core system in an OS (Operating System) of a vehicle control device.
  • OS Operating System
  • an embedded system such as an automobile system has been increasing in the amount of calculation year by year due to its multi-functionality, and the CPU performance required for the embedded system is being improved.
  • an increase in processing amount has been dealt with by increasing the number of cores of a CPU (Central Processing Unit) that is a computing device (multi-core).
  • the field of embedded systems is no exception, and the number of computations such as car navigation and mobile phones is large, and consumer systems with relatively loose real-time restrictions are becoming multi-core.
  • an embedded control system such as an automobile control system becomes more sophisticated and complicated, the amount of calculation is expected to exceed the limit of one single core.
  • Inter-core exclusive control means that if there are resources that multiple cores can access (Read / Write / Execution) at the same time, the resources (eg, memory) are monopolized by the accessing core so that other cores cannot access it. Is a process of locking.
  • Patent Document 1 has a progress information calculation unit and an asynchronous processing unit, and one of a plurality of cores that perform synchronous processing can execute asynchronous processing while suppressing the waiting time for synchronization Is disclosed.
  • the progress information calculation means calculates the progress information up to the start of the synchronous processing of the other processor based on the current PC (program counter) value and the address position.
  • the asynchronous processing means calculates the progress information based on the progress information. Before starting the synchronous process, if the own processor determines that the asynchronous process can be executed, the asynchronous process is executed.
  • an object of the present invention is to provide a program for optimizing the usage efficiency so that the load is not concentrated on some arithmetic units when performing inter-core communication due to periodic interruption.
  • a vehicle control device includes a plurality of calculation units that execute a program, a storage area that is periodically accessed by the plurality of calculation units, and a detection unit that detects external information. Receives the external information detected by the detection unit, and adjusts the processing for the storage area based on the received external information.
  • the processing for the storage area can be changed according to the fluctuating external information. Accordingly, it is possible to suppress contention for a recording area that is a shared resource for a plurality of arithmetic units and to improve the utilization efficiency of the arithmetic units.
  • FIG. 1st calculating part data management table 51 The figure which shows the 1st calculating part data recording table 52.
  • FIG. The figure which shows the 2nd calculating part data management table 61 The figure which shows the 2nd calculating part data recording table 62.
  • FIG. 1st calculating part data management table 51 The figure which shows the 1st calculating part data recording table 52.
  • FIG. The figure which shows the 2nd calculating part data management table 61 The figure which shows the 2nd calculating part data recording table 62.
  • FIG. 1 is a configuration diagram of an engine control unit ECU1 configured by a multi-core system including two arithmetic units according to the present embodiment.
  • the engine control unit ECU1 is mounted on a vehicle and controls various devices such as an engine and a transmission of the vehicle.
  • the engine control unit ECU1 includes a first calculation unit 2 and a second calculation unit 3 as a calculation unit and an external information monitoring unit, a program area 4, a first calculation unit storage area 5, and a second calculation unit storage area 6.
  • the input / output circuit 7 is provided.
  • the input / output circuit 7 is connected to a sensor 8 as a detection unit and an actuator 9.
  • the sensor 8 detects various states of the vehicle and is input as detection signals into the engine control unit ECU1 via the input / output circuit 7.
  • the actuator 9 operates in response to an output signal output from the engine control unit ECU1 via the input / output circuit 7.
  • the first calculation unit 2 and the second calculation unit 3 are a processor core (CPU: Central Processing Unit) that executes a program stored in the program area 4.
  • the first calculation unit 2 and the second calculation unit 3 can execute the program stored in the program area 4 in parallel.
  • the first calculation unit 2 and the second calculation unit 3 also function as an external information monitoring unit that monitors external information based on the detection signal output from the sensor 8.
  • the multi-core system defined in the present embodiment refers to a computer system having a plurality of processor cores. Therefore, for example, a system configured by two or more processor cores in one package or a system configured by a plurality of packages having processor cores may be used.
  • the program area 4 stores a first calculation unit software control unit 41, a first calculation unit timer unit 42, a first calculation unit interrupt unit 43, and a second calculation unit software control unit 44. Further, the program area 4 includes a second calculation unit timer unit 45, a second calculation unit cycle processing unit 46, a second calculation unit sampling adjustment unit 47, a second calculation unit cycle adjustment unit 48, and a second calculation unit. The offset adjustment unit 49 and the second calculation unit sampling unit 40 are stored.
  • the first calculation unit storage area 5 includes a first calculation unit data management table 51 in FIG. 2, which will be described later, a first calculation unit data recording table 52 in FIG. 3, and a first calculation unit interrupt recording table 53 in FIG. Store.
  • the second arithmetic unit storage area 6 includes a second arithmetic unit data management table 61 shown in FIG. 5, which will be described later, a second arithmetic unit data recording table 62 shown in FIG. 6, and a second arithmetic unit sampling recording table 63 shown in FIG. 8, the second calculation unit sampling adjustment table 64 in FIG. 8, the second calculation unit sampling period adjustment table 65 in FIG. 9, and the second calculation unit offset adjustment table 66 in FIG.
  • the engine control ECU 1 may include, for example, a non-volatile memory (backup RAM) for storing data, a shared storage area for each arithmetic unit to access, different sensors, and the like.
  • backup RAM non-volatile memory
  • the tables 51 to 53 stored in the first calculation unit storage area 5 and accessed (read and written) from the first calculation unit 2 and the second calculation unit 3 will be described below.
  • FIG. 2 is a diagram illustrating an example of the first arithmetic unit data management table 51.
  • the first arithmetic unit data management table 51 includes a name field 510 and a set value field 511.
  • the name field 510 is a name of a target managed by the first arithmetic unit data management table 51.
  • the first arithmetic unit timer unit 42 includes a first arithmetic unit timer counter maximum value which is the maximum value of the software timer operated by the first arithmetic unit timer unit 42.
  • the setting value field 511 represents a setting value to be managed by the first arithmetic unit data management table 51.
  • FIG. 3 is a diagram illustrating an example of the first calculation unit data recording table 52.
  • the first calculation unit data recording table 52 includes a name field 520 and a value field 521.
  • the name field 520 is a name of a target managed by the first calculation unit data recording table 52.
  • the first arithmetic unit timer counter value which is the counter value of the software timer that is the reference for the operation of the first arithmetic unit 2, and the table that the first arithmetic unit 2 accesses (reads and writes) at the time of interruption are stored. It consists of the latest value storage destination ID indicating the destination ID.
  • the value field 521 stores a value to be managed by the first calculation unit data recording table 52.
  • FIG. 4 is a diagram showing an example of the first arithmetic unit interrupt record table 53. As shown in FIG.
  • the first arithmetic unit interrupt record table 53 includes an ID field 530, a timer counter value field 531, a sampling flag field 532, and a data value field 533.
  • the ID field 530 is an ID for managing an object managed by the first arithmetic unit interrupt recording table 53.
  • the timer counter value field 531 is a timer counter value at a timing when the first arithmetic unit interrupt unit 43 accesses the first arithmetic unit interrupt record table 53.
  • the sampling flag field 532 is a flag indicating the presence / absence of access from the second arithmetic unit 3.
  • the sampling flag is expressed by binary values of “0” and “1”, “0” indicates that the second arithmetic unit is accessed, and “1” is that the second arithmetic unit is not accessed. It shows that.
  • the configuration of the sampling flag indicating the access from the second arithmetic unit 3 is not limited to this.
  • the data value field 533 is a field for managing the data value of the interrupt managed by the first arithmetic unit interrupt recording table 53.
  • FIG. 5 is a diagram illustrating an example of the second arithmetic unit data management table 61.
  • the second arithmetic unit data management table 61 includes a name field 610 and a set value field 611.
  • the name field 610 stores the name of data managed by the second arithmetic unit data recording table 61.
  • the second arithmetic unit timer counter maximum value which is the maximum value of the timer updated by the second arithmetic unit timer unit 45, and the sampling timing at which the second arithmetic unit 2 accesses the first arithmetic unit storage area 5 are used.
  • the set value field 611 stores a set value of data managed by the second arithmetic unit data recording table 61.
  • FIG. 6 is a diagram showing an example of the second arithmetic unit data recording table 62. As shown in FIG. 6
  • the second arithmetic unit data recording table 62 includes a name field 620 and a value field 621.
  • the name field 620 stores the name of data managed by the second arithmetic unit data recording table 62.
  • the second arithmetic unit timer counter value which is a counter of the software timer accessed by the second arithmetic unit timer unit 45
  • the sampling which is the cycle at which the second arithmetic unit 3 accesses the first arithmetic unit storage area 5
  • the value field 621 stores the value of data managed by the second arithmetic unit data recording table 62.
  • FIG. 7 is a diagram showing an example of the second arithmetic unit sampling record table 63. As shown in FIG.
  • the second arithmetic unit sampling recording table 63 includes an ID field 630, a timer counter value field 631, a sampling timer counter value field 632, and a data value field 633.
  • the ID field 60300 stores an ID of an area in which data managed by the second arithmetic unit sampling recording table 63 is stored.
  • the timer counter value field 631 stores a timer counter value accessed by the first arithmetic unit interrupt unit 43 to the first arithmetic unit storage area 5.
  • the sampling timer counter value field 632 stores a timer counter value when the second arithmetic unit sampling unit 40 accesses the first arithmetic unit storage area 5.
  • the data value field 633 stores the value of sampling data managed by the second arithmetic unit sampling record table 63.
  • FIG. 8 shows the second arithmetic unit sampling adjustment table 64.
  • the second arithmetic unit sampling adjustment table 64 includes an ID field 640, an interrupt period field 641, an interrupt tendency field 642, an offset difference field 643, and an offset difference tendency field 644.
  • the ID field 640 stores an ID of an area in which data managed by the second arithmetic unit sampling adjustment table 64 is stored.
  • the interrupt cycle field 641 stores an interrupt cycle that is a result of calculating the frequency with which the second calculation unit 3 accesses the first calculation unit storage area 5.
  • the interrupt cycle is, for example, the time elapsed since the previous access, the average time for accessing the first arithmetic unit storage area 5, or the like.
  • the interrupt tendency field 642 is a rate of change per unit time of the interrupt cycle described above.
  • the rate of change per unit time of the interrupt cycle is, for example, the difference between the latest interrupt cycle and the previous interrupt cycle, or the rate of change of the interrupt cycle within a certain period from the latest interrupt cycle.
  • the offset difference field 643 stores the difference between the timer counter value managed by the second arithmetic unit sampling recording table 63 and the sampling timer counter value as an offset difference.
  • the offset difference tendency field 644 is a change rate per unit time of the offset difference.
  • the change rate per unit time of the offset difference is, for example, the difference between the latest offset difference and the previous offset difference, or the change rate of the offset difference within a certain time.
  • FIG. 9 shows the second arithmetic unit sampling cycle adjustment table 65.
  • the second calculation unit sampling cycle adjustment table 65 includes an interrupt tendency determination threshold value 650 field and a sampling cycle correction value field 651.
  • the interrupt tendency determination threshold value 650 field stores a threshold value for determining an interrupt tendency value managed by the second arithmetic unit sampling adjustment table 64.
  • the sampling period correction value tendency field 651 stores a correction value corresponding to the interrupt tendency value described above. For example, if the interrupt tendency is 0 or more and the absolute value of the sampling tendency is less than a certain value ( ⁇ in the figure), the correction value is 0, and if the correction value is more than a certain value ( ⁇ in the figure), it is specified. The value is used as a correction value.
  • the specified value is used as a correction value.
  • the correction value is a fixed value, but is not limited thereto.
  • the correction value may be, for example, a value that changes according to the interrupt tendency value.
  • FIG. 10 shows the second calculation unit offset adjustment table 66.
  • the second calculation unit offset adjustment table 66 includes an offset tendency determination threshold field 660 and an offset field 661.
  • the offset tendency determination threshold field 660 stores a threshold for determining an offset difference tendency managed by the second arithmetic unit sampling adjustment table 64.
  • the offset field 661 stores an offset corresponding to the above-described offset difference tendency value. For example, if the offset difference tendency is greater than or equal to 0 and less than a certain value ( ⁇ in the figure), the specified value is 0, and if it is greater than or equal to a certain value ( ⁇ in the figure), the specified value is offset. .
  • the designated value is set as an offset, and if it is equal to or larger than the certain value ( ⁇ ), it is similarly designated.
  • the value is an offset.
  • the offset value is a fixed value, but is not limited thereto.
  • the offset value may be, for example, a value that changes according to the offset difference tendency value.
  • the above tables 51 to 53 and 61 to 66 are stored in the first calculation unit data storage area 5 and the second calculation unit storage area 6 of the engine control ECU 1 of the present embodiment.
  • the types and number of objects managed by the tables 51 to 53 and 61 to 66 and the management method are not limited to this.
  • each of the tables 51 to 53 and 61 to 66 can be accessed (read and written) at any timing from the first arithmetic unit storage area 5 and the second arithmetic unit storage area 6.
  • FIG. 11 is an operation flow of the first calculation unit software control unit 41 of the first calculation unit 2.
  • steps 410 to 412 in FIG. 11 will be described.
  • the first calculation unit software control unit 41 initializes the first calculation unit data recording table 52 and the first calculation unit interrupt recording table 53 managed in the first calculation unit storage area 5.
  • the first calculation unit software control 41 calls a first calculation unit timer unit 42 described later with reference to FIG. Thereby, the counter value of the timer which the 1st calculating part 2 refers is updated.
  • Step 412 The first calculation unit software control unit 41 determines whether or not the end condition is satisfied. If the end condition is satisfied, the first operation unit software control unit 41 ends the processing. If not satisfied, the process returns to step 411.
  • FIG. 12 is an operation flow of the first arithmetic unit timer unit 42. Hereinafter, steps 420 to 422 in FIG. 12 will be described.
  • the first arithmetic unit timer unit 42 acquires the first arithmetic unit timer counter value from the first arithmetic unit data recording table 52. The acquired value is compared with the maximum value of the first arithmetic unit timer counter managed by the data management table 51. If the acquired value is equal to or greater than the maximum timer counter, the process proceeds to step 421. Otherwise, the process proceeds to step 422.
  • the first arithmetic unit timer unit 42 assigns 0 to the first arithmetic unit timer counter value of the first arithmetic unit data recording table 52 and ends the process.
  • the first arithmetic unit timer unit 42 writes a value obtained by adding 1 to the first arithmetic unit timer counter value of the data recording table 52 and ends the process.
  • FIG. 13 is an operation flow of the first arithmetic unit interrupt unit 43. The steps 430 to 432 in FIG. 13 will be described below.
  • the first arithmetic unit interrupt unit 43 executes interrupt processing.
  • the first calculation unit interrupt unit 43 refers to the first calculation unit data recording table 52 and acquires the first calculation unit timer counter value and the latest value storage ID.
  • the first calculation unit interrupt unit 43 includes a timer counter value field of the first calculation unit interrupt recording table 53 indicated by the same ID as the acquired latest value storage ID, a timer counter value acquired as the value of the data value field, and an interrupt process. Stores execution results.
  • the first arithmetic unit interrupt unit 43 updates the latest value storage ID managed by the first arithmetic unit data recording table 52 and the sampling flag of the first arithmetic unit interrupt recording table 53, and ends the processing.
  • FIG. 14 is an operation flow of the second arithmetic unit software control unit 44. Hereinafter, each step of FIG. 14 will be described.
  • the second calculation unit software control unit 404 initializes the second calculation unit data recording table 62 and the second calculation unit sampling recording table 63 managed in the second calculation unit storage area 6.
  • the second calculation unit software control unit 44 calls a second calculation unit timer unit 45 described later with reference to FIG. Thereby, the counter value of the timer which the 2nd calculating part 3 refers is updated.
  • the second calculation unit software control unit 44 calls a second calculation unit cycle processing unit 46 described later with reference to FIG. Thereby, the 2nd calculating part 3 performs a process with a fixed period.
  • Step 443 The second arithmetic unit software control unit 44 determines whether or not the end condition is satisfied. If the end condition is satisfied, the second operation unit software control unit 44 ends the processing. If not satisfied, the process returns to step 441.
  • FIG. 15 is an operation flow of the second arithmetic unit timer unit 45. Hereinafter, each step of FIG. 15 will be described.
  • the second arithmetic unit timer unit 45 acquires the second arithmetic unit timer counter value from the second arithmetic unit data recording table 62.
  • the obtained timer counter value is compared with the second arithmetic unit timer counter maximum value managed by the data management table 61. If the timer counter value is equal to or greater than the maximum timer counter value, the process proceeds to step 451. Otherwise, the process proceeds to step 452.
  • the second arithmetic unit timer unit 45 assigns 0 to the second arithmetic unit timer counter value of the second arithmetic unit data recording table 62 and ends the process.
  • the second arithmetic unit timer unit 45 writes a value obtained by adding 1 to the second arithmetic unit timer counter value of the second arithmetic unit data recording table 62 and ends the process.
  • FIG. 16 is an operation flow of the second calculation unit cycle processing unit 46.
  • Step 460 The second calculation unit cycle processing unit 46 calls a second calculation unit sampling adjustment unit 47 described later with reference to FIG. Thereby, the second calculation unit cycle processing unit 46 can determine the sampling cycle and the offset.
  • the 2nd calculating part period process part 46 calls the 2nd calculating part sampling part 40 demonstrated in below-mentioned FIG. Thereby, the second calculation unit cycle processing unit 46 can acquire the latest value of the data stored in the first calculation unit storage area 5.
  • FIG. 17 is an operation flow of the second arithmetic unit sampling adjustment unit 47. Hereinafter, each step of FIG. 17 will be described.
  • the second calculation unit sampling adjustment unit compares the second calculation unit timer counter value stored in the second calculation unit data recording table 62 with the sampling adjustment timing managed by the second calculation unit data management table 61. If the second arithmetic unit timer counter value is divisible by the second arithmetic unit sampling adjustment timing, the process proceeds to step 471, and otherwise, the process ends.
  • the second calculation unit sampling adjustment unit 47 calls a second calculation unit cycle adjustment unit 48 of FIG. Thereby, the second calculation unit sampling adjustment unit 47 adjusts the sampling period for acquiring the data stored in the first calculation unit storage area 5.
  • the second calculation unit sampling adjustment unit 47 calls a second calculation unit offset adjustment unit 49 of FIG. Thereby, the second calculation unit sampling adjustment unit 47 adjusts the offset of the sampling period for acquiring the data stored in the first calculation unit storage area 5.
  • FIG. 18 is an operation flow of the second calculation unit cycle adjustment unit 48. Hereinafter, each step of FIG. 18 will be described.
  • the second calculation unit cycle adjustment unit 48 refers to the timer counter value field 631 managed by the second calculation unit sampling record table 63, and calculates a cycle in which the first calculation unit 2 updates the first calculation unit storage area 5. .
  • the second calculation unit cycle adjustment unit 48 records the calculation result in the interrupt cycle field 641 of the second calculation unit sampling adjustment table 64.
  • the storage destination is the latest value storage destination ID stored in the name field 620 of the second arithmetic unit data recording table 62.
  • the interrupt cycle refers to a time interval at which the first calculation unit 2 updates the first calculation unit interrupt recording table 53 per unit time.
  • the interrupt period is calculated by dividing the value obtained by integrating the timer counter values managed by the second calculation unit sampling recording table 63 by the total number of IDs managed by the second calculation unit sampling recording table 63.
  • the calculation method is not limited to this.
  • the calculation method is a timer for a certain period from the latest value of the timer counter value. An average value of the counter values may be used.
  • the second calculation unit cycle adjustment unit 408 calculates the tendency of an interrupt in which the first calculation unit 2 updates data from the interrupt cycle field 641 of the second calculation unit sampling adjustment table 604. At this time, as the storage destination, the calculation result is recorded in the latest value storage destination ID stored in the name field 60200 of the second arithmetic unit data recording table 602.
  • the interrupt tendency is the rate of change per unit time of the interrupt cycle described above.
  • the interrupt tendency is, for example, the difference between the latest interrupt cycle and the previous interrupt cycle, or the rate of change of the interrupt cycle within a certain period from the latest interrupt cycle.
  • the second calculation unit cycle adjustment unit 48 compares the absolute value of the interrupt tendency described above with its sign and the second calculation unit sampling cycle adjustment table 65 to obtain a sampling cycle correction value.
  • the second calculation unit cycle adjustment unit 48 records the value obtained by adding the sampling cycle correction value to the update cycle as the sampling cycle in the second calculation unit data recording table 62, and ends the process.
  • FIG. 19 is an operation flow of the second calculation unit offset adjustment unit 49. Hereinafter, each step of FIG. 19 will be described.
  • the second calculation unit offset adjustment unit 49 calculates an offset difference based on the timer counter value 631 and the sampling timer counter value 632 of the second calculation unit sampling recording table 63.
  • the second calculation unit offset adjustment unit 49 records the calculated offset difference in the offset difference field 643 of the second calculation unit sampling adjustment table 64.
  • the second calculation unit offset adjustment unit 49 records the result in the latest value storage destination ID stored in the name field 620 of the second calculation unit data recording table 62.
  • the second calculation unit offset adjustment unit 49 calculates an offset difference tendency from the offset difference of the second calculation unit sampling adjustment table 64 and records the result in the offset difference tendency 644 field of the second calculation unit sampling adjustment table 64. At this time, the result is recorded in the latest value storage destination ID stored in the name field 620 of the second arithmetic unit data recording table 62.
  • the offset tendency is a change rate per unit time of the offset difference described above.
  • the offset tendency is, for example, the difference between the latest offset difference and the previous offset difference, or the change rate of the offset difference within a certain period from the latest offset difference.
  • the second calculation unit offset adjustment unit 49 calculates an offset based on the calculated absolute value of the offset difference tendency, its sign, and the second calculation unit offset adjustment table 66, and stores it in the second calculation unit data recording table 62. Record as an offset and end the process.
  • FIG. 20 is an operation flow of the second arithmetic unit sampling unit 40. Hereinafter, each step of FIG. 20 will be described.
  • the second calculation unit sampling unit 40 acquires a sampling period and an offset based on the second calculation unit data recording table 62.
  • the second calculation unit sampling unit 40 determines whether it is a sampling timing based on the second calculation unit timer counter value and the offset acquired from the second calculation unit data recording table 62.
  • the second arithmetic unit sampling unit 40 proceeds to step 402 if it is a sampling timing, and ends otherwise.
  • it is determined whether or not the value obtained by adding the offset to the second arithmetic unit timer counter value is divisible by the sampling period stored in the second arithmetic unit data recording table 62. To do.
  • the second calculation unit sampling unit 40 acquires the latest value of the first calculation unit interrupt recording table 53 indicated by the latest value storage destination ID of the first calculation unit data recording table 52. After acquiring the latest value, the second calculation unit sampling unit 40 updates the value of the second calculation unit sampling record table 63 indicated by the latest value storage ID held in the second calculation unit data recording table 62. After the update, the latest value storage ID stored in the second arithmetic unit data recording table 63 is updated, and the process is terminated.
  • the plurality of calculation units 2 and 3 that execute the program receive the external information detected by the sensor 8 and adjust the processing for the storage area 5 based on the received external information.
  • the process for the storage area 5 can be changed following the fluctuating external information, and the concentration of the load on any one of the plurality of calculation units 2 and 3 can be suppressed. Accordingly, it is possible to suppress contention on the recording area 5 serving as a resource shared between two different calculation units 2 and 3 and to improve the utilization efficiency of the calculation units 2 and 3.
  • the external information is the writing frequency to the recording area 5, even when the writing frequency to the recording area 5 is high, it is possible to reduce the load concentrated on any one of the plurality of calculation units 2 and 3. .
  • the plurality of calculation units 2 and 3 adjust the processing cycle for the storage area 5 based on the external information, it is easy to perform processing that follows the fluctuating external information simply by adjusting the processing cycle. Can be changed.
  • the plurality of calculation units 2 and 3 adjust the cycle of the process of reading the external information from the recording area 5 based on the external information, the adjustment of the update cycle of the recording area 5 makes it possible to change the external information to fluctuate. It is possible to easily change the process to follow.
  • the plurality of calculation units 2 and 3 adjust the phase of the cycle based on the external information, the adjustment range of processing to be executed is widened.
  • the plurality of calculation units 2 and 3 calculate the time change rate of the external information, and adjust the processing for the storage area 5 based on the calculated time change rate of the external information, so that future external information is predicted. It is possible to improve the reliability of the processing to be executed.

Abstract

The purpose of the present invention is to optimize efficiency during inter-core communication arising from cyclic interrupts by ensuring that load is not being focused on just some of the computation units. Provided is a vehicle control device comprising: a plurality of computation units 2, 3 for executing programs; a storage region 5 which the plurality of computation units 2, 3 cyclically access; and a sensor 8 for detecting external information. The plurality of computation units 2, 3 receive the external information detected by the sensor 8 and adjust a process involving the storage region on the basis of the external information received. The external information is the frequency of writes to a recording region 4.

Description

車両制御装置Vehicle control device
　本発明は、車両制御装置のＯＳ(オペレーティングシステム)において、マルチコアシステムで共有されるメモリ領域を介して実行されるコア間データ通信に関するものである。 The present invention relates to inter-core data communication executed via a memory area shared by a multi-core system in an OS (Operating System) of a vehicle control device.
　近年、例えば、自動車システム等の組込みシステムは、多機能化により、演算量が年々増加しており、組込みシステムに求められるＣＰＵの性能は、向上する一方である。パソコンの分野では、このような処理量の増加に対して、演算装置であるＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）のコア数を増やすこと(マルチコア化)によって対応してきた。組込みシステムの分野も例外ではなく、カーナビや携帯電話といった演算量が多く、リアルタイム性の制約が比較的緩いコンシューマ系では、マルチコア化が進んでいる。例えば、自動車制御システム等の組み込み制御システムが、高度化および複雑化するのに伴い、これらの演算量が1シングルコアの限界を超えることが予想されるため、マルチコアの採用が検討されている。 In recent years, for example, an embedded system such as an automobile system has been increasing in the amount of calculation year by year due to its multi-functionality, and the CPU performance required for the embedded system is being improved. In the field of personal computers, such an increase in processing amount has been dealt with by increasing the number of cores of a CPU (Central Processing Unit) that is a computing device (multi-core). The field of embedded systems is no exception, and the number of computations such as car navigation and mobile phones is large, and consumer systems with relatively loose real-time restrictions are becoming multi-core. For example, as an embedded control system such as an automobile control system becomes more sophisticated and complicated, the amount of calculation is expected to exceed the limit of one single core.
　一般的に、複数のコアが連携してアプリケーションを処理するシステムでは、コアをまたいで情報を処理するため、データの一貫性を担保する必要がある。しかしながら、マルチコアシステムは、各コアが並列で動作するため、排他制御が必要となり、オーバーヘッドの増加が課題となる。コア間排他制御とは、複数のコアが同時にアクセス（Ｒｅａｄ/Ｗｒｉｔｅ/Ｅｘｅｃｕｔｉｏｎ）できるリソースがある場合、アクセス中のコアにリソース(例、メモリ)を独占させ、他のコアがアクセスできないようにリソースをロックする処理である。 Generally, in a system in which multiple cores cooperate to process an application, it is necessary to ensure data consistency because information is processed across cores. However, in a multi-core system, since each core operates in parallel, exclusive control is necessary, and an increase in overhead becomes a problem. Inter-core exclusive control means that if there are resources that multiple cores can access (Read / Write / Execution) at the same time, the resources (eg, memory) are monopolized by the accessing core so that other cores cannot access it. Is a process of locking.
　下記特許文献１には、進捗情報算出手段と、非同期処理手段とを有しており、同期処理を行う複数のコアの一方が、同期待ちの時間を抑制して非同期処理を実行可能なマルチプロセッサが開示されている。進捗情報算出手段は、現在ＰＣ(プログラムカウンタ)値と、アドレス位置とに基づいて、他のプロセッサの同期処理開始までの進捗情報を算出する非同期処理手段は、進捗情報に基づき、他のプロセッサが同期処理を開始する前に、自プロセッサが非同期処理を実行可能であると判定した場合に、非同期処理を実行する。 The following Patent Document 1 has a progress information calculation unit and an asynchronous processing unit, and one of a plurality of cores that perform synchronous processing can execute asynchronous processing while suppressing the waiting time for synchronization Is disclosed. The progress information calculation means calculates the progress information up to the start of the synchronous processing of the other processor based on the current PC (program counter) value and the address position. The asynchronous processing means calculates the progress information based on the progress information. Before starting the synchronous process, if the own processor determines that the asynchronous process can be executed, the asynchronous process is executed.
特開２０１４-１９１６５５号公報JP 2014-191655 A
　複数のＣＰＵで構成されるマルチコアアーキテクチャにおいて、コアを跨いでデータを入手するには、該当データまたは更新フラグが格納された領域を周期的に監視する必要がある。ソフトウェアの更新タイミングが、車両状態に依存して変動する場合(ｅｘ.エンジン、インバータ)、周期的に監視する手法では、サンプリング周期は、できるだけ短い周期に設定する必要があるため、高負荷となる。 In a multi-core architecture composed of a plurality of CPUs, in order to obtain data across cores, it is necessary to periodically monitor the area where the corresponding data or update flag is stored. When the software update timing fluctuates depending on the vehicle condition (ex. Engine, inverter), the periodic monitoring method requires a sampling cycle to be set as short as possible, resulting in high load. .
　よって、本発明は、周期的な割り込み起因のコア間通信を行っているときに、一部の演算部に負荷が集中しないようにして利用効率を最適化するためのプログラムを提供することを目的とする。 Therefore, an object of the present invention is to provide a program for optimizing the usage efficiency so that the load is not concentrated on some arithmetic units when performing inter-core communication due to periodic interruption. And
　本発明に係わる車両制御装置は、プログラムを実行する複数の演算部と、前記複数の演算部が周期的にアクセスする記憶領域と、外部情報を検出する検出部とを備え、前記複数の演算部は、前記検出部が検出した前記外部情報を受信し、当該受信した前記外部情報に基づいて、前記記憶領域に対する処理を調整する。 A vehicle control device according to the present invention includes a plurality of calculation units that execute a program, a storage area that is periodically accessed by the plurality of calculation units, and a detection unit that detects external information. Receives the external information detected by the detection unit, and adjusts the processing for the storage area based on the received external information.
　本発明に関わる車両制御装置によれば、変動する外部情報に応じて、記憶領域に対する処理を変更することができる。従って、複数の演算部に対して共有資源となる記録領域への競合を抑制し、演算部の利用効率を向上することができる。 According to the vehicle control apparatus related to the present invention, the processing for the storage area can be changed according to the fluctuating external information. Accordingly, it is possible to suppress contention for a recording area that is a shared resource for a plurality of arithmetic units and to improve the utilization efficiency of the arithmetic units.
エンジン制御装置ＥＣＵ１の構成図。The block diagram of engine control apparatus ECU1. 第１演算部データ管理テーブル５１を示す図。The figure which shows the 1st calculating part data management table 51. FIG. 第１演算部データ記録テーブル５２を示す図。The figure which shows the 1st calculating part data recording table 52. FIG. 第１演算部割り込み記録テーブル５３を示す図。The figure which shows the 1st calculating part interruption recording table 53. FIG. 第２演算部データ管理テーブル６１を示す図。The figure which shows the 2nd calculating part data management table 61. FIG. 第２演算部データ記録テーブル６２を示す図。The figure which shows the 2nd calculating part data recording table 62. FIG. 第２演算部サンプリング記録テーブル６３を示す図。The figure which shows the 2nd calculating part sampling recording table 63. FIG. 第２演算部サンプリング調整テーブル６４を示す図。The figure which shows the 2nd calculating part sampling adjustment table 64. FIG. 第２演算部サンプリング周期調整テーブル６５を示す図。The figure which shows the 2nd calculating part sampling period adjustment table 65. FIG. 第２演算部オフセット調整テーブル６６を示す図。The figure which shows the 2nd calculating part offset adjustment table 66. FIG. 第１演算部ソフトウェア制御部４１の動作フローを示す図。The figure which shows the operation | movement flow of the 1st calculating part software control part 41. FIG. 第１演算部タイマ部４２の動作フローを示す図。The figure which shows the operation | movement flow of the 1st calculating part timer part 42. FIG. 第１演算部割り込み部４３の動作フローを示す図。The figure which shows the operation | movement flow of the 1st calculating part interruption part 43. FIG. 第２演算部ソフトウェア制御部４４の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part software control part 44. FIG. 第２演算部タイマ部４５の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part timer part 45. FIG. 第２演算部周期処理部４６の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part period process part. 第２演算部サンプリング調整部４７の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part sampling adjustment part 47. FIG. 第２演算部周期調整部４８の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part period adjustment part 48. FIG. 第２演算部オフセット調整部４９の動作フローを示す図。The figure which shows the operation | movement flow of the 2nd calculating part offset adjustment part 49. FIG. 第２演算部サンプリング部４０の動作フローを示す図The figure which shows the operation | movement flow of the 2nd calculating part sampling part 40.
　図１は、本実施例に係る２つの演算部からなるマルチコアシステムで構成されるエンジン制御装置ＥＣＵ１の構成図である。 FIG. 1 is a configuration diagram of an engine control unit ECU1 configured by a multi-core system including two arithmetic units according to the present embodiment.
　エンジン制御装置ＥＣＵ１は、車両に搭載され、当該車両のエンジン、変速機等の各種機器を制御する。エンジン制御装置ＥＣＵ１は、演算部および外部情報監視部としての第１演算部２および第２演算部３と、プログラム領域４と、第１演算部記憶領域５と、第２演算部記憶領域６と、入出力回路７とを備える。入出力回路７は、検出部としてのセンサ８と、アクチュエータ９とに、相互に接続されている。センサ８は、車両の各種状態を検出し、検出信号として入出力回路７を介してエンジン制御装置ＥＣＵ１内に入力される。
アクチュエータ９は、エンジン制御装置ＥＣＵ１が入出力回路７を介して出力する出力信号に応じて動作する。 The engine control unit ECU1 is mounted on a vehicle and controls various devices such as an engine and a transmission of the vehicle. The engine control unit ECU1 includes a first calculation unit 2 and a second calculation unit 3 as a calculation unit and an external information monitoring unit, a program area 4, a first calculation unit storage area 5, and a second calculation unit storage area 6. The input / output circuit 7 is provided. The input / output circuit 7 is connected to a sensor 8 as a detection unit and an actuator 9. The sensor 8 detects various states of the vehicle and is input as detection signals into the engine control unit ECU1 via the input / output circuit 7.
The actuator 9 operates in response to an output signal output from the engine control unit ECU1 via the input / output circuit 7.
　第１演算部２と、第２演算部３とは、プログラム領域４が格納しているプログラムを実行するプロセッサコア（ＣＰＵ：Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）である。第１演算部２と、第２演算部３とは、プログラム領域４が格納しているプログラムの実行を並列に行うことができる。さらに、第１演算部２と、第２演算部３とは、センサ８から出力される検出信号に基づいて、外部情報を監視する外部情報監視部としても機能する。ここで、マルチコアシステムの演算装置は、２つとしているが、これに限らない。
  本実施例で定義するマルチコアシステムとは、複数のプロセッサコアを有するコンピュータシステムのことを指す。したがって、例えば、１つのパッケージ内に２つ以上の複数のプロセッサコアで構成されるシステムや、プロセッサコアを有する複数のパッケージで構成されたシステムでもよい。 The first calculation unit 2 and the second calculation unit 3 are a processor core (CPU: Central Processing Unit) that executes a program stored in the program area 4. The first calculation unit 2 and the second calculation unit 3 can execute the program stored in the program area 4 in parallel. Furthermore, the first calculation unit 2 and the second calculation unit 3 also function as an external information monitoring unit that monitors external information based on the detection signal output from the sensor 8. Here, although there are two arithmetic devices of the multi-core system, the present invention is not limited to this.
The multi-core system defined in the present embodiment refers to a computer system having a plurality of processor cores. Therefore, for example, a system configured by two or more processor cores in one package or a system configured by a plurality of packages having processor cores may be used.
　プログラム領域４は、第１演算部ソフトウェア制御部４１と、第１演算部タイマ部４２と、第１演算部割り込み部４３と、第２演算部ソフトウェア制御部４４とを格納する。さらに、プログラム領域４は、第２演算部タイマ部４５と、第２演算部周期処理部４６と、第２演算部サンプリング調整部４７と、第２演算部周期調整部４８と、第２演算部オフセット調整部４９と、第２演算部サンプリング部４０とを格納する。 The program area 4 stores a first calculation unit software control unit 41, a first calculation unit timer unit 42, a first calculation unit interrupt unit 43, and a second calculation unit software control unit 44. Further, the program area 4 includes a second calculation unit timer unit 45, a second calculation unit cycle processing unit 46, a second calculation unit sampling adjustment unit 47, a second calculation unit cycle adjustment unit 48, and a second calculation unit. The offset adjustment unit 49 and the second calculation unit sampling unit 40 are stored.
　第１演算部記憶領域５は、後述する図２の第１演算部データ管理テーブル５１と、図３の第１演算部データ記録テーブル５２と、図４の第１演算部割り込み記録テーブル５３とを格納する。さらに、第２演算部記憶領域６は、後述する図５の第２演算部データ管理テーブル６１と、図６の第２演算部データ記録テーブル６２と、図７の第２演算部サンプリング記録テーブル６３と、図８の第２演算部サンプリング調整テーブル６４と、図９の第２演算部サンプリング周期調整テーブル６５と、図１０の第２演算部オフセット調整テーブル６６とを格納する。 The first calculation unit storage area 5 includes a first calculation unit data management table 51 in FIG. 2, which will be described later, a first calculation unit data recording table 52 in FIG. 3, and a first calculation unit interrupt recording table 53 in FIG. Store. Further, the second arithmetic unit storage area 6 includes a second arithmetic unit data management table 61 shown in FIG. 5, which will be described later, a second arithmetic unit data recording table 62 shown in FIG. 6, and a second arithmetic unit sampling recording table 63 shown in FIG. 8, the second calculation unit sampling adjustment table 64 in FIG. 8, the second calculation unit sampling period adjustment table 65 in FIG. 9, and the second calculation unit offset adjustment table 66 in FIG.
　本処理システムは、マルチコアプロセッサを採用しているため、第１演算部２と、第２演算部３とは、プログラム領域４と、第１演算部データ記憶領域５と、第２演算部データ記憶領域６とに並列にアクセス可能である。さらに、本実例におけるエンジン制御ＥＣＵ１の構成は、これに限らない。エンジン制御ＥＣＵ１は、例えば、データを保存するための不揮発性メモリ（バックアップＲＡＭ）や、各演算部がアクセスするための共有記憶領域や異なるセンサなどを備えてもよい。 Since this processing system employs a multi-core processor, the first calculation unit 2, the second calculation unit 3, the program area 4, the first calculation unit data storage area 5, and the second calculation unit data storage The area 6 can be accessed in parallel. Furthermore, the configuration of the engine control ECU 1 in this example is not limited to this. The engine control ECU 1 may include, for example, a non-volatile memory (backup RAM) for storing data, a shared storage area for each arithmetic unit to access, different sensors, and the like.
　第１演算部記憶領域５に格納され、第１演算部２と、第２演算部３とからアクセス（読み込み，書き込み）されるテーブル５１～５３を、下記より説明する。 The tables 51 to 53 stored in the first calculation unit storage area 5 and accessed (read and written) from the first calculation unit 2 and the second calculation unit 3 will be described below.
　図２は、第１演算部データ管理テーブル５１の一例を示す図である。 FIG. 2 is a diagram illustrating an example of the first arithmetic unit data management table 51.
　第１演算部データ管理テーブル５１は、名称フィールド５１０と、設定値フィールド５１１とからなる。名称フィールド５１０は、第１演算部データ管理テーブル５１が管理する対象の名称である。本実施例では、第１演算部タイマ部４２が操作するソフトウェアタイマの最大値である第１演算部タイマカウンタ最大値からなる。設定値フィールド５１１は、第１演算部データ管理テーブル５１が管理する対象の設定値を表す。 The first arithmetic unit data management table 51 includes a name field 510 and a set value field 511. The name field 510 is a name of a target managed by the first arithmetic unit data management table 51. In the present embodiment, the first arithmetic unit timer unit 42 includes a first arithmetic unit timer counter maximum value which is the maximum value of the software timer operated by the first arithmetic unit timer unit 42. The setting value field 511 represents a setting value to be managed by the first arithmetic unit data management table 51.
　図３は、第１演算部データ記録テーブル５２の一例を示す図である。 FIG. 3 is a diagram illustrating an example of the first calculation unit data recording table 52.
　第１演算部データ記録テーブル５２は、名称フィールド５２０と、値フィールド５２１とからなる。名称フィールド５２０は、第１演算部データ記録テーブル５２が管理する対象の名称である。本実施例では、第１演算部２の動作の基準となるソフトウェアタイマのカウンタ値である第１演算部タイマカウンタ値と、第１演算部２が割り込み時にアクセス(読み込み、書き込み)するテーブルの格納先ＩＤを示す最新値格納先ＩＤとからなる。値フィールド５２１は、第１演算部データ記録テーブル５２で管理する対象の値が格納される。 The first calculation unit data recording table 52 includes a name field 520 and a value field 521. The name field 520 is a name of a target managed by the first calculation unit data recording table 52. In the present embodiment, the first arithmetic unit timer counter value, which is the counter value of the software timer that is the reference for the operation of the first arithmetic unit 2, and the table that the first arithmetic unit 2 accesses (reads and writes) at the time of interruption are stored. It consists of the latest value storage destination ID indicating the destination ID. The value field 521 stores a value to be managed by the first calculation unit data recording table 52.
　図４は、第１演算部割り込み記録テーブル５３の一例を示す図である。 FIG. 4 is a diagram showing an example of the first arithmetic unit interrupt record table 53. As shown in FIG.
　第１演算部割り込み記録テーブル５３は、ＩＤフィールド５３０と、タイマカウンタ値フィールド５３１と、サンプリングフラグフィールド５３２と、データ値フィールド５３３とからなる。ＩＤフィールド５３０は、第１演算部割り込み記録テーブル５３が管理する対象を管理するＩＤである。タイマカウンタ値フィールド５３１は、第１演算部割り込み部４３が第１演算部割り込み記録テーブル５３にアクセスしたタイミングのタイマカウンタ値である。サンプリングフラグフィールド５３２は、第２演算部３からのアクセス有無を示すフラグである。本実施例では、サンプリングフラグは「０」，「１」の２値で表現され、「０」は第２演算部がアクセスしたことを示し、「１」は第２演算部が未アクセスであることを示す。ただし、第２演算部３からのアクセスを示すサンプリングフラグの構成は、これに限らない。データ値フィールド５３３は、第１演算部割り込み記録テーブル５３が管理する割り込みのデータ値を管理するフィールドである。 The first arithmetic unit interrupt record table 53 includes an ID field 530, a timer counter value field 531, a sampling flag field 532, and a data value field 533. The ID field 530 is an ID for managing an object managed by the first arithmetic unit interrupt recording table 53. The timer counter value field 531 is a timer counter value at a timing when the first arithmetic unit interrupt unit 43 accesses the first arithmetic unit interrupt record table 53. The sampling flag field 532 is a flag indicating the presence / absence of access from the second arithmetic unit 3. In this embodiment, the sampling flag is expressed by binary values of “0” and “1”, “0” indicates that the second arithmetic unit is accessed, and “1” is that the second arithmetic unit is not accessed. It shows that. However, the configuration of the sampling flag indicating the access from the second arithmetic unit 3 is not limited to this. The data value field 533 is a field for managing the data value of the interrupt managed by the first arithmetic unit interrupt recording table 53.
　次に、エンジン制御ＥＣＵ１の第２演算部記憶領域６に格納され、第１演算部２と、第２演算部３とからアクセス（読み込み、書き込み）されるテーブル６１～６６を、下記より説明する。 Next, the tables 61 to 66 stored in the second calculation unit storage area 6 of the engine control ECU 1 and accessed (read and written) from the first calculation unit 2 and the second calculation unit 3 will be described below. .
　図５は、第２演算部データ管理テーブル６１の一例を示す図である。 FIG. 5 is a diagram illustrating an example of the second arithmetic unit data management table 61.
　第２演算部データ管理テーブル６１は、名称フィールド６１０と、設定値フィールド６１１とからなる。名称フィールド６１０は、第２演算部データ記録テーブル６１が管理するデータの名称が格納される。本実施例では、第２演算部タイマ部４５が更新するタイマの最大値である第２演算部タイマカウンタ最大値と、第２演算部２が第１演算部記憶領域５にアクセスするサンプリングのタイミングを調整するサンプリング調整周期とからなるが、これに限らない。設定値フィールド６１１は、第２演算部データ記録テーブル６１が管理するデータの設定値が格納される。 The second arithmetic unit data management table 61 includes a name field 610 and a set value field 611. The name field 610 stores the name of data managed by the second arithmetic unit data recording table 61. In the present embodiment, the second arithmetic unit timer counter maximum value, which is the maximum value of the timer updated by the second arithmetic unit timer unit 45, and the sampling timing at which the second arithmetic unit 2 accesses the first arithmetic unit storage area 5 are used. However, the present invention is not limited to this. The set value field 611 stores a set value of data managed by the second arithmetic unit data recording table 61.
　図６は、第２演算部データ記録テーブル６２の一例を示す図である。 FIG. 6 is a diagram showing an example of the second arithmetic unit data recording table 62. As shown in FIG.
　第２演算部データ記録テーブル６２は、名称フィールド６２０と、値フィールド６２１とからなる。名称フィールド６２０は、第２演算部データ記録テーブル６２が管理するデータの名称が格納される。本実施例では、第２演算部タイマ部４５がアクセスするソフトウェアタイマのカウンタである第２演算部タイマカウンタ値と、第２演算部３が第１演算部記憶領域５にアクセスする周期であるサンプリング周期と、第２演算部３が第１演算部記憶領域５にアクセスする周期のオフセットとからなる。しかし、これに限らない。値フィールド６２１は、第２演算部データ記録テーブル６２が管理するデータの値が格納される。 The second arithmetic unit data recording table 62 includes a name field 620 and a value field 621. The name field 620 stores the name of data managed by the second arithmetic unit data recording table 62. In the present embodiment, the second arithmetic unit timer counter value, which is a counter of the software timer accessed by the second arithmetic unit timer unit 45, and the sampling, which is the cycle at which the second arithmetic unit 3 accesses the first arithmetic unit storage area 5, are sampled. It consists of a cycle and an offset of the cycle at which the second computing unit 3 accesses the first computing unit storage area 5. However, it is not limited to this. The value field 621 stores the value of data managed by the second arithmetic unit data recording table 62.
　図７は、第２演算部サンプリング記録テーブル６３の例を示す図である。 FIG. 7 is a diagram showing an example of the second arithmetic unit sampling record table 63. As shown in FIG.
　第２演算部サンプリング記録テーブル６３は、ＩＤフィールド６３０と、タイマカウンタ値フィールド６３１と、サンプリングタイマカウンタ値フィールド６３２と、データ値フィールド６３３とからなる。ＩＤフィールド６０３００は、第２演算部サンプリング記録テーブル６３が管理するデータが格納される領域のＩＤが格納される。タイマカウンタ値フィールド６３１は、第１演算部割り込み部４３が第１演算部記憶領域５にアクセスしたタイマカウンタ値が格納される。サンプリングタイマカウンタ値フィールド６３２は、第２演算部サンプリング部４０が第１演算部記憶領域５にアクセスした際のタイマカウンタ値が格納される。データ値フィールド６３３は、第２演算部サンプリング記録テーブル６３が管理するサンプリングデータの値が格納される。 The second arithmetic unit sampling recording table 63 includes an ID field 630, a timer counter value field 631, a sampling timer counter value field 632, and a data value field 633. The ID field 60300 stores an ID of an area in which data managed by the second arithmetic unit sampling recording table 63 is stored. The timer counter value field 631 stores a timer counter value accessed by the first arithmetic unit interrupt unit 43 to the first arithmetic unit storage area 5. The sampling timer counter value field 632 stores a timer counter value when the second arithmetic unit sampling unit 40 accesses the first arithmetic unit storage area 5. The data value field 633 stores the value of sampling data managed by the second arithmetic unit sampling record table 63.
　図８は、第２演算部サンプリング調整テーブル６４である。 FIG. 8 shows the second arithmetic unit sampling adjustment table 64.
　第２演算部サンプリング調整テーブル６４は、ＩＤフィールド６４０と、割り込み周期フィールド６４１と、割り込み傾向フィールド６４２と、オフセット差フィールド６４３と、オフセット差傾向フィールド６４４とからなる。ＩＤフィールド６４０は、第２演算部サンプリング調整テーブル６４が管理するデータが格納される領域のＩＤが格納される。割り込み周期フィールド６４１は、第２演算部３が第１演算部記憶領域５にアクセスする頻度を算出した結果である割り込み周期を格納する。割り込み周期は、例えば、前回アクセスしてから経過した時間や、第１演算部記憶領域５にアクセスする平均時間などである。割り込み傾向フィールド６４２は、前述した割り込み周期の単位時間当たりの変化率である。割り込み周期の単位時間当たりの変化率は、例えば、最新の割り込み周期と、前回の割り込み周期との差分、または最新の割り込み周期から一定期間内の割り込み周期の変化率である。オフセット差フィールド６４３は、第２演算部サンプリング記録テーブル６３が管理するタイマカウンタ値とサンプリングタイマカウンタ値との差を、オフセット差として格納する。オフセット差傾向フィールド６４４は、オフセット差の単位時間あたりの変化率である。オフセット差の単位時間あたりの変化率は、例えば、最新のオフセット差と前回のオフセット差との差分、または一定時間内のオフセット差の変化率である。 The second arithmetic unit sampling adjustment table 64 includes an ID field 640, an interrupt period field 641, an interrupt tendency field 642, an offset difference field 643, and an offset difference tendency field 644. The ID field 640 stores an ID of an area in which data managed by the second arithmetic unit sampling adjustment table 64 is stored. The interrupt cycle field 641 stores an interrupt cycle that is a result of calculating the frequency with which the second calculation unit 3 accesses the first calculation unit storage area 5. The interrupt cycle is, for example, the time elapsed since the previous access, the average time for accessing the first arithmetic unit storage area 5, or the like. The interrupt tendency field 642 is a rate of change per unit time of the interrupt cycle described above. The rate of change per unit time of the interrupt cycle is, for example, the difference between the latest interrupt cycle and the previous interrupt cycle, or the rate of change of the interrupt cycle within a certain period from the latest interrupt cycle. The offset difference field 643 stores the difference between the timer counter value managed by the second arithmetic unit sampling recording table 63 and the sampling timer counter value as an offset difference. The offset difference tendency field 644 is a change rate per unit time of the offset difference. The change rate per unit time of the offset difference is, for example, the difference between the latest offset difference and the previous offset difference, or the change rate of the offset difference within a certain time.
　図９は、第２演算部サンプリング周期調整テーブル６５である。 FIG. 9 shows the second arithmetic unit sampling cycle adjustment table 65.
　第２演算部サンプリング周期調整テーブル６５は、割り込み傾向判定閾値６５０フィールドと、サンプリング周期補正値フィールド６５１とからなる。割り込み傾向判定閾値６５０フィールドは、第２演算部サンプリング調整テーブル６４が管理する割り込み傾向の値を判定する閾値が格納される。サンプリング周期補正値傾向フィールド６５１は、前述した割り込み傾向の値に応じた補正値を格納する。例えば、割り込み傾向が０以上でかつサンプリング傾向の絶対値が一定値（図中、α）以下であれば、補正値が０となり、一定値（図中、β）以上であれば、指定された値を補正値とする。さらに、割り込み傾向が０より小さく、サンプリング傾向の絶対値が一定値（α）以下であれば指定された値を補正値とし、一定値（β）以上であれば、同様に指定された値を補正値とする。ここで、補正の値は、固定値としているが、これに限らない。補正の値は、例えば、割り込み傾向の値に応じた変化する値でもよい。 The second calculation unit sampling cycle adjustment table 65 includes an interrupt tendency determination threshold value 650 field and a sampling cycle correction value field 651. The interrupt tendency determination threshold value 650 field stores a threshold value for determining an interrupt tendency value managed by the second arithmetic unit sampling adjustment table 64. The sampling period correction value tendency field 651 stores a correction value corresponding to the interrupt tendency value described above. For example, if the interrupt tendency is 0 or more and the absolute value of the sampling tendency is less than a certain value (α in the figure), the correction value is 0, and if the correction value is more than a certain value (β in the figure), it is specified. The value is used as a correction value. Furthermore, if the interrupt tendency is smaller than 0 and the absolute value of the sampling tendency is equal to or less than a certain value (α), the specified value is used as a correction value. The correction value. Here, the correction value is a fixed value, but is not limited thereto. The correction value may be, for example, a value that changes according to the interrupt tendency value.
　図１０は、第２演算部オフセット調整テーブル６６である。 FIG. 10 shows the second calculation unit offset adjustment table 66.
　第２演算部オフセット調整テーブル６６は、オフセット傾向判定閾値フィールド６６０と、オフセットフィールド６６１とからなる。オフセット傾向判定閾値フィールド６６０は、第２演算部サンプリング調整テーブル６４で管理するオフセット差傾向を判定する閾値が格納される。オフセットフィールド６６１は、前述したオフセット差傾向の値に応じたオフセットを格納する。例えば、オフセット差傾向が０以上でかつ一定値（図中、α）以下であれば、指定した値が０となり、一定値（図中、β）以上であれば、指定された値をオフセットする。さらに、オフセット差傾向が０より小さく、オフセット差傾向の絶対値が一定値（α）以下であれば、指定された値をオフセットとし、一定値（β）以上であれば、同様に指定された値をオフセットとする。ここで、オフセットの値は固定値としているが、これに限らない。オフセットの値は、例えば、オフセット差傾向の値に応じて変化する値でもよい。 The second calculation unit offset adjustment table 66 includes an offset tendency determination threshold field 660 and an offset field 661. The offset tendency determination threshold field 660 stores a threshold for determining an offset difference tendency managed by the second arithmetic unit sampling adjustment table 64. The offset field 661 stores an offset corresponding to the above-described offset difference tendency value. For example, if the offset difference tendency is greater than or equal to 0 and less than a certain value (α in the figure), the specified value is 0, and if it is greater than or equal to a certain value (β in the figure), the specified value is offset. . Furthermore, if the offset difference tendency is smaller than 0 and the absolute value of the offset difference tendency is equal to or smaller than a certain value (α), the designated value is set as an offset, and if it is equal to or larger than the certain value (β), it is similarly designated. The value is an offset. Here, the offset value is a fixed value, but is not limited thereto. The offset value may be, for example, a value that changes according to the offset difference tendency value.
　以上のテーブル５１～５３，６１～６６が、本実施例のエンジン制御ＥＣＵ１の第１演算部データ記憶領域５と、第２演算部記憶領域６とに格納される。ただし、各テーブル５１～５３，６１～６６が管理する対象の種類や数および管理方法は、これに限らない。さらに、各テーブル５１～５３，６１～６６は、第１演算部記憶領域５と、第２演算部記憶領域６とから、任意のタイミングでアクセス（読み込み，書き込み）可能である。 The above tables 51 to 53 and 61 to 66 are stored in the first calculation unit data storage area 5 and the second calculation unit storage area 6 of the engine control ECU 1 of the present embodiment. However, the types and number of objects managed by the tables 51 to 53 and 61 to 66 and the management method are not limited to this. Furthermore, each of the tables 51 to 53 and 61 to 66 can be accessed (read and written) at any timing from the first arithmetic unit storage area 5 and the second arithmetic unit storage area 6.
　次に、エンジン制御ＥＣＵ１のプログラム領域４に格納され、第１演算部２で実行されるプログラムの動作フローについて説明する。 Next, the operation flow of the program stored in the program area 4 of the engine control ECU 1 and executed by the first calculation unit 2 will be described.
　図１１は、第１演算部２の第１演算部ソフトウェア制御部４１の動作フローである。以下、図１１の各ステップ４１０～４１２について説明する。 FIG. 11 is an operation flow of the first calculation unit software control unit 41 of the first calculation unit 2. Hereinafter, steps 410 to 412 in FIG. 11 will be described.
　(図１１：ステップ４１０)
  第１演算部ソフトウェア制御部４１は、第１演算部記憶領域５で管理される第１演算部データ記録テーブル５２と、第１演算部割り込み記録テーブル５３とを初期化する。 (FIG. 11: Step 410)
The first calculation unit software control unit 41 initializes the first calculation unit data recording table 52 and the first calculation unit interrupt recording table 53 managed in the first calculation unit storage area 5.
　（図１１：ステップ４１１）
  第１演算部ソフトウェア制御４１は、後述の図７で説明する第１演算部タイマ部４２を呼ぶ。これにより、第１演算部２が参照するタイマのカウンタ値を更新する。 (FIG. 11: Step 411)
The first calculation unit software control 41 calls a first calculation unit timer unit 42 described later with reference to FIG. Thereby, the counter value of the timer which the 1st calculating part 2 refers is updated.
　（図１１：ステップ４１２）
  第１演算部ソフトウェア制御部４１は、終了条件が満たされているか判定し、満たされていれば、処理を終了し、満たされていなければ、ステップ４１１へ戻る。 (FIG. 11: Step 412)
The first calculation unit software control unit 41 determines whether or not the end condition is satisfied. If the end condition is satisfied, the first operation unit software control unit 41 ends the processing. If not satisfied, the process returns to step 411.
　図１２は、第１演算部タイマ部４２の動作フローである。以下、図１２の各ステップ４２０～４２２について説明する。 FIG. 12 is an operation flow of the first arithmetic unit timer unit 42. Hereinafter, steps 420 to 422 in FIG. 12 will be described.
　(図１２：ステップ４２０)
  第１演算部タイマ部４２は、第１演算部データ記録テーブル５２から第１演算部タイマカウンタ値を取得する。取得した値が、データ管理テーブル５１で管理される第１演算部タイマカウンタ最大値と比較し、最大タイマカウンタ以上でれば、ステップ４２１に進み、その他の場合は、ステップ４２２に進む。 (FIG. 12: Step 420)
The first arithmetic unit timer unit 42 acquires the first arithmetic unit timer counter value from the first arithmetic unit data recording table 52. The acquired value is compared with the maximum value of the first arithmetic unit timer counter managed by the data management table 51. If the acquired value is equal to or greater than the maximum timer counter, the process proceeds to step 421. Otherwise, the process proceeds to step 422.
　(図１２：ステップ４２１)
  第１演算部タイマ部４２は、第１演算部データ記録テーブル５２の第１演算部タイマカウンタ値に０を代入し、処理を終了する。 (FIG. 12: Step 421)
The first arithmetic unit timer unit 42 assigns 0 to the first arithmetic unit timer counter value of the first arithmetic unit data recording table 52 and ends the process.
　(図１２：ステップ４２２)
  第１演算部タイマ部４２は、データ記録テーブル５２の第１演算部タイマカウンタ値に１を加算した値を書き込み、処理を終了する。 (FIG. 12: Step 422)
The first arithmetic unit timer unit 42 writes a value obtained by adding 1 to the first arithmetic unit timer counter value of the data recording table 52 and ends the process.
　図１３は、第１演算部割り込み部４３の動作フローである。以下、図１３の各ステップ４３０～４３２について説明する。 FIG. 13 is an operation flow of the first arithmetic unit interrupt unit 43. The steps 430 to 432 in FIG. 13 will be described below.
　(図１３：ステップ４３０)
  第１演算部割り込み部４３は、割り込み処理を実行する。 (FIG. 13: Step 430)
The first arithmetic unit interrupt unit 43 executes interrupt processing.
　(図１３：ステップ４３１)
  第１演算部割り込み部４３は、第１演算部データ記録テーブル５２を参照し、第１演算部タイマカウンタ値と、最新値格納ＩＤとを取得する。第１演算部割り込み部４３は、取得した最新値格納ＩＤと同じＩＤが示す第１演算部割り込み記録テーブル５３のタイマカウンタ値フィールドと、データ値フィールドの値に取得したタイマカウンタ値と、割り込み処理実行結果とを格納する。 (FIG. 13: Step 431)
The first calculation unit interrupt unit 43 refers to the first calculation unit data recording table 52 and acquires the first calculation unit timer counter value and the latest value storage ID. The first calculation unit interrupt unit 43 includes a timer counter value field of the first calculation unit interrupt recording table 53 indicated by the same ID as the acquired latest value storage ID, a timer counter value acquired as the value of the data value field, and an interrupt process. Stores execution results.
　(図１３：ステップ４３２)
  第１演算部割り込み部４３は、第１演算部データ記録テーブル５２が管理する最新値格納ＩＤと、第１演算部割り込み記録テーブル５３のサンプリングフラグとを更新し、処理を終了する。 (FIG. 13: Step 432)
The first arithmetic unit interrupt unit 43 updates the latest value storage ID managed by the first arithmetic unit data recording table 52 and the sampling flag of the first arithmetic unit interrupt recording table 53, and ends the processing.
　次に、エンジン制御ＥＣＵ１のプログラム領域４に格納され、第２演算部３で実行されるプログラムの動作フローについて説明する。 Next, an operation flow of a program stored in the program area 4 of the engine control ECU 1 and executed by the second arithmetic unit 3 will be described.
　図１４は、第２演算部ソフトウェア制御部４４の動作フローである。以下、図１４の各ステップについて説明する。 FIG. 14 is an operation flow of the second arithmetic unit software control unit 44. Hereinafter, each step of FIG. 14 will be described.
　(図１４：ステップ４４０)
  第２演算部ソフトウェア制御部４０４は、第２演算部記憶領域６で管理された第２演算部データ記録テーブル６２と、第２演算部サンプリング記録テーブル６３とを初期化する。 (FIG. 14: Step 440)
The second calculation unit software control unit 404 initializes the second calculation unit data recording table 62 and the second calculation unit sampling recording table 63 managed in the second calculation unit storage area 6.
　(図１４：ステップ４４１)
  第２演算部ソフトウェア制御部４４は、後述の図１５で説明する第２演算部タイマ部４５を呼ぶ。これにより、第２演算部３が参照するタイマのカウンタ値を更新する。 (FIG. 14: Step 441)
The second calculation unit software control unit 44 calls a second calculation unit timer unit 45 described later with reference to FIG. Thereby, the counter value of the timer which the 2nd calculating part 3 refers is updated.
　(図１４：ステップ４４２)
  第２演算部ソフトウェア制御部４４は、後述の図１６で説明する第２演算部周期処理部４６を呼ぶ。これにより、第２演算部３は、一定の周期で処理を実行する。 (FIG. 14: Step 442)
The second calculation unit software control unit 44 calls a second calculation unit cycle processing unit 46 described later with reference to FIG. Thereby, the 2nd calculating part 3 performs a process with a fixed period.
　(図１４：ステップ４４３)
  第２演算部ソフトウェア制御部４４は、終了条件が満たされているか判定し、満たされていれば、処理を終了し、満たされていなければ、ステップ４４１へ戻る。 (FIG. 14: Step 443)
The second arithmetic unit software control unit 44 determines whether or not the end condition is satisfied. If the end condition is satisfied, the second operation unit software control unit 44 ends the processing. If not satisfied, the process returns to step 441.
　図１５は、第２演算部タイマ部４５の動作フローである。以下、図１５の各ステップについて説明する。 FIG. 15 is an operation flow of the second arithmetic unit timer unit 45. Hereinafter, each step of FIG. 15 will be described.
　(図１５：ステップ４５０)
  第２演算部タイマ部４５は、第２演算部データ記録テーブル６２から第２演算部タイマカウンタ値を取得する。取得したタイマカウンタ値をデータ管理テーブル６１で管理される第２演算部タイマカウンタ最大値と比較し、最大タイマカウンタ値以上でれば、ステップ４５１に進み、その他の場合は、ステップ４５２に進む。 (Figure 15: Step 450)
The second arithmetic unit timer unit 45 acquires the second arithmetic unit timer counter value from the second arithmetic unit data recording table 62. The obtained timer counter value is compared with the second arithmetic unit timer counter maximum value managed by the data management table 61. If the timer counter value is equal to or greater than the maximum timer counter value, the process proceeds to step 451. Otherwise, the process proceeds to step 452.
　(図１５：ステップ４５１)
  第２演算部タイマ部４５は、第２演算部データ記録テーブル６２の第２演算部タイマカウンタ値に０を代入し、処理を終了する。 (FIG. 15: Step 451)
The second arithmetic unit timer unit 45 assigns 0 to the second arithmetic unit timer counter value of the second arithmetic unit data recording table 62 and ends the process.
　(図１５：ステップ４５２)
  第２演算部タイマ部４５は、第２演算部データ記録テーブル６２の第２演算部タイマカウンタ値に１を加算した値を書き込み、処理を終了する。 (FIG. 15: Step 452)
The second arithmetic unit timer unit 45 writes a value obtained by adding 1 to the second arithmetic unit timer counter value of the second arithmetic unit data recording table 62 and ends the process.
　図１６は、第２演算部周期処理部４６の動作フローである。以下、図１６の各ステップについて説明する。
  (図１６：ステップ４６０)
  第２演算部周期処理部４６は、後述の図１７で説明する第２演算部サンプリング調整部４７を呼ぶ。これにより、第２演算部周期処理部４６は、サンプリングの周期とオフセットとを判別することができる。 FIG. 16 is an operation flow of the second calculation unit cycle processing unit 46. Hereinafter, each step of FIG. 16 will be described.
(FIG. 16: Step 460)
The second calculation unit cycle processing unit 46 calls a second calculation unit sampling adjustment unit 47 described later with reference to FIG. Thereby, the second calculation unit cycle processing unit 46 can determine the sampling cycle and the offset.
　(図１６：ステップ４６１)
  第２演算部周期処理部４６は、後述の図２０で説明する第２演算部サンプリング部４０を呼ぶ。これにより、第２演算部周期処理部４６は、第１演算部記憶領域５に格納されたデータの最新値を取得できる。 (FIG. 16: Step 461)
The 2nd calculating part period process part 46 calls the 2nd calculating part sampling part 40 demonstrated in below-mentioned FIG. Thereby, the second calculation unit cycle processing unit 46 can acquire the latest value of the data stored in the first calculation unit storage area 5.
　図１７は、第２演算部サンプリング調整部４７の動作フローである。以下、図１７の各ステップについて説明する。 FIG. 17 is an operation flow of the second arithmetic unit sampling adjustment unit 47. Hereinafter, each step of FIG. 17 will be described.
　(図１７：ステップ４７０)
  第２演算部サンプリング調整部は、第２演算部データ記録テーブル６２に格納された第２演算部タイマカウンタ値と、第２演算部データ管理テーブル６１で管理するサンプリング調整タイミングとを比較する。第２演算部タイマカウンタ値が、第２演算部サンプリング調整タイミングで割り切れる場合は、ステップ４７１に進み、それ以外は、処理を終了する。 (FIG. 17: Step 470)
The second calculation unit sampling adjustment unit compares the second calculation unit timer counter value stored in the second calculation unit data recording table 62 with the sampling adjustment timing managed by the second calculation unit data management table 61. If the second arithmetic unit timer counter value is divisible by the second arithmetic unit sampling adjustment timing, the process proceeds to step 471, and otherwise, the process ends.
　(図１７：ステップ４７１)
  第２演算部サンプリング調整部４７は、後述する図１７の第２演算部周期調整部４８を呼ぶ。これにより、第２演算部サンプリング調整部４７は、第１演算部記憶領域５に格納されたデータを取得するサンプリング周期を調整する。 (FIG. 17: Step 471)
The second calculation unit sampling adjustment unit 47 calls a second calculation unit cycle adjustment unit 48 of FIG. Thereby, the second calculation unit sampling adjustment unit 47 adjusts the sampling period for acquiring the data stored in the first calculation unit storage area 5.
　(図１７：ステップ４７２)
  第２演算部サンプリング調整部４７は、後述する図１８の第２演算部オフセット調整部４９を呼ぶ。これにより、第２演算部サンプリング調整部４７は、第１演算部記憶領域５に格納されたデータを取得するサンプリング周期のオフセットを調整する。 (FIG. 17: Step 472)
The second calculation unit sampling adjustment unit 47 calls a second calculation unit offset adjustment unit 49 of FIG. Thereby, the second calculation unit sampling adjustment unit 47 adjusts the offset of the sampling period for acquiring the data stored in the first calculation unit storage area 5.
　図１８は、第２演算部周期調整部４８の動作フローである。以下、図１８の各ステップについて説明する。 FIG. 18 is an operation flow of the second calculation unit cycle adjustment unit 48. Hereinafter, each step of FIG. 18 will be described.
　(図１８：ステップ４８０)
  第２演算部周期調整部４８は、第２演算部サンプリング記録テーブル６３が管理するタイマカウンタ値フィールド６３１を参照し、第１演算部２が第１演算部記憶領域５を更新する周期を算出する。第２演算部周期調整部４８は、その算出結果を第２演算部サンプリング調整テーブル６４の割り込み周期フィールド６４１に記録する。このとき、格納先は、第２演算部データ記録テーブル６２の名称フィールド６２０に格納された最新値格納先ＩＤとする。ここで、割り込み周期とは、第１演算部２が単位時間あたりに第１演算部割り込み記録テーブル５３を更新する時間間隔を指す。割り込み周期は、第２演算部サンプリング記録テーブル６３が管理するタイマカウンタ値を積算した値を、第２演算部サンプリング記録テーブル６３が管理するＩＤの総数で割ることによって算出される。ただし、算出方法は、これに限らない。例えば、算出方法は、システムがおかれる外部状態に応じて第１演算部２が更新する頻度が不定となる、または周期が離散的に切り替わる場合は、タイマカウンタ値の最新値から一定期間のタイマカウンタ値の平均値でもよい。 (FIG. 18: Step 480)
The second calculation unit cycle adjustment unit 48 refers to the timer counter value field 631 managed by the second calculation unit sampling record table 63, and calculates a cycle in which the first calculation unit 2 updates the first calculation unit storage area 5. . The second calculation unit cycle adjustment unit 48 records the calculation result in the interrupt cycle field 641 of the second calculation unit sampling adjustment table 64. At this time, the storage destination is the latest value storage destination ID stored in the name field 620 of the second arithmetic unit data recording table 62. Here, the interrupt cycle refers to a time interval at which the first calculation unit 2 updates the first calculation unit interrupt recording table 53 per unit time. The interrupt period is calculated by dividing the value obtained by integrating the timer counter values managed by the second calculation unit sampling recording table 63 by the total number of IDs managed by the second calculation unit sampling recording table 63. However, the calculation method is not limited to this. For example, when the frequency of updating by the first calculation unit 2 is indefinite or the period is switched discretely according to the external state in which the system is placed, the calculation method is a timer for a certain period from the latest value of the timer counter value. An average value of the counter values may be used.
　(図１８：ステップ４８１)
  第２演算部周期調整部４０８は、第２演算部サンプリング調整テーブル６０４の割り込み周期フィールド６４１から第１演算部２がデータを更新する割り込みの傾向を算出する。このとき、格納先は、第２演算部データ記録テーブル６０２の名称フィールド６０２００に格納された最新値格納先ＩＤに算出結果が記録される。ここで、割り込み傾向とは、前述した割り込み周期の単位時間当たりの変化率である。割り込み傾向は、例えば、最新の割り込み周期と前回の割り込み周期との差分、または最新の割り込み周期から一定期間内の割り込み周期の変化率である。 (Figure 18: Step 481)
The second calculation unit cycle adjustment unit 408 calculates the tendency of an interrupt in which the first calculation unit 2 updates data from the interrupt cycle field 641 of the second calculation unit sampling adjustment table 604. At this time, as the storage destination, the calculation result is recorded in the latest value storage destination ID stored in the name field 60200 of the second arithmetic unit data recording table 602. Here, the interrupt tendency is the rate of change per unit time of the interrupt cycle described above. The interrupt tendency is, for example, the difference between the latest interrupt cycle and the previous interrupt cycle, or the rate of change of the interrupt cycle within a certain period from the latest interrupt cycle.
　(図１８：ステップ４８２)
  第２演算部周期調整部４８は、前述した割り込み傾向の絶対値と、その符号と第２演算部サンプリング周期調整テーブル６５とを比較し、サンプリング周期補正値を求める。第２演算部周期調整部４８は、更新周期にサンプリング周期補正値を加えた値を、第２演算部データ記録テーブル６２にサンプリング周期として記録し、処理を終了する。 (FIG. 18: Step 482)
The second calculation unit cycle adjustment unit 48 compares the absolute value of the interrupt tendency described above with its sign and the second calculation unit sampling cycle adjustment table 65 to obtain a sampling cycle correction value. The second calculation unit cycle adjustment unit 48 records the value obtained by adding the sampling cycle correction value to the update cycle as the sampling cycle in the second calculation unit data recording table 62, and ends the process.
　図１９は、第２演算部オフセット調整部４９の動作フローである。以下、図１９の各ステップについて説明する。 FIG. 19 is an operation flow of the second calculation unit offset adjustment unit 49. Hereinafter, each step of FIG. 19 will be described.
　(図１９：ステップ４９０)
  第２演算部オフセット調整部４９は、第２演算部サンプリング記録テーブル６３のタイマカウンタ値６３１と、サンプリングタイマカウンタ値６３２とに基づいて、オフセット差を算出する。第２演算部オフセット調整部４９は、算出したオフセット差を第２演算部サンプリング調整テーブル６４のオフセット差フィールド６４３に記録する。このとき、第２演算部オフセット調整部４９は、第２演算部データ記録テーブル６２の名称フィールド６２０に格納された最新値格納先ＩＤに結果を記録する。 (FIG. 19: Step 490)
The second calculation unit offset adjustment unit 49 calculates an offset difference based on the timer counter value 631 and the sampling timer counter value 632 of the second calculation unit sampling recording table 63. The second calculation unit offset adjustment unit 49 records the calculated offset difference in the offset difference field 643 of the second calculation unit sampling adjustment table 64. At this time, the second calculation unit offset adjustment unit 49 records the result in the latest value storage destination ID stored in the name field 620 of the second calculation unit data recording table 62.
　(図１９：ステップ４９１)
  第２演算部オフセット調整部４９は、第２演算部サンプリング調整テーブル６４のオフセット差からオフセット差傾向を算出し、その結果を第２演算部サンプリング調整テーブル６４のオフセット差傾向６４４フィールドに記録する。このとき、第２演算部データ記録テーブル６２の名称フィールド６２０に格納された最新値格納先ＩＤに結果を記録する。ここで、オフセット傾向とは、前述したオフセット差の単位時間当たりの変化率である。オフセット傾向は、例えば、最新のオフセット差と前回のオフセット差の差分、または最新のオフセット差から一定期間内のオフセット差の変化率である。 (FIG. 19: Step 491)
The second calculation unit offset adjustment unit 49 calculates an offset difference tendency from the offset difference of the second calculation unit sampling adjustment table 64 and records the result in the offset difference tendency 644 field of the second calculation unit sampling adjustment table 64. At this time, the result is recorded in the latest value storage destination ID stored in the name field 620 of the second arithmetic unit data recording table 62. Here, the offset tendency is a change rate per unit time of the offset difference described above. The offset tendency is, for example, the difference between the latest offset difference and the previous offset difference, or the change rate of the offset difference within a certain period from the latest offset difference.
　(図１９：ステップ４９２)
  第２演算部オフセット調整部４９は、算出したオフセット差傾向の絶対値と、その符号と第２演算部オフセット調整テーブル６６とに基づいて、オフセットを算出し、第２演算部データ記録テーブル６２にオフセットとして記録し、処理を終了する。 (FIG. 19: Step 492)
The second calculation unit offset adjustment unit 49 calculates an offset based on the calculated absolute value of the offset difference tendency, its sign, and the second calculation unit offset adjustment table 66, and stores it in the second calculation unit data recording table 62. Record as an offset and end the process.
　図２０は、第２演算部サンプリング部４０の動作フローである。以下、図２０の各ステップについて説明する。 FIG. 20 is an operation flow of the second arithmetic unit sampling unit 40. Hereinafter, each step of FIG. 20 will be described.
　(図２０：ステップ４００)
  第２演算部サンプリング部４０は、第２演算部データ記録テーブル６２に基づいてサンプリング周期と、オフセットとを取得する。 (FIG. 20: Step 400)
The second calculation unit sampling unit 40 acquires a sampling period and an offset based on the second calculation unit data recording table 62.
　(図２０：ステップ４０１)
  第２演算部サンプリング部４０は、第２演算部データ記録テーブル６２から取得した第２演算部タイマカウンタ値とオフセットとに基づいて、サンプリングタイミングかどうかを判定する。第２演算部サンプリング部４０は、サンプリングのタイミングであれば、ステップ４０２へ進み、それ以外は、終了する。ここで、サンプリングタイミングであるかどうかを判定するには、第２演算部タイマカウンタ値にオフセットを加えた値を、第２演算部データ記録テーブル６２に格納されたサンプリング周期で割り切れるかどうかで判定する。 (FIG. 20: Step 401)
The second calculation unit sampling unit 40 determines whether it is a sampling timing based on the second calculation unit timer counter value and the offset acquired from the second calculation unit data recording table 62. The second arithmetic unit sampling unit 40 proceeds to step 402 if it is a sampling timing, and ends otherwise. Here, in order to determine whether or not it is the sampling timing, it is determined whether or not the value obtained by adding the offset to the second arithmetic unit timer counter value is divisible by the sampling period stored in the second arithmetic unit data recording table 62. To do.
　(図２０：ステップ４０２)
  第２演算部サンプリング部４０は、第１演算部データ記録テーブル５２の最新値格納先ＩＤが示す第１演算部割り込み記録テーブル５３の最新値を取得する。最新値の取得後、第２演算部サンプリング部４０は、第２演算部データ記録テーブル６２が保持する最新値格納ＩＤが示す第２演算部サンプリング記録テーブル６３の値を更新する。更新後、第２演算部データ記録テーブル６３が格納する最新値格納ＩＤを更新し、処理を終了する。 (FIG. 20: Step 402)
The second calculation unit sampling unit 40 acquires the latest value of the first calculation unit interrupt recording table 53 indicated by the latest value storage destination ID of the first calculation unit data recording table 52. After acquiring the latest value, the second calculation unit sampling unit 40 updates the value of the second calculation unit sampling record table 63 indicated by the latest value storage ID held in the second calculation unit data recording table 62. After the update, the latest value storage ID stored in the second arithmetic unit data recording table 63 is updated, and the process is terminated.
　以上のように、本実施例によれば、プログラムを実行する複数の演算部２，３と、複数の演算部２，３が周期的にアクセスする記録領域５と、外部情報を検出するセンサ８とを備え、複数の演算部２，３は、センサ８が検出した外部情報を受信し、当該受信した外部情報に基づいて、記憶領域５に対する処理を調整する。これにより、変動する外部情報に追従して、記憶領域５に対する処理を変更することができ、複数の演算部２，３のうちの何れかに負荷が集中することを抑制することができる。従って、相互に異なる２つの演算部２，３間で共有する資源となる記録領域５への競合を抑制し、演算部２，３の利用効率を向上することができる。 As described above, according to the present embodiment, the plurality of calculation units 2 and 3 that execute the program, the recording area 5 that the plurality of calculation units 2 and 3 periodically access, and the sensor 8 that detects external information. The plurality of arithmetic units 2 and 3 receive the external information detected by the sensor 8 and adjust the processing for the storage area 5 based on the received external information. Thereby, the process for the storage area 5 can be changed following the fluctuating external information, and the concentration of the load on any one of the plurality of calculation units 2 and 3 can be suppressed. Accordingly, it is possible to suppress contention on the recording area 5 serving as a resource shared between two different calculation units 2 and 3 and to improve the utilization efficiency of the calculation units 2 and 3.
　さらに、外部情報は、記録領域５に対する書込頻度であるので、記録領域５に対する書き込み頻度が高い場合でも、複数の演算部２，３のうちの何れかに集中する負荷を低減することができる。 Furthermore, since the external information is the writing frequency to the recording area 5, even when the writing frequency to the recording area 5 is high, it is possible to reduce the load concentrated on any one of the plurality of calculation units 2 and 3. .
　さらに、複数の演算部２，３は、外部情報に基づいて、記憶領域５に対する処理の周期を調整するので、実行する処理の周期を調整するだけで、変動する外部情報に追従した処理に容易に変更することができる。 Furthermore, since the plurality of calculation units 2 and 3 adjust the processing cycle for the storage area 5 based on the external information, it is easy to perform processing that follows the fluctuating external information simply by adjusting the processing cycle. Can be changed.
　さらに、複数の演算部２，３は、外部情報に基づいて、記録領域５から外部情報を読み込む処理の周期を調整するので、記録領域５の更新周期を調整するだけで、変動する外部情報に追従した処理に容易に変更することができる。 Furthermore, since the plurality of calculation units 2 and 3 adjust the cycle of the process of reading the external information from the recording area 5 based on the external information, the adjustment of the update cycle of the recording area 5 makes it possible to change the external information to fluctuate. It is possible to easily change the process to follow.
　さらに、複数の演算部２，３は、外部情報に基づいて、周期の位相を調整するので、実行する処理の調整幅が広がる。 Furthermore, since the plurality of calculation units 2 and 3 adjust the phase of the cycle based on the external information, the adjustment range of processing to be executed is widened.
　さらに、複数の演算部２，３は、外部情報の時間変化率を算出し、当該算出した外部情報の時間変化率に基づいて、記憶領域５に対する処理を調整するので、将来の外部情報を予測でき、実行する処理の信頼性を高めることできる。 Further, the plurality of calculation units 2 and 3 calculate the time change rate of the external information, and adjust the processing for the storage area 5 based on the calculated time change rate of the external information, so that future external information is predicted. It is possible to improve the reliability of the processing to be executed.
１…エンジン制御装置、２…第１演算部、３…第２演算部、５…第１演算部記憶領域、７…入出力回路、８…センサ DESCRIPTION OF SYMBOLS 1 ... Engine control apparatus, 2 ... 1st calculating part, 3 ... 2nd calculating part, 5 ... 1st calculating part storage area, 7 ... Input-output circuit, 8 ... Sensor

Claims (6)

  1. 　プログラムを実行する複数の演算部と、
    　前記複数の演算部が周期的にアクセスする記憶領域と、
    　外部情報を検出する検出部とを備え、
    　前記複数の演算部は，前記検出部が検出した前記外部情報を受信し、当該受信した外部情報に基づいて、前記記憶領域に対する処理を調整する、車両制御装置。     A plurality of arithmetic units for executing the program;
    A storage area periodically accessed by the plurality of arithmetic units;
    A detection unit for detecting external information,
    The plurality of calculation units receive the external information detected by the detection unit, and adjust processing for the storage area based on the received external information.
  2. 　前記外部情報は、前記記憶領域に対する書込み頻度である、請求項１記載の車両制御装置。 The vehicle control device according to claim 1, wherein the external information is a frequency of writing to the storage area.
  3. 　前記複数の演算部は、前記外部情報に基づいて、前記記憶領域に対する処理の周期を調整する、請求項１記載の車両制御装置。 The vehicle control device according to claim 1, wherein the plurality of calculation units adjust a processing cycle for the storage area based on the external information.
  4. 　前記複数の演算部は、前記外部情報に基づいて、前記記録領域から前記外部情報を読み込む処理の周期を調整する、請求項３記載の車両制御装置。 The vehicle control device according to claim 3, wherein the plurality of calculation units adjust a cycle of a process of reading the external information from the recording area based on the external information.
  5. 　前記複数の演算部は、前記外部情報に基づいて、前記周期の位相を調整する、請求項４記載の車両制御装置。 The vehicle control device according to claim 4, wherein the plurality of calculation units adjust the phase of the cycle based on the external information.
  6. 　前記複数の演算部は，前記外部情報の時間変化率を算出し、当該算出した外部情報の時間変化率に基づいて、前記記憶領域に対する処理を調整する、請求項１記載の車両制御装置。 The vehicle control device according to claim 1, wherein the plurality of calculation units calculate a time change rate of the external information, and adjust processing for the storage area based on the calculated time change rate of the external information.
PCT/JP2018/010701 2017-03-27 2018-03-19 Vehicle control device WO2018180664A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017060430A JP2018163528A (en) 2017-03-27 2017-03-27 Vehicle control device
JP2017-060430 2017-03-27

Publications (1)

Publication Number Publication Date
WO2018180664A1 true WO2018180664A1 (en) 2018-10-04

Family

ID=63675811

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/010701 WO2018180664A1 (en) 2017-03-27 2018-03-19 Vehicle control device

Country Status (2)

Country Link
JP (1) JP2018163528A (en)
WO (1) WO2018180664A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04168530A (en) * 1990-10-31 1992-06-16 Mitsubishi Electric Corp Program priority control system
JPH0664565A (en) * 1992-06-10 1994-03-08 Norm Pacific Autom Corp Device for preventing, recording, testing and analyzing vehicle accident
WO2012001835A1 (en) * 2010-07-02 2012-01-05 パナソニック株式会社 Multiprocessor system
JP2013171547A (en) * 2012-02-23 2013-09-02 Hitachi Automotive Systems Ltd Vehicle control device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5737135B2 (en) * 2011-10-26 2015-06-17 トヨタ自動車株式会社 Control device for internal combustion engine

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04168530A (en) * 1990-10-31 1992-06-16 Mitsubishi Electric Corp Program priority control system
JPH0664565A (en) * 1992-06-10 1994-03-08 Norm Pacific Autom Corp Device for preventing, recording, testing and analyzing vehicle accident
WO2012001835A1 (en) * 2010-07-02 2012-01-05 パナソニック株式会社 Multiprocessor system
JP2013171547A (en) * 2012-02-23 2013-09-02 Hitachi Automotive Systems Ltd Vehicle control device

Also Published As

Publication number Publication date
JP2018163528A (en) 2018-10-18

Similar Documents

Publication Publication Date Title
US20220334948A1 (en) Methods and apparatus to improve performance data collection of a high performance computing application
US9164899B2 (en) Administering thermal distribution among memory modules of a computing system
US10467106B2 (en) Data processing method, data processing system, and non-transitory computer program product for controlling a workload delay time
US20120297216A1 (en) Dynamically selecting active polling or timed waits
US20120266163A1 (en) Virtual Machine Migration
US9239742B2 (en) Embedded systems and methods for threads and buffer management thereof
JP2008310748A (en) Task execution time recording device, task execution time recording method, and task execution recording program
CN109889406B (en) Method, apparatus, device and storage medium for managing network connection
US20180217875A1 (en) Data processing system and data processing method
US8601488B2 (en) Controlling the task switch timing of a multitask system
WO2018180664A1 (en) Vehicle control device
WO2015075803A1 (en) Information processing device, method, program, and storage medium
JPWO2004046926A1 (en) Event notification method, device, and processor system
US7827215B2 (en) Real-time operation by a diskless client computer
US20070239972A1 (en) Processing internal timestamp counter instructions in reference to external counter
US8566538B2 (en) Administering thermal distribution among memory modules with call stack frame size management
WO2013129061A1 (en) Control system for simultaneous number of connections, control server for simultaneous number of connections, control method for simultaneous number of connections and control program for simultaneous number of connections
US11216336B2 (en) Storage apparatus and memory device control method
EP4239482A1 (en) Electronic device and method with on-demand accelerator checkpointing
KR101014524B1 (en) Method of reading data coherently
EP4068096A1 (en) Data processing program, information processing system, and data processing method
US20220156074A1 (en) Electronic device and multiplexing method of spatial
JP2007172519A (en) Information processor, link management method for software module, and program
KR20230007774A (en) Memory management system and method for edge type artificial intelligence SoC
JP2014002649A (en) Semiconductor device and access timing adjustment method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18774679

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18774679

Country of ref document: EP

Kind code of ref document: A1