JP2009200701A - Cmos differential amplifier circuit and semiconductor integrated circuit for power control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS differential amplifier circuit in which an input offset can be reduced and an operation point is easily set. <P>SOLUTION: The CMOS differential amplifier circuit includes: a differential input stage (11) provided with a pair of differential MOS transistors (Mp1, Mp2), a pair of load MOS transistors (Mn1, Mn2) respectively connected to the drain terminals of the differential MOS transistors, and a current source connected to the common source of the differential MOS transistors; and an output stage (12) provided with a pair of N-type MOS transistors (Mn3, Mn4) connected so as to receive the potential on the drain side of the differential MOS transistors at a gate terminal, a pair of P-type MOS transistors (Mp3, Mp4) which are serial with the respective MOS transistors, and have terminals connected to a first power supply voltage terminal, and a P-type MOS transistor (Mp5) and an N-type MOS transistor (Mn5) which are connected between the P-type MOS transistors and the N-type MOS transistors and to which a constant voltage is applied respectively at the gate terminals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an input offset reduction technique in a CMOS differential amplifier circuit, and is used, for example, in an error amplifier circuit for amplifying a feedback voltage used in a power supply control semiconductor integrated circuit constituting a DC power supply device such as a DC-DC converter. Related to effective technology.

  A CMOS differential amplifier circuit as shown in FIG. 4 is known as an error amplifier circuit used in a control semiconductor integrated circuit to amplify a feedback voltage. The CMOS differential amplifier circuit shown in FIG. 4 includes a differential input stage 11 and an output stage 12. The differential input stage 11 includes a pair of differential MOS transistors (insulated gate field effect transistors) Mp1 and Mp2 connected in common, load MOS transistors Mn1 and Mp2, and Mp1 and Mp2 respectively connected to the drains thereof. A constant current source CI connected between the common source and the power supply voltage VDD;

The output stage 12 is connected in series between the load MOS transistors Mn1 and Mn2 of the differential input stage 11 and the MOS transistors Mn3 and Mn4 respectively connected in a current mirror manner, and between the Mn3 and Mn4, the power supply voltage VDD, and the ground point. The MOS transistors Mp3 and Mp4 are configured so that Mp3 and Mp4 are connected in a current mirror, and an output is taken out from a connection node N1 between Mn3 and Mp3.
JP 11-265600 A JP 2005-12852 A

  In the differential amplifier circuit, it is important to reduce the input offset. As a result of detailed examination of the CMOS differential amplifier circuit shown in FIG. 4 by the present inventors, the drain voltage of the MOS transistor Mp3 and the drain voltage of Mn4 in the output stage 12 are likely to be fluctuated due to fluctuations in the power supply voltage VDD. It has been found that due to the channel modulation effect accompanying fluctuations in the voltage, a current equal to Mp3 and Mp4 does not flow even when there is no signal (I1 ≠ I2), causing an input offset.

  As an input offset reduction technique in a CMOS differential amplifier circuit, for example, there are those disclosed in Patent Document 1 and Patent Document 2, but the offset reduction mechanism is different between these inventions and the present invention. .

  An object of the present invention is to provide a CMOS differential amplifier circuit that can reduce an input offset and can easily set an operating point.

  Another object of the present invention is to provide a CMOS differential amplifier circuit suitable for use in applications where the fluctuation range of the input voltage is relatively narrow, such as an error amplifier circuit used in a power supply control semiconductor integrated circuit. .

  To achieve the above object, the present invention provides a pair of first conductivity type differential MOS transistors connected in common to a source, and a pair of second conductivity type loads connected to the drain terminals of the differential MOS transistors. A differential input stage having a MOS transistor and a current source connected to a common source of the differential MOS transistor, and a pair of drains connected to receive the potential on the drain side of the differential MOS transistor at the gate terminal First and second MOS transistors of the second conductivity type, and a pair of first and third MOS transistors of the first conductivity type in series with each of the first and second MOS transistors and having a source terminal connected to the first power supply voltage terminal A constant voltage is applied to each of the gate terminals connected to the transistors, the third and fourth MOS transistors, and the first and second MOS transistors. A first 6MOS transistor of the 5MOS transistor and the second conductivity type of a first conductivity type, and an output stage having a by is obtained so as to constitute a CMOS differential amplifier circuit.

  Here, preferably, the first and second MOS transistors are configured in a current mirror connection with each of the pair of load MOS transistors in the differential input stage. More preferably, the third and fourth MOS transistors are configured to be current mirror connected.

  According to the above configuration, a CMOS differential amplifier circuit that can reduce the input offset and easily set the operating point can be realized.

  Further, the voltages applied to the gate terminals of the fifth and sixth MOS transistors are set to be the same. This simplifies the circuit that generates the constant voltage applied to the gate terminals of the fifth and sixth MOS transistors.

  A phase compensation circuit composed of a parallel capacitor and resistor is connected between the first and second MOS transistors and the second power supply voltage terminal. This makes it difficult for oscillation to occur when used in a feedback loop.

  According to the present invention, the input offset can be reduced and the operating point can be easily set. Further, there is an effect that a CMOS differential amplifier circuit suitable for use in applications where the variation range of the input voltage is relatively narrow, such as an error amplifier circuit used in a power supply control semiconductor integrated circuit, can be realized.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a CMOS differential amplifier circuit according to the present invention.
The CMOS differential amplifier circuit of this embodiment comprises a differential input stage 11 and an output stage 12. The differential input stage 11 includes a pair of P-channel type differential MOS transistors Mp1 and Mp2 connected in common to each other, N-channel type load MOS transistors Mn1 and Mp2 connected to their drains, and Mp1 and Mp2, respectively. A constant current source CI connected between the common source and the power supply voltage VDD;

  The output stage 12 includes a pair of P-channel MOS transistors Mp3 and Mp4 whose source terminals are connected to the power supply voltage VDD and whose gates are commonly connected to each other, and load MOS transistors Mn1 and Mn2 of the differential input stage 11, respectively. MOS transistors Mn3 and Mn4 whose gates are commonly connected, and a P-channel MOS transistor Mp5 and an N-channel MOS transistor Mn5 connected in series between the Mn3 and Mp4 and the MOS transistors Mp3 and Mp4, respectively Consists of.

  In the load MOS transistors Mn1 and Mn2 in the input stage 11, the gates and drains are coupled, Mn1 is connected to the gates of the output stage MOS transistors Mn3, and Mn2 is connected to the gates of the output stage MOS transistors Mn4 and Mn2. Thus, each current mirror circuit is configured. The MOS transistors Mp3 and Mp4 that supply the drain currents of Mn3 and Mn4 also form a current mirror circuit by connecting the gates and drains of Mp4 and connecting the gates of Mp3 and Mp4.

  In this way, the current I4 of Mn4 in which current proportional to the drain current of Mn2 flows according to the size ratio of the current mirrors Mn2 and Mn4 is folded by the current mirror composed of Mp4 and Mp3, and the drain of the folded Mp3 By causing the current I3 to flow through the input stage load MOS transistor Mn1 and Mn3 connected in a current mirror, linearity in the vicinity of the operating point, that is, in the vicinity of the intermediate potential between the power supply voltage VDD (for example, 5V) and the ground potential (0V) is obtained. An excellent amplifier circuit is realized.

  Further, in this embodiment, the constant voltage Va is applied to the gate terminals of Mp5 and Mn5 connected between Mn3 and Mp3 and between Mn4 and Mp4, respectively, so that the transistor operates as a grounded gate type transistor. Then, the connection node N1 between Mp5 and Mn3 is connected to the output terminal OUT to take out the output.

  In the conventional differential amplifier circuit as shown in FIG. 4 without Mp5 and Mn5, the drain voltage of the MOS transistor Mp3 in the output stage 12 and the drain voltage of Mn4 (particularly the drain voltage of Mp3) are the power supply voltage VDD. Due to the channel modulation effect accompanying the fluctuation of the voltage, current equal to Mp3 and Mp4 did not flow even when there was no signal, and an input offset occurred.

  In contrast, in the differential amplifier circuit of this embodiment, Mp5 and Mn5 are connected between Mn3 and Mp3 and between Mn4 and Mp4, respectively, and a constant voltage Va is applied to the gate terminal. , Mp5 and Mn5 suppress fluctuations in the drain voltage of Mp3 and the drain voltage of Mn4 and stabilize the potential. As a result, it is possible to suppress the change of the drain currents of Mp3 and Mn4 due to the channel modulation effect, and to obtain an effect that the input offset is reduced.

  Further, in the differential amplifier circuit, there is a problem that the circuit operating point, that is, the output amplitude center deviates from the target value due to variations in elements, but in the differential amplifier circuit of this embodiment, Mp5 and Mn5 There is an advantage that the operating point can be easily adjusted to the target value by adjusting the constant voltage Va applied to the gate terminal in accordance with the element variation. When the power supply voltage VDD is 5 V, the constant voltage Va is around 2.5 V, which is a substantially intermediate potential between 5 V and the ground potential of 0 V, and an optimum value is selected as the operating point, that is, the output amplitude center. The When used as an error amplifier in a later-described DC-DC converter, the optimum range of the constant voltage Va was 2.0 to 2.2V.

In the above embodiment, the same constant voltage Va is applied to the gate terminals of Mp5 and Mn5, but separate constant voltages may be applied. Thereby, the operating point can be set to the target value with higher accuracy. However, if the configuration is such that different constant voltages are applied, the operation of matching the operating points becomes very troublesome, so if the same constant voltage Va is applied to the gate terminals of Mp5 and Mn5 as in the above embodiment. Often enough.
(Modification)
FIG. 2 shows a modification of the differential amplifier circuit of the above embodiment. In this modification, a phase compensation circuit is added to the differential amplifier circuit of FIG. 1 to increase the phase margin of the circuit so that oscillation does not easily occur. Specifically, resistors R3 and R4 are connected between the MOS transistors Mn3 and Mn4 in the output stage and the ground point, and capacitors C1 and C2 are connected in parallel with these resistors R3 and R4, respectively, to thereby provide a phase compensation circuit. Configured.

Further, a resistor R5 and a capacitor C3 are connected in series between the output terminal OUT and the ground point to form a phase compensation circuit. Further, although not particularly limited, in order to match the bias condition of each MOS transistor of the output stage 12 with the bias condition of each MOS transistor of the differential input stage 11, the load MOS transistors Mn1, Mn2 of the input stage and the ground point The resistors R1 and R2 are also connected between the two.
(Application example)
FIG. 3 shows a configuration example of a DC-DC converter as a suitable system using the differential amplifier circuit of the above embodiment. FIG. 3 shows a switching regulator type DC-DC converter, in which the differential amplifier circuit of the above embodiment is used as an error amplifier for amplifying an output feedback voltage.

  The DC-DC converter shown in FIG. 3 is connected between a coil L1 as an inductor, a voltage input terminal IN to which a DC input voltage Vin is applied, and one terminal of the coil L1, and a drive current flows into the coil L1. Driving switch transistor SW1 composed of a P-channel MOSFET, synchronous rectification switch transistor SW2 composed of an N-channel MOSFET provided between the coil terminal and the ground point, and switching control for controlling on / off of these switch transistors SW1 and SW2. The circuit 20 includes a smoothing capacitor C1 connected between the other terminal of the coil L1 and a ground point.

  Although not particularly limited, elements other than the coil L1 and the smoothing capacitor C1 among elements constituting the DC-DC converter are formed on one semiconductor chip. That is, the control circuit 20 and the switching elements SW1 and SW2 are configured as a semiconductor integrated circuit (IC), and the coil L1 and the capacitor C1 are connected to external terminals provided in the IC as external elements. .

  In the DC-DC converter shown in FIG. 3, the switching control circuit 20 generates a driving pulse that complementarily turns on and off the transistors SW1 and SW2, and in a steady state, the driving switch transistor SW1. Is turned on, the DC input voltage Vin is applied to the coil L1, a current directed to the output terminal flows, the smoothing capacitor C1 is charged, and when the drive switch transistor SW1 is turned off, the synchronous rectification switch transistor is substituted. SW2 is turned on, and a current flows through the coil L1 through the turned-on transistor SW2. Then, the pulse width of the drive pulse input to the control terminal (gate terminal) of SW1 is controlled according to the output feedback voltage, so that the DC output voltage Vout obtained by stepping down the DC input voltage Vin is generated.

  The switching control circuit 20 is connected in series between the voltage feedback terminal FB and the ground point, and bleeder resistors R1 and R2 that divide the output voltage Vout by a resistance ratio, and the voltage divided by the bleeder resistor and the reference voltage Vref1. Are output from the PWM comparator 22, an error amplifier 21 that outputs a voltage corresponding to the potential difference, a PWM (pulse width modulation) comparator 22 that outputs the output of the error amplifier 21 to a non-inverting input terminal. And a driver circuit 23 for generating a signal for driving the gates of the switch transistors SW1 and SW2 based on the PWM pulse.

  The switching control circuit 20 includes a waveform generation circuit 24 that generates a waveform signal such as a triangular wave or a sawtooth wave applied to the inverting input terminal of the PWM comparator 22, and a reference voltage Vref1 applied to the error amplifier 21. A reference voltage generation circuit 25 including a band gap reference circuit for generating Further, when the differential amplifier circuit of the embodiment is used as the error amplifier 21, the constant voltage Va applied to the gate terminals of the MOS transistors Mp5 and Mn5 may be generated by the reference voltage generation circuit 25. it can.

  In the DC-DC converter of FIG. 3, a voltage corresponding to the potential difference between the reference voltage Vref1 and the voltage obtained by resistance-dividing the output feedback voltage is output from the error amplifier 21 to the PWM comparator 22, and the output voltage is output by the PWM comparator 22. When the output voltage decreases, the width of the PWM pulse is lengthened to increase the on time of the switch transistor SW1, and when the output voltage increases, the width of the PWM pulse is shortened to shorten the on time of the switch transistor SW1.

  In the DC-DC converter, the output voltage Vout does not fluctuate rapidly in a steady state with little fluctuation in the load, and the period during which a relatively small fluctuation voltage is output from the error amplifier 21 becomes long. When the differential amplifier circuit of the above-described embodiment is used for such an error amplifier 21, it is possible to perform amplification with extremely excellent linearity in a voltage range with small fluctuations by combining the operating points. Accurate feedback control of the output voltage becomes possible.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above-described embodiment, the differential amplifier circuit using the P-channel MOSFET as the differential input transistor is shown. However, the differential amplifier using the N-channel MOSFET as the differential input transistor and the P-channel MOSFET as the load MOSFET. In the circuit, that is, the circuit of FIGS. 1 and 2, the present invention can be applied to a circuit in which the relationship between the power supply voltage VDD and the ground potential GND is reversed and the conductivity type of each transistor is reversed.

  In the above embodiment, the load MOS transistor Mn1 in the differential input stage and the MOS transistor Mn3 in the output stage, and Mn2 and Mn4 are connected in current mirror, respectively. However, Mn1 and Mn2 are connected in current mirror. The output stage MOS transistors Mn3 and Mn4 may be connected so that the gate terminal receives the drain voltage of the load MOS transistor Mn1 or Mn2 in the differential input stage.

  Further, in the above embodiment, the output stage MOS transistors Mp3 and Mp4 are shown as being current-mirror connected. However, Mp3 and Mp4 are so-called diode-connected MOS transistors in which their gates and drains are coupled. It may be.

  In the above description, the example in which the present invention is applied to an error amplifier of a DC-DC converter has been described. However, the present invention is not limited to this, and a differential amplifier circuit that amplifies a signal having a relatively small amplitude range is described. It can be widely used for built-in semiconductor integrated circuits.

1 is a circuit diagram showing one embodiment of a CMOS differential amplifier circuit according to the present invention. FIG. FIG. 6 is a circuit diagram showing a modification of the differential amplifier circuit of FIG. 1. It is a block diagram which shows the structural example of the DC-DC converter as a suitable system using the differential amplifier circuit of an Example. It is a circuit diagram which shows an example of the conventional CMOS differential amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Differential input stage 12 Output stage 20 Switching control circuit 21 Error amplifier 22 PWM comparator 23 Driver circuit 24 Waveform generation circuit 25 Reference voltage generation circuit Mp1, Mp2 Differential MOS transistor Mn1, Mn2 Load MOS transistor SW1 Drive switch transistor SW2 Synchronization Switch transistor for rectification

Claims (7)

A differential input stage having a pair of first conductivity type differential MOS transistors connected in common to a source and a pair of second conductivity type load MOS transistors respectively connected to the drain terminals of the differential MOS transistors; ,
A pair of first and second MOS transistors of the second conductivity type connected to receive the drain side potential of the differential MOS transistor at the gate terminal, and a pair of first MOS transistors whose source terminals are connected to the first power supply voltage terminal. First conductivity type third and fourth MOS transistors, and first conductivity type first MOS transistors connected between the third and fourth MOS transistors and the first and second MOS transistors, respectively, each having a constant voltage applied to the gate terminal. An output stage having a 5MOS transistor and a second MOS transistor of the second conductivity type;
A CMOS differential amplifier circuit comprising:   2. The CMOS differential amplifier circuit according to claim 1, wherein the first and second MOS transistors are current-mirror connected to each of a pair of load MOS transistors of the differential input stage.   3. The CMOS differential amplifier circuit according to claim 1, wherein the third and fourth MOS transistors are current mirror connected.   4. The CMOS differential amplifier circuit according to claim 1, wherein the voltages applied to the gate terminals of the fifth and sixth MOS transistors are the same.   5. The CMOS according to claim 4, wherein a phase compensation circuit composed of a parallel capacitor and resistor is connected between the first and second MOS transistors and the second power supply voltage terminal. Differential amplifier circuit. An error amplifier that outputs a voltage corresponding to the potential difference between the feedback voltage from the output side and the reference voltage, and a PWM comparator that receives the output of the error amplifier at one input terminal, and a current flowing through the voltage conversion inductor A power supply control semiconductor integrated circuit having a switching control circuit for generating a control signal for a driving switching element to be controlled,
6. A power supply control semiconductor integrated circuit using the CMOS differential amplifier circuit according to claim 1 as the error amplifier.   A reference voltage generation circuit that generates the reference voltage supplied to the error amplifier and a constant voltage applied to the gate terminals of the fifth MOS transistor and the sixth MOS transistor of the CMOS differential amplifier circuit. A power supply control semiconductor integrated circuit according to claim 6.

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