JP2009200667A - Signal amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal amplifier circuit capable of maintaining an SN ratio by securing a wide dynamic range even when a voltage is lowered. <P>SOLUTION: The signal amplifier circuit comprises: a reference voltage generation circuit for outputting a first reference voltage set at the intermediate voltage of a prescribed voltage, a second reference voltage set between the first reference voltage and a ground potential, and a third reference voltage set between the prescribed potential and the first reference voltage; an amplifier circuit 31 for amplifying input signals with the first reference voltage as the reference potential; and a voltage level conversion circuit 40 for converting signals from the amplifier circuit 31 to non-inverted output signals in which the second reference voltage is used as a reference, also converting them to inverted output signals in which the third reference voltage is used as a reference, and using a difference between the non-inverted output signal and the inverted output signal as an output signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal amplifier circuit that amplifies an electric signal.

  A conventional signal amplifying circuit is described in Patent Document 1. The photodetector built-in preamplifier described in Patent Document 1 is shown in FIG. As shown in FIG. 8, a conventional signal amplifier circuit includes an amplifier 102 that converts a current signal that flows when a photodiode 101 receives light into an input current signal into a voltage signal, and an output voltage that amplifies the converted voltage signal. And an amplifier 103 that outputs the signal.

  The gain of the amplifier 102 that converts current into voltage is determined by the resistor R10, and the gain of the amplifier 103 that amplifies the voltage signal is determined by the resistor R101 / resistor R102. In the conventional gain adjustment circuit integrated on one chip, the resistor R102 is divided into a plurality of resistors in order to make it easy to change the gain, and can be set to an arbitrary gain by rearranging the wiring in the chip. I have to.

Another conventional signal amplifier circuit is shown in FIG. The signal amplifying circuit shown in FIG. 9 is used as a part of the front monitor circuit of the optical disk drive, and the changeover switch 104, the gain adjusting resistor R _DVD , and the like so that the gain can be switched between DVD and CD. It includes a R _CD, and a gain adjustment volume VR1, VR2. In order to ensure a wide dynamic range, an inversion buffer 105 and a non-inversion buffer 106 are provided, and a voltage difference between an output terminal V _{out +} from the inversion buffer 105 and an output terminal V _out− from the non-inversion buffer 106. Is the output signal.
JP 63-108808 A

FIG. 10A shows voltage characteristics when the power supply voltage of the signal amplifier circuit shown in FIG. 9 is operated at 5V. As shown in FIG. 10A, from the reference voltage V _ref (2.5 V), the potential of the output terminal V _{out +} is the power supply potential until the amplifier 103 is saturated in accordance with the increase of the input voltage of the amplifier 103. The potential of the output terminal _Vout− decreases to near the ground potential. Since the output signal is a voltage difference between the output terminal V _{out +} from the inverting buffer 105 and the output terminal V _out− from the non-inverting buffer 106, a dynamic range close to + 5V can be secured.

However, in recent years, the power supply voltage has been lowered for the purpose of reducing power consumption and the like, so the dynamic range becomes narrower than when the power supply voltage is 5V. For example, FIG. 10B shows voltage characteristics when the power supply voltage is 3.3V. When the power supply voltage is 3.3 V, the reference voltage V _ref is 1.65 V, which is half of 3.3 V, the output voltage V _{out +} rises to near the power supply potential, and the output voltage V _out− is the ground potential. Even if it drops to near, the dynamic range cannot be secured above 3.3V.

  Therefore, when the signal amplifier circuit shown in FIG. 9 is operated at a low voltage, the dynamic range is narrowed, so that the SN ratio is lowered.

  Accordingly, an object of the present invention is to provide a signal amplifier circuit that can maintain an SN ratio by ensuring a wide dynamic range even when the voltage is lowered.

  The signal amplifying circuit of the present invention includes a first reference voltage set to an intermediate voltage of a predetermined voltage, a second reference voltage set between the first reference voltage and a ground potential, the predetermined potential, and the first voltage A reference voltage generation circuit that outputs a third reference voltage set between the reference voltage, an amplification circuit that amplifies an input signal using the first reference voltage as a reference potential, and a signal from the amplification circuit Is converted into a non-inverted output signal based on the second reference voltage, and is converted into an inverted output signal based on the third reference voltage, and the difference between the non-inverted output signal and the inverted output signal is converted. And a voltage level conversion circuit using the output signal as an output signal.

  The present invention relates to a non-inverted output signal based on a second reference voltage lower than the first reference voltage, which is an intermediate voltage, and an inverted output signal based on a third reference voltage higher than the first reference voltage. By using this differential signal, a wide dynamic range can be secured even if the voltage is lowered. Therefore, the SN ratio can be maintained.

  According to a first aspect of the present application, a first reference voltage set to an intermediate voltage of a predetermined voltage, a second reference voltage set between the first reference voltage and the ground potential, the predetermined potential and the first reference voltage A reference voltage generation circuit that outputs a third reference voltage set between the first reference voltage, an amplification circuit that amplifies an input signal using the first reference voltage as a reference potential, and a signal from the amplification circuit as a second reference. A voltage level conversion circuit that converts a non-inverted output signal with a voltage as a reference and converts the third reference voltage into an inverted output signal with a reference as a reference and uses the difference between the non-inverted output signal and the inverted output signal as an output signal It is characterized by having.

  In the signal amplifying circuit of the present invention, the reference voltage generating circuit, the first reference voltage set to the intermediate voltage of the predetermined voltage, the second reference voltage set between the first reference voltage and the ground potential, A third reference voltage set between the predetermined potential and the first reference voltage is output. The amplifier circuit amplifies and outputs the input signal using the first reference voltage as a reference voltage. The voltage level conversion circuit converts the output signal from the amplifier circuit into a non-inverted output signal based on the second reference voltage. The voltage level conversion circuit converts the output signal from the amplifier circuit into an inverted output signal based on the third reference voltage. The voltage level conversion circuit uses the difference between the non-inverted output signal and the inverted output signal as the output signal. Therefore, the output signal is a difference between the non-inverted output signal based on the second reference voltage lower than the first reference voltage, which is an intermediate voltage, and the inverted output signal based on the third reference voltage higher than the first reference voltage. Since it becomes a dynamic signal, a wide dynamic range can be secured even if the voltage is lowered.

  According to a second invention of the present application, in the first invention, the voltage level conversion circuit level-shifts the signal from the amplifier circuit to a signal based on the second reference voltage and outputs the signal as a second reference voltage signal. A level shift circuit that outputs a third reference voltage signal by level shifting to a signal based on the third reference voltage, the second reference voltage signal is input to the non-inverting terminal, and the second reference voltage is input to the inverting input terminal. And a third reference voltage amplifier having a third reference voltage signal input to an inverting terminal and a third reference voltage input to a non-inverting input terminal. It is.

  In the second invention of the present application, the voltage level conversion circuit can be composed of a level shift circuit, a second reference voltage amplifier, and a third reference voltage amplifier.

  According to a third aspect of the present invention, in the second aspect, the level shift circuit includes at least four or more series-connected divisions that voltage-divides the predetermined voltage into the first reference voltage, the second reference voltage, and the third reference voltage. A resistor is provided, and the output from the amplifier circuit is connected to an intermediate position of the series-connected divided resistors, and the position where the voltage is divided into the second reference voltage is set as the output terminal of the second reference voltage signal, and the third reference voltage is set. The voltage dividing position is the output terminal of the third reference voltage signal.

  In the third invention of the present application, the level shift circuit can be divided resistors so that the voltage level can be shifted with a simple circuit.

  According to a fourth aspect of the present invention, in any one of the first to third aspects, the reference voltage generating circuit divides the predetermined voltage into a first reference voltage, a second reference voltage, and a third reference voltage and outputs the divided voltage. , At least four or more divided resistors connected in series are provided.

  In the fourth invention of the present application, the voltage level can be shifted with a simple circuit by making the reference voltage generating circuit a dividing resistor.

  According to a fifth invention of the present application, in the fourth invention, the dividing resistor forming the level shift circuit and the dividing resistor forming the reference voltage generating circuit are formed by a semiconductor integrated circuit, and have substantially the same wiring width and wiring. It is characterized by being formed with a long length and adjacently arranged.

  In the fifth invention of the present application, when the dividing resistor forming the level shift circuit and the dividing resistor forming the reference voltage generating circuit are formed by a semiconductor integrated circuit, the wiring width and the wiring length are almost equal. By forming and arranging them adjacent to each other, it is possible to form divided resistors having substantially the same electrical characteristics.

(Embodiment)
A signal amplifier circuit according to an embodiment of the present invention will be described with reference to the drawings, taking an optical signal amplifier circuit of a front monitor circuit mounted on an optical disk drive as an example. FIG. 1 is a circuit diagram showing an optical signal amplifier circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a reference voltage generating circuit for supplying a reference voltage to the optical signal amplifier circuit shown in FIG.

  As shown in FIG. 1, the optical signal amplifier circuit 10 includes a photodiode 20, an amplifier circuit 30, and a voltage level conversion circuit 40, and is a semiconductor integrated circuit that operates at a predetermined potential 3.3V supplied from a power supply terminal Vcc. Circuit. The optical signal amplifying circuit 10 includes a reference voltage generating circuit 50 shown in FIG.

  The photodiode 20 is a light receiving element that passes a current corresponding to the intensity of the received optical signal. The photodiode 20 has an anode connected to the ground terminal GND and a cathode connected to the amplifier circuit 30.

  The amplifier circuit 30 includes a first amplifier 31, gain adjustment volumes VR <b> 1 and VR <b> 2, and a changeover switch 32 as feedback resistors of the first amplifier 31.

In the first amplifier 31, the cathode of the photodiode 20 and the external terminal 33 are connected to the inverting input terminal, and the first reference voltage V _ref1 from the reference voltage generating circuit 50 is connected to the non-inverting input terminal. The operational amplifier functions as a current-voltage conversion (IV) amplifier that outputs a voltage signal corresponding to the current flowing through the diode 20.

  The gain adjustment volumes VR1 and VR2 are externally attached via external terminals 33 to 34. The gain adjustment volume VR1 is for DVD, and the gain adjustment volume VR2 is for CD. The gain adjustment volumes VR1 and VR2 switch the connection state of the changeover switch 32 by inputting a changeover signal to the changeover terminal SW, and the connection to the first amplifier 31 is changed.

  The voltage level conversion circuit 40 includes a level shift circuit 41 and a voltage amplification circuit 42. The level shift circuit 41 includes resistors R11 to R14, a first buffer 41a, and a second buffer 41b.

  The resistors R11 to R14 are series-connected divided resistors that divide the power supply voltage set to 3.3V. In the resistors R11 to R14, the resistors R11 and R14 have the same resistance value, and the resistors R12 and R13 have the same resistance value. In the present embodiment, the resistors R11 and R14 are 20 kΩ, and the resistors R12 and R13 are 13 kΩ. Therefore, the connection point between the resistor R12 and the resistor R13 to which the output of the first amplifier 31 is connected is a position where the voltage is divided into 1.65V, which is half of the intermediate voltage of the power supply voltage. Further, the connection point between the resistor R11 and the resistor R12 is voltage-divided into 1V, becomes a position for outputting the second reference voltage signal, and is connected to the input of the first buffer 41a. Further, the connection point between the resistors R13 and R14 is divided into 2.3V voltage, becomes a position for outputting the third reference voltage signal, and is connected to the input of the second buffer 41b.

  The first buffer 41a and the second buffer 41b output the second reference voltage signal or the third reference voltage signal as they are without converting the voltage level. The first buffer 41a and the second buffer 41b are provided in order to avoid voltage fluctuations in the level shift circuit 41 formed by a divided resistor due to the influence of the voltage amplifier circuit.

  The voltage amplifier circuit 42 includes a second amplifier 42a (second reference voltage amplifier) and a third amplifier 42b (third reference voltage amplifier).

In the second amplifier 42a, the output of the first buffer 41a is connected to the non-inverting input terminal, the second reference voltage _Vref2 is connected to the inverting input terminal via the resistor R21, and the resistor R22 which is a feedback resistor is connected. Thus, the operational amplifier functions as a non-inverting amplifier having a bias voltage of the second reference voltage V _ref2 and an amplification factor of R22 / R21. The output terminal of the second amplifier 42a is connected to the output terminal _{Vout +} via the resistor R23. In the present embodiment, the gain of the second amplifier 42a is set to 4 by setting the resistance R21 to 1 kΩ and the resistance R22 to 3 kΩ.

In the third amplifier 42b, the third reference voltage _Vref3 is connected to the non-inverting input terminal, the output of the second buffer 41b is connected to the inverting input terminal via the resistor R31, and the resistor R32 that is a feedback resistor is connected. _Thus , the operational amplifier functions as an inverting amplifier having a bias voltage of the third reference voltage V _ref3 and having an amplification factor of R32 / R31. The output terminal of the third amplifier 42b is connected to the output terminal V _out− via a resistor R33. In the present embodiment, the gain of the third amplifier 42b is set to 4 by setting the resistance R31 to 1 kΩ and the resistance R32 to 4 kΩ.

  The reference voltage generation circuit 50 includes resistors R41 to R44, a first reference voltage buffer 51, a second reference voltage buffer 52, and a third reference voltage buffer 53.

The first resistors R41 to R44 are divided resistors connected in series to voltage-divide between the 3.3V power supply voltage and the ground. In the resistors R41 to R44, the resistor R41 and the resistor R44 have the same resistance value, and the resistor R42 and the resistor R43 have the same resistance value. Therefore, the connection point between the resistor R42 and the resistor R43 is at a position where the voltage is divided into 1.65V, which is half of the power supply voltage, even in the intermediate voltage between the power supply voltage and the ground potential. This is the first reference voltage output point for extracting the voltage V _ref1 . A connection point between the resistor R41 and the resistor R42 serves as a second reference voltage output point for extracting the second reference voltage _{Vref2 serving} as a reference for the second amplifier 42a. Further, the connection point between the resistor R43 and the resistor 44 is a third reference voltage output point for extracting the third reference voltage _{Vref3 serving} as a reference for the third amplifier 42b.

A first reference voltage buffer 51, a second reference voltage buffer 52, and a third reference voltage buffer 53 are connected to the first to third reference voltage output points, respectively. The output of the first reference voltage buffer 51 is _supplied to the first amplifier 31 as the first reference voltage V _ref1 , and the output of the second reference voltage buffer 52 is _supplied to the second amplifier 42a as the second reference voltage V _ref2 . The output of the buffer 53 is output to the third amplifier 42b as the third reference voltage _Vref3 .

In the present embodiment, the resistors R41 and R44 are 20 kΩ, and the resistors R42 and R43 are 13 kΩ. Therefore, as described above, the first reference voltage V _ref1 is 1.65V, the second reference voltage V _ref2 is 1V, and the third reference voltage V _ref3 is _2.3V .

  The resistors R41 to R44 of the reference voltage generating circuit 50 and the resistors R11 to R14 of the level shift circuit 41 are formed with substantially the same wiring width and wiring length, and are arranged adjacent to each other. By doing so, it is possible to form resistors R41 to R44 and resistors R11 to R14 which are divided resistors having substantially the same electrical characteristics.

  In this embodiment, in order to set the first reference voltage to 1.65V, the second reference voltage to 1V, and the third reference voltage to 2.3V, the resistors R11 and R14 and the resistors 41 and R44 are set to 20 kΩ. The resistors R12 and R13 and the resistors 42 and R43 are set to 13 kΩ, but may be changed according to the operating voltage of the optical signal amplifier circuit 10, or may be changed according to the saturation voltage of the second amplifier 42a or the third amplifier 42b. can do. In addition, the first reference voltage is a half of the power supply voltage, but it may be a voltage that is in the middle of the power supply voltage.

  The operation of the optical signal amplifier 1 according to the embodiment of the present invention configured as described above will be further described with reference to FIGS. FIG. 3 is a graph showing the characteristics of the output voltage of the first amplifier. FIG. 4 is a graph showing the output voltage characteristics of the first buffer. FIG. 5 is a diagram illustrating the characteristics of the output voltage of the second buffer. 6A and 6B are diagrams illustrating the characteristics of the output voltage of the voltage amplifier circuit, in which FIG. 6A is a diagram illustrating the characteristics of the second amplifier, and FIG. FIG. 7 is a diagram illustrating the voltage characteristics of the output signal.

  As shown in FIG. 1, first, a switching signal of the switch 32 is input from the switching terminal SW to designate switching of the gain adjustment volumes VR1 and VR2.

When the optical signal is applied to the photodiode 20 of the optical signal amplifier circuit 10, the photodiode 20 passes a current corresponding to the intensity of the optical signal. In accordance with the current flowing through the photodiode 20, the first amplifier 31 outputs a voltage signal with a voltage based on the first reference voltage _Vref1 . The voltage characteristics of the first amplifier 31 at this time are shown in FIG. In the voltage characteristics shown in FIG. 3, as the input current rises from 0 A, the output voltage rises by current-voltage conversion from the first reference voltage V _ref1 (1.65 V), which is a bias voltage, and the input current is increased due to saturation. Even if the voltage rises, the output voltage becomes constant.

The voltage level of the signal from the first amplifier 31 having the bias voltage set to the first reference voltage V _ref1 is converted by the level shift circuit 41. That is, a signal from the first amplifier 31 whose bias voltage is set to the first reference voltage V _ref1 is taken out from the connection point between the resistor R11 and the resistor R12, and 1V (second reference voltage V _ref2 ) is used as a reference. Converted to the second reference voltage signal. Further, by extracting a signal from the first amplifier 31 whose bias voltage is set to the first reference voltage V _ref1 from the connection point between the resistor R14 and the resistor R13, 2.3 V (third reference voltage V _ref3 ) is obtained. It is converted into a reference third reference voltage signal. The first buffer 41a and the second buffer 41b output the input signal as it is without converting the voltage level.

As shown in FIG. 4, the signal from the first buffer 41a has a voltage characteristic in which the bias voltage is shifted from the first reference voltage _Vref1 to the second reference voltage _Vref2 . Further, as shown in FIG. 5, the signal from the second buffer 41b is a voltage characteristic bias voltage is shifted relative to the third reference voltage V _ref3 from the first reference voltage V _ref1.

Next, the signal output from the first buffer 41a is non-inverted and amplified by the second amplifier 42a and output to the output terminal _{Vout +} . FIG. 6A shows voltage characteristics of a signal output to the output terminal V _{out +} . As shown in FIG. _6A , the output voltage of the signal output to the output terminal V _{out +} is amplified from 1V, which is the bias voltage, in accordance with the input voltage rising from the second reference voltage V _ref2 (1V). And, even if the input voltage rises due to saturation, the output voltage becomes constant.

Further, the signal output from the second buffer 41b is inverted and amplified by the third amplifier 42b and output to the output terminal V _out− . FIG. 6B shows voltage characteristics of a signal output to the output terminal V _out− . As shown in FIG. 6B, the output signal output to the output terminal V _out− is a bias voltage of _2.3V according to the input voltage rising from the third reference voltage V _ref3 ( _2.3V ). Thus, the output voltage is inverted and amplified, and the output voltage becomes constant even when the input voltage rises due to saturation.

Then, by calculating the difference between the signal level at the output terminal V _{out +} shown in FIG. _6A and the signal level at the output terminal V _out− shown in FIG. 6B as an output signal by an external circuit, A differential output signal having voltage characteristics as shown in FIG. 7 can be obtained. That is, as the input voltage increases from the second reference voltage V _ref2 (1V) _−the third reference voltage V _ref3 ( _2.3V ), the voltage at the output terminal V _{out− and} the voltage at the output terminal V _{out +} Since it is amplified to the calculated voltage, a wider dynamic range than the power supply voltage of 3.3V can be secured. Therefore, the SN ratio can be maintained even when the voltage is lowered.

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to the said embodiment. In the present embodiment, the level shift circuit 41 and the reference voltage generation circuit 50 are provided so as to divide the voltage between the power supply voltage and the ground, but can be set to a predetermined voltage different from the power supply voltage. .

  In the present embodiment, the level shift circuit 41 and the reference voltage generation circuit 50 are formed by dividing resistors. However, the level shift circuit 41 may be configured by a DC-DC converter, or the reference voltage generation circuit 50 may be a regulator. It is also possible to configure with. However, it is desirable to form with a dividing resistor because a reference voltage generating circuit can be easily formed.

  Further, the level shift circuit 41 and the reference voltage generation circuit 50 are four resistors connected in series. If each resistor is set to have a predetermined resistance value, a divided resistor is constituted by four or more resistors. You may make it do.

  The present invention is suitable for a signal amplifying circuit that amplifies an electric signal because the SN ratio can be maintained by securing a wide dynamic range even when the voltage is lowered.

1 is a circuit diagram showing an optical signal amplifier circuit according to an embodiment of the present invention. 1 is a circuit diagram showing a reference voltage generating circuit for supplying a reference voltage to the optical signal amplifier circuit shown in FIG. The figure which shows the characteristic of the output voltage of a 1st amplifier The figure which shows the characteristic of the output voltage of a 1st buffer The figure which shows the characteristic of the output voltage of a 2nd buffer It is a figure which shows the characteristic of the output voltage of a voltage amplifier circuit, (A) is a figure which shows the characteristic of a 2nd amplifier, (B) is a figure which shows the characteristic of a 3rd amplifier. Diagram showing voltage characteristics of output signal Circuit diagram showing a conventional signal amplifier Circuit diagram showing another conventional signal amplifier (A) is a figure which shows the voltage characteristic when operating the power supply voltage of another conventional signal amplifier circuit at 5V, (B) is operating the power supply voltage of another conventional signal amplifier circuit at 3.3V. Figure showing the voltage characteristics

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Optical signal amplifier circuit 20 Photodiode 30 Amplifier circuit 31 1st amplifier 32 Changeover switch 33-35 External terminal 40 Voltage level conversion circuit 41 Level shift circuit 41a 1st buffer 41b 2nd buffer 42 Voltage amplifier circuit 42a 2nd amplifier 42b 2nd amplifier 3 amplifier 50 reference voltage generation circuit 51 first reference voltage buffer 52 second reference voltage buffer R11 to R14, R21 to R23, R31 to R33, R41 to R44 resistors VR1, VR2 gain adjustment volume V _ref1 first reference voltage V _ref2 first 2 reference voltage V _ref3 3rd reference voltage V _{out +} output terminal SW switching terminal Vcc power supply terminal GND ground terminal

Claims (5)

A first reference voltage set to an intermediate voltage of a predetermined voltage, a second reference voltage set between the first reference voltage and the ground potential, and set between the predetermined potential and the first reference voltage A reference voltage generating circuit for outputting the third reference voltage generated;
An amplifier circuit for amplifying an input signal using the first reference voltage as a reference potential;
The signal from the amplifier circuit is converted into a non-inverted output signal based on the second reference voltage, and is converted into an inverted output signal based on the third reference voltage, and the non-inverted output signal and the A signal amplification circuit comprising: a voltage level conversion circuit that uses a difference from an inverted output signal as an output signal. The voltage level conversion circuit includes:
The signal from the amplifier circuit is level-shifted to a signal based on the second reference voltage and output as a second reference voltage signal, and level-shifted to a signal based on the third reference voltage. A level shift circuit that outputs a reference voltage signal;
A second reference voltage amplifier, wherein the second reference voltage signal is input to a non-inverting terminal, and the second reference voltage is input to an inverting input terminal;
2. The signal amplification circuit according to claim 1, further comprising a third reference voltage amplifier having the third reference voltage signal input to an inverting terminal and the third reference voltage input to a non-inverting input terminal. The level shift circuit includes at least four or more series-connected dividing resistors that divide the predetermined voltage into the first reference voltage, the second reference voltage, and the third reference voltage,
The output from the amplifier circuit is connected to an intermediate position of the series-connected split resistors,
The position where the voltage is divided into the second reference voltage is the output terminal of the second reference voltage signal,
3. The signal amplifier circuit according to claim 2, wherein a position where the voltage is divided into the third reference voltage is an output terminal of the third reference voltage signal. The reference voltage generation circuit includes at least four or more series-connected divided resistors that divide and output the predetermined voltage into the first reference voltage, the second reference voltage, and the third reference voltage. The signal amplifier circuit according to claim 1, wherein the signal amplifier circuit is a signal amplifier circuit. The dividing resistor forming the level shift circuit and the dividing resistor forming the reference voltage generation circuit are formed by a semiconductor integrated circuit, are formed with substantially the same wiring width and wiring length, and are arranged adjacent to each other. 5. The signal amplifier circuit according to claim 4, wherein the signal amplifier circuit is provided.

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