JP2009198590A - Thin film transistor array substrate and inspection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To write and read charges to/from each pixel and improve efficiency in inspection as much as possible in array inspection of TFT array substrate. <P>SOLUTION: The TFT array substrate includes: a plurality of first TFTs provided on a plurality of the pixels respectively; a plurality of auxiliary capacities connected to first TFTs respectively; a plurality of source lines 16a connected to first TFTs respectively and extending between the plurality of the pixels in parallel with each other; and a plurality of connection terminals 21 connected to the source lines 16a respectively. The TFT array substrate includes: a plurality of second TFTs 5b connected to connection terminal 21, respectively; a plurality of inspection terminals 23 provided for each adjacent N (N is 2 or more natural number) second TFTs 5b and connected to each adjacent second TFT 5b respectively; and a control circuit 25a for turning on one of the N second TFTs 5b connected to respective inspection terminals 23 by controlling on/off of each second TFT 5b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film transistor array substrate and an inspection method thereof, and more particularly to an array inspection technique for a thin film transistor array substrate.

  In an active matrix liquid crystal display panel, a plurality of pixels, each of which is a minimum unit of an image, are arranged in a matrix. For example, for each pixel, a thin film transistor (hereinafter referred to as TFT) and a pixel connected to the TFT A TFT array substrate having electrodes, a counter substrate disposed opposite to the TFT array substrate and having a common electrode, and a liquid crystal layer sealed between the two substrates are provided.

  As a method for inspecting the liquid crystal display panel, for example, an inspection signal is input to each of the pixel electrodes of the TFT array substrate and the common electrode of the counter substrate, and all the pixels are turned on. A lighting inspection is widely known in which a defective pixel (defective pixel) is detected by applying light from a backlight from the back of the display panel.

  In the above lighting inspection, if the liquid crystal display panel is determined to be defective due to the detected defective pixel or the like, the counter substrate or the like constituting the liquid crystal display panel is wasted. Array inspection such as a charge detection method that inspects not in a panel state but in a substrate state has attracted attention. Here, in the charge detection method, the same charge as the actual operation is written to all the pixels of the TFT array substrate, and after a predetermined time has elapsed, the written charge is read and the normality / defectiveness of each pixel is determined from the change To do.

  For example, in Patent Document 1, wirings having terminal pads connected to a plurality of thin film control elements for controlling display are individually extended in a non-display region via extension wirings, and switching elements are connected to the extension wirings. There is disclosed a display device in which a terminal pad portion for inspection is formed via According to this, it is described that the conduction of the inspection terminal pad is switched by the switching element, and when the conduction is conducted, the thin film control element can be inspected by energization.

  Further, in Patent Document 2, inspection switching elements for switching supply of display signals for inspection are individually connected to a plurality of data lines, and each inspection switching element is connected via an inspection switching element. In addition, an inspection display signal line for supplying an inspection display signal to the data line is provided in common, and a control signal line for inputting a control signal for conducting / interrupting the inspection switching element is connected to the adjacent data line. There is disclosed an active matrix liquid crystal display panel in which a plurality of different control signals are input. According to this, it is possible to provide a liquid crystal display panel that can identify a leak defect between signal systems and can also visually detect a leak between data lines without increasing the number of processes. Has been.

  Patent Document 3 discloses a liquid crystal display panel in which a plurality of inspection terminals are arranged in a plurality of rows according to a predetermined rule. And, according to this, since it becomes possible to inspect the disconnection, short circuit, etc. of the electrode by an inspection device using a simple strip-like inspection terminal such as a conductive rubber, it has a structure compared to that using a pin type probe. However, it is described that an intermediate function inspection using a simple and inexpensive inspection apparatus can be performed.

Patent Document 4 discloses a liquid crystal display unit formed on a display substrate, signal lines and scanning lines formed on the display substrate, and part or all of the signal lines and scanning lines formed on the display substrate. There is disclosed a liquid crystal display device comprising a logic circuit that performs a predetermined logical operation with the input as input and reduces the number of outputs with respect to the input, and an inspection terminal for taking out an output signal of the logic circuit to the outside. . According to this, it is described that it is possible to easily perform an operation test, a mounting inspection, and a liquid crystal display unit inspection of the driving IC.
Japanese Patent Laid-Open No. 2005-241988 JP 11-338376 A JP 2006-215302 A Japanese Patent Laid-Open No. 5-265026

  By the way, when inspecting a TFT array substrate having a COG (Chip On Glass) mounting structure in which a bare chip of an integrated circuit chip is mounted on a glass substrate, a TFT corresponding to each of a plurality of bumps arranged on the bottom surface of the bare chip. Needle-like probe pins must be brought into contact with a plurality of connection terminals provided on the array substrate. Here, in the TFT array substrate having a general COG mounting structure, the pitch between the terminals of the plurality of connection terminals is as narrow as 40 μm to 60 μm, and each of the plurality of connection terminals arranged at the narrow pitch has Since a plurality of probe pins formed extremely finely must be brought into contact with each other reliably, there is a possibility that the inspection efficiency may be lowered.

  In each of the above patent documents, a lighting test for lighting each pixel is assumed, and an array test for the TFT array substrate is not assumed. For example, in Patent Document 1, a plurality of pixels are used for testing. Although charges can be collectively written through the terminal pad portion, it is considered impossible to individually read the written charges. In Patent Documents 2 to 4, writing and reading to a specific pixel are not possible. It is considered impossible. In Patent Document 4, it is considered that a simple test is performed in which a signal output from a liquid crystal display device after chip mounting is reduced by a logic circuit and received and inspected.

  The present invention has been made in view of the above points, and an object of the present invention is to perform individual writing and reading for each pixel in the array inspection of the thin film transistor array substrate, and to improve the efficiency of the inspection. Is to improve.

  In order to achieve the above object, the present invention provides a plurality of inspection terminals provided for every N (N is a natural number of 2 or more) adjacent to a plurality of second thin film transistors respectively connected to each connection terminal. And a control circuit for controlling on / off of each second thin film transistor to turn on one of the N second thin film transistors connected to each inspection terminal.

  Specifically, the thin film transistor array substrate according to the present invention includes a plurality of pixels provided in a matrix, a plurality of first thin film transistors provided in each of the pixels, and a plurality of pixels connected to the first thin film transistors. An auxiliary capacitor; a plurality of source lines provided in parallel to each other between the plurality of pixels; and connected to the first thin film transistors; and a plurality of connection terminals connected to the source lines, respectively. A plurality of second thin film transistors connected to each of the connection terminals, and N adjacent to each of the plurality of second thin film transistors (N is a natural number of 2 or more). A plurality of inspection terminals respectively connected to the adjacent second thin film transistors, and the second thin film transistors And controls the on / off, characterized in that it comprises a control circuit for one of the second TFT connected to the N to each test pin to the on state.

  According to the above configuration, the plurality of inspection terminals provided for every N (N is a natural number of 2 or more) adjacent to the plurality of second thin film transistors connected to each connection terminal of the thin film transistor array substrate. And a control circuit that controls on / off of each second thin film transistor to turn on one of the N second thin film transistors connected to each inspection terminal. By inputting a signal, one of the N second thin film transistors connected to each inspection terminal is turned on. At this time, by inputting an inspection signal to each inspection terminal, the connection terminal connected to each second thin film transistor that is turned on, the source line connected to the connection terminal, and the ON connected to the source line The charge written in the auxiliary capacitor can be read after the charge is written into the auxiliary capacitor connected to the first thin film transistor through the first thin film transistor in the state. Therefore, it is possible to detect the presence or absence of a defect in each pixel by individually writing and reading out each pixel. In addition, since each inspection terminal for inputting / outputting the inspection signal is provided for every N adjacent second thin film transistors, the number of terminals with which the probe pins are brought into contact during the array inspection is reduced, and each inspection terminal is provided. Can be designed to be large, for example, about N times the width of each connection terminal. This makes it possible to reduce the number of probing pins per cell, so the number of cells that are measured simultaneously increases, so the number of times that the probe pins abut on the substrate decreases, and the probe pins that abut each inspection terminal Can be designed thicker than before, the strength of the propping pin is increased, the frequency of replacement thereof is reduced, and the efficiency of inspection is improved. Accordingly, in the array inspection of the thin film transistor array substrate, it is possible to individually write and read out each pixel and to improve the inspection efficiency as much as possible.

  The control circuit may include N control signal lines that are provided so as to extend in parallel with each other and are respectively connected to N second thin film transistors connected to the inspection terminals.

  According to the above configuration, for example, by inputting a control signal to one of the N control signal lines, one of the N second thin film transistors connected to each inspection terminal is specifically turned on. Become.

  The control circuit is provided in parallel with a plurality of third thin film transistors provided for every two adjacent N second thin film transistors connected to the respective inspection terminals and respectively connected to the adjacent second thin film transistors. Two first control signal lines provided to extend and connected to the two adjacent second thin film transistors, respectively, and two adjacent ones of the plurality of third thin film transistors provided to extend in parallel with each other Two connected second control signal lines may be provided.

  According to the above configuration, for example, when a control signal is input to one of the two first control signal lines, one of the adjacent second thin film transistors is turned on, and the two second control signals Since one of the adjacent third thin film transistors is turned on by inputting a control signal to one of the lines, one of the four adjacent second thin film transistors connected to each inspection terminal is specifically Turns on.

  The control circuit is provided for every two adjacent third thin film transistors, and is connected to each of the adjacent third thin film transistors, and is provided so as to extend in parallel with each other. Two third control signal lines connected to two adjacent ones of the fourth thin film transistors may be provided.

  According to the above configuration, for example, when a control signal is input to one of the two first control signal lines, one of the adjacent second thin film transistors is turned on, and the two second control signals By inputting a control signal to one of the lines, one of the adjacent third thin film transistors is turned on, and by inputting a control signal to one of the two third control signal lines, Since one of the thin film transistors is turned on, one of the eight adjacent second thin film transistors connected to each inspection terminal is specifically turned on.

  Here, as a transistor constituting the control circuit, a transistor for controlling on / off of a current for charging / discharging a charge for the purpose of measuring a pixel defect (hereinafter referred to as a current control type), and A transistor of a type that controls the voltage of the gate of a current control type transistor (hereinafter referred to as a voltage control type) can be used. That is, all of the third thin film transistors and the fourth thin film transistors may be current control type transistors. However, current control type and voltage control type transistors may be used in appropriate combination within the range permitted by the characteristics. Good.

  Each of the connection terminals may be a terminal for connecting an integrated circuit chip.

  According to the above configuration, the probe pins used at the time of array inspection are brought into contact with each inspection terminal instead of each connection terminal for COG mounting, which generally has a narrow pitch between terminals. The effect is specifically demonstrated.

  A plurality of gate lines provided to extend in parallel with each other in a direction intersecting with each of the source lines and connected to the first thin film transistors; and the gate lines are connected to a driving circuit formed monolithically. May be.

  According to the above configuration, since each gate line is connected to the driving circuit formed monolithically, each first thin film transistor is specifically determined by the gate signal supplied from the driving circuit when performing an array inspection. Is turned on.

  The control circuit includes N second switches connected to the respective inspection terminals by switching control of a plurality of positive switch thin film transistors each operating as a positive switch and a plurality of negative switch thin film transistors each operating as a reverse switch. The thin film transistors may be configured to function as AND circuits.

  According to the above configuration, for example, each inspection terminal includes three positive switch thin film transistors that operate as positive switches (“1”) and three negative switch thin film transistors that operate as reverse switches (“0”). Eight adjacent second thin film transistors (AND circuits) connected to, respectively, are “111”, “110”, “101”, “100”, “011”, “010”, “001”, and “000”. Therefore, one of the eight adjacent second thin film transistors connected to each inspection terminal is specifically turned on.

  The thin film transistor array substrate inspection method according to the present invention includes a plurality of pixels provided in a matrix, a plurality of first thin film transistors provided in each of the pixels, and a connection to each of the first thin film transistors. A plurality of auxiliary capacitors, a plurality of source lines provided in parallel to each other between the plurality of pixels and connected to the first thin film transistors, and a plurality of connections connected to the source lines, respectively. A terminal, a plurality of second thin film transistors connected to each of the connection terminals, and N adjacent to each other (N is a natural number of 2 or more) of the plurality of second thin film transistors. A plurality of inspection terminals respectively connected to the thin film transistors and each on / off of the second thin film transistors are controlled to A thin film transistor array substrate inspection method comprising a control circuit for turning on one of N second thin film transistors connected to a child, wherein each inspection is performed by inputting a control signal to the control circuit. A TFT control step for turning on one of the N second thin film transistors connected to the terminal, and each second turned on in the TFT control step by inputting an inspection signal to each of the inspection terminals. Charge is applied to the auxiliary capacitor connected to the first thin film transistor through the connection terminal connected to the thin film transistor, the source line connected to the connection terminal, and the first thin film transistor connected to the source line. Defect detection in which after writing, the charge written in the auxiliary capacitor is read from each inspection terminal to detect the presence or absence of a defect in each pixel Characterized in that it comprises a step.

  According to the above method, the plurality of inspection terminals provided at every N (N is a natural number of 2 or more) adjacent to the plurality of second thin film transistors connected to each connection terminal of the thin film transistor array substrate. And a control circuit for controlling on / off of each second thin film transistor to turn on one of the N second thin film transistors connected to each inspection terminal. By inputting the control signal to the circuit, one of the N second thin film transistors connected to each inspection terminal is turned on, and in the defect detection step, the inspection signal is input to each inspection terminal, so that the TFT A connection terminal connected to each second thin film transistor turned on in the control step, a source line connected to the connection terminal, and a connection to the source line Via the first thin film transistor has been turned on, after writing a charge in the auxiliary capacitor connected to the first thin film transistor, comprising the charge written in the storage capacitance can be read from the test terminal. Therefore, in the defect detection step, it is possible to detect the presence or absence of a defect in each pixel by performing individual writing and reading on each pixel. In addition, since each inspection terminal for inputting / outputting the inspection signal is provided for every N adjacent second thin film transistors, the number of terminals with which the probe pins are brought into contact during the array inspection is reduced, and each inspection terminal is provided. Can be designed to be large, for example, about N times the width of each connection terminal. This makes it possible to reduce the number of probing pins per cell, so the number of cells that are measured simultaneously increases, so the number of times that the probe pins abut on the substrate decreases, and the probe pins that abut each inspection terminal Can be set thicker than before, the strength of the propping pin is increased, the replacement frequency is reduced, and the inspection efficiency is improved. Therefore, in the array inspection of the thin film transistor array substrate, it is possible to individually write and read out each pixel and improve the inspection efficiency as much as possible.

  According to the present invention, a plurality of inspection terminals provided for every N (N is a natural number of 2 or more) adjacent to a plurality of second thin film transistors respectively connected to each connection terminal, and each second thin film transistor And a control circuit for turning on one of the N second thin film transistors connected to each inspection terminal by controlling on / off of each thin film transistor array substrate. Thus, individual writing and reading can be performed, and the inspection efficiency can be improved as much as possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 5 show a first embodiment of a TFT array substrate and an inspection method thereof according to the present invention. Specifically, FIG. 1 is a plan view of the TFT array substrate 30 of the present embodiment. 2 is an enlarged plan view of each pixel of the TFT array substrate 30, and FIG. 3 is a cross-sectional view of the TFT array substrate 30 taken along line III-III in FIG.

  As shown in FIGS. 1 and 2, the TFT array substrate 30 is connected to each of the plurality of pixels P provided in a matrix, the pixel electrode 18 provided for each pixel P, and each pixel electrode 18. Between the plurality of first TFTs 5 a, the plurality of auxiliary capacitors 3 connected to the respective first TFTs 5 a, the plurality of source lines 16 a provided so as to extend in parallel between the pixel electrodes 18, and the pixel electrodes 18. Are provided with a plurality of capacitance lines 14b provided so as to extend in parallel to each other in a direction orthogonal to the respective source lines 16a, and a plurality of gate lines 14a provided so as to extend in parallel with each other between the capacitance lines 14b. ing.

  Each pixel electrode 18 constitutes a pixel P, which is the minimum unit of an image, and is arranged in a matrix to constitute a display region D for displaying an image.

  As shown in FIGS. 2 and 3, each first TFT 5a includes a semiconductor layer 12a provided on an insulating substrate 10 such as a glass substrate through a base coat film 11, and a gate insulating film provided so as to cover the semiconductor layer 12a. 13, a gate electrode (14a) provided on the gate insulating film 13, a first interlayer insulating film 15 provided to cover the gate electrode (14a), and a first interlayer insulating film 15 A source electrode (16a) and a drain electrode 16b are provided. Further, as shown in FIG. 3, a second interlayer insulating film 17 is provided on the first interlayer insulating film 15 so as to cover the source electrode (16a) and the drain electrode 16b. On the second interlayer insulating film 17, a plurality of pixel electrodes 18 are provided in a matrix as shown in FIG. Here, as shown in FIG. 2, the gate electrode (14a) is a portion where each gate line 14a protrudes laterally. Further, as shown in FIGS. 2 and 3, the source electrode (16a) is a part of each source line 16a, and is a contact hole C1 formed in the laminated film of the gate insulating film 13 and the first interlayer insulating film 15. Is connected to the semiconductor layer 12a. Further, as shown in FIGS. 2 and 3, the drain electrode 16b is connected to the semiconductor layer 12a via a contact hole C2 formed in the laminated film of the gate insulating film 13 and the first interlayer insulating film 15. The pixel electrodes 18 are connected through contact holes C 3 formed in the second interlayer insulating film 17.

  As shown in FIGS. 2 and 3, each auxiliary capacitor 3 includes a semiconductor layer 12a provided on an insulating substrate 10 such as a glass substrate via a base coat film 11, and a gate insulation provided so as to cover the semiconductor layer 12a. A film 13 and a capacitor line 14 b provided on the gate insulating film 13 are provided.

  As shown in FIG. 1, the TFT array substrate 30 is provided with a gate driver 26 that is monolithically formed with each gate line 14a connected to the left side in the drawing, and each source line 16a is connected to the lower side in the drawing. A mounting region 28 on which a bare chip of an integrated circuit chip functioning as a source driver is mounted, and a plurality of input terminals 27 drawn from the gate driver 26 and the mounting region 28 are provided.

  Here, FIG. 4 is a plan view of the mounting region 28 of the TFT array substrate 30, and FIG. 5 is a cross-sectional view of the TFT array substrate 30 along the line V-V in FIG.

  In the mounting region 28, as shown in FIG. 4, a plurality of connection terminals 21 connected to the end portions of the respective source lines 16a and a plurality of second TFTs 5b connected to the respective connection terminals 21 are adjacent to each other. A plurality of inspection terminals 23 provided for each of the second TFTs 5b and respectively connected to the eight second TFTs 5b, and eight second TFTs 5b provided to extend in parallel with each other and connected to the inspection terminals 23 Eight control signal lines 16e connected to each other are provided. Here, each control signal line 16e is a control circuit 25a that controls on / off of each second TFT 5b to turn on one of the eight second TFTs 5b connected to each inspection terminal 23. Each control signal line 16e has an input terminal 22 at its end.

  As shown in FIGS. 4 and 5, each second TFT 5b includes a semiconductor layer 12b provided on the insulating substrate 10 via a base coat film 11, a gate insulating film 13 provided so as to cover the semiconductor layer 12b, a gate The gate electrode 14d provided on the insulating film 13, the first conductive layer 14c connected to each connection terminal 21, the second conductive layer 14e connected to the common inspection terminal 23, the gate electrode 14d, the first conductivity A first interlayer insulating film 15 provided so as to cover the layer 14c and the second conductive layer 14e, and a source electrode 16c and a drain electrode 16d provided on the first interlayer insulating film 15 are provided. Here, the gate electrode 14d is connected to each control signal line 16e through a contact hole C8 formed in the first interlayer insulating film 15, as shown in FIG. The source electrode 16 c is connected to the semiconductor layer 12 b through a contact hole C 5 formed in the laminated film of the gate insulating film 13 and the first interlayer insulating film 15 and is formed in the first interlayer insulating film 15. The second conductive layer 14e is connected via the contact hole C7. Further, the drain electrode 16 d is connected to the semiconductor layer 12 b through a contact hole C 4 formed in the laminated film of the gate insulating film 13 and the first interlayer insulating film 15 and is formed in the first interlayer insulating film 15. The contact hole C6 is connected to the first conductive layer 14c.

  Each connection terminal 21 is provided so as to overlap a plurality of bumps arranged on the bottom surface of the bare chip mounted in the mounting region 28. The width of each inspection terminal 23 is designed to be about 8 times the width of each connection terminal 21 (for example, the pitch between terminals is 300 μm to 500 μm). In addition, each connection terminal 21, each input terminal 22, and each test | inspection terminal 23 are the metal conductive film which comprises each gate line 14a etc., the metal conductive film which comprises each source line 16a, etc., and each pixel electrode 18, for example. It is comprised by the laminated film of the transparent conductive film to comprise.

  The TFT array substrate 30 having the above configuration includes an active matrix driving type liquid crystal display together with a counter substrate (not shown) having a color filter layer and a common electrode, and a liquid crystal layer (not shown) sealed between the two substrates. Configure the panel.

  Next, a method for manufacturing the TFT array substrate 30 will be described with an example.

  First, a base coat film 11 is formed by forming a silicon oxide film on the entire substrate of the insulating substrate 10 such as a glass substrate by a plasma CVD (Chemical Vapor Deposition) method.

  Subsequently, after the base coat film 11 is formed, an amorphous silicon film is formed on the entire substrate by plasma CVD using disilane or the like as a source gas, and then subjected to heat treatment such as laser light irradiation to form a polysilicon film. Transforms into Thereafter, the polysilicon film is patterned by photolithography to form semiconductor layers 12a and 12b.

  Further, a gate insulating film 13 is formed by forming a silicon oxide film over the entire substrate on which the semiconductor layers 12a and 12b are formed by a plasma CVD method.

  Then, a tantalum nitride film and a tungsten film are sequentially formed on the entire substrate on the gate insulating film 13 by sputtering, and then patterned by the PEP technique to form gate lines (gate electrodes) 14a and 14d, and capacitor lines 14b. First conductive layer 14c and second conductive layer 14e are formed.

  Subsequently, using the gate electrodes (14a) and 14d as a mask, the semiconductor layers 12a and 12b are doped with phosphorus or boron through the gate insulating film 13, and a channel region is formed on the portion overlapping the gate electrodes 14a and 14d, and on the outside thereof. A source region and a drain region are formed, and then heat treatment is performed, and activation of doped phosphorus or boron is performed. Note that a region overlapping with the capacitor line 14b of the semiconductor layer 12a is separately doped with phosphorus or boron before forming the capacitor line 14b.

  Further, a silicon nitride film and a silicon oxide film are sequentially formed on the entire substrate on which the gate lines (gate electrodes) 14a and 14d, the capacitor line 14b, the first conductive layer 14c, and the second conductive layer 14e are formed by plasma CVD. A first interlayer insulating film 15 is formed by film formation.

  Thereafter, the first interlayer insulating film 15 and the laminated film of the gate insulating film 13 and the first interlayer insulating film 15 are partially etched away to form contact holes C1, C2, C4 to C8.

  Then, a titanium film, an aluminum film, and a titanium film are sequentially formed on the entire substrate on the first interlayer insulating film 15 by sputtering, and then patterned by photolithography to form source lines (source electrodes) 16a and 16c. The drain electrodes 16b and 16d and the control signal lines 16e are formed.

  Subsequently, heat treatment is performed to hydrogenate the semiconductor layers 12a and 12b to terminate the dangling bonds.

  Further, an acrylic resin or the like is applied to the entire substrate on which the source lines (source electrodes) 16a and 16c, the drain electrodes 16b and 16d, and the control signal lines 16e are formed by a spin coating method. Form.

  Thereafter, the second interlayer insulating film 17 is partially removed by etching to form a contact hole C3.

  Finally, an ITO (Indium Tin Oxide) film is formed by sputtering on the entire substrate on which the second interlayer insulating film 17 is formed, and then patterned by photolithography to form the pixel electrode 18.

  As described above, the TFT array substrate 30 can be manufactured.

  Next, an inspection method for the TFT array substrate 30 will be described. Note that the inspection method of this embodiment includes a TFT control step and a defect detection step.

<TFT control step>
After a plurality of probe pins are brought into contact with each input terminal 22 and each inspection terminal 23, a control signal is input to one of eight input terminals 22 (see FIG. 4) via each probe pin. Accordingly, one of the eight second TFTs 5b connected to each inspection terminal 23 is turned on. In FIG. 4, the input terminals 22 are illustrated to be small due to space limitations. However, it is preferable that the input terminals 22 be arranged at approximately equal intervals in consideration of the balance with the pitch of the inspection terminals 23. The area outside the mounting area 28 may be designed to be relatively large as long as the space to be arranged allows.

<Defect detection step>
Connection terminals connected to the second TFTs 5b that are turned on by inputting inspection source signals to the inspection terminals 23 via the probe pins with respect to the TFT array substrate 30 on which the TFT control step has been performed. 21, the source line 16 a connected to the connection terminal 21, and the first TFT 5 a connected to the source line 16 a and turned on by a gate inspection signal from the gate driver 26. After the charge is written in the auxiliary capacitor 3, the charge written in the auxiliary capacitor 3 is read to detect the presence or absence of a defect in each pixel P. Here, in the region where there is no defective pixel, the amount of charge read out by each pixel P is detected almost uniformly, and in the region where there is no defective pixel, the amount of charge of the defective pixel is equal to the amount of charge of each surrounding pixel P Detected differently. Therefore, the presence / absence, position, and nature of the defect can be identified by the relative value of the detected charge amount.

  As described above, the TFT array substrate 30 can be inspected.

  As described above, according to the TFT array substrate 30 and the inspection method thereof according to the present embodiment, a plurality of inspections provided for every eight adjacent second TFTs 5b connected to the connection terminals 21 respectively. Eight control signal lines 16e are provided as a control circuit 25a for controlling on / off of the terminal 23 and each of the second TFTs 5b to turn on one of the eight second TFTs 5b connected to each inspection terminal 23. Therefore, in the TFT control step, by inputting a control signal to each control signal line 16e, one of the eight second TFTs 5b connected to each inspection terminal 23 is turned on. In the defect detection step, By inputting an inspection source signal to each inspection terminal 23, the connection terminal 21 connected to each second TFT 5b turned on in the TFT control step, and its connection The charge is written in the auxiliary capacitor 3 connected to the first TFT 5a through the source line 16a connected to the terminal 21 and the first TFT 5a in the on state connected to the source line 16a, and then the auxiliary capacitor 3 The written charge can be read out. Therefore, in the defect detection step, it is possible to detect the presence / absence of a defect in each pixel P by individually writing and reading out each pixel P. Further, since each inspection terminal 23 for inputting / outputting the inspection source signal is provided for every adjacent eight of the plurality of second TFTs 5b, the number of terminals with which the probe pins are brought into contact during the array inspection is reduced, and each inspection terminal is provided. 23 can be designed to be as large as about eight times the width of each connection terminal 21, for example. As a result, the number of times the probe pins are brought into contact with each other is reduced, and the probe pins that are brought into contact with the respective inspection terminals can be set to be thicker than in the prior art, so that the inspection efficiency can be improved. Therefore, in the array inspection of the TFT array substrate, individual writing and reading can be performed on each pixel, and the inspection efficiency can be improved as much as possible.

  Further, in the present embodiment, the configuration in which the eight connection terminals 21 are aggregated into one inspection terminal 23 is exemplified, but the present invention has one connection terminal of N (N is a natural number of 2 or more). It can be applied to a configuration in which the inspection terminals are aggregated.

<< Embodiment 2 of the Invention >>
FIG. 6 is a plan view of the control circuit 25b constituting the TFT array substrate of the present embodiment. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same part as FIGS. 1-5, and the detailed description is abbreviate | omitted.

  In the first embodiment, the eight control signal lines 16e are illustrated as the control circuit 25a. However, in the present embodiment, the two first control signal lines 16ea and the two second control signals are used as the control circuit 25b. A line 16eb, two third control signal lines 16ec, a plurality of third TFTs 5c, and a plurality of fourth TFTs 5d are illustrated.

  Specifically, as shown in FIG. 6, the mounting region 28 is provided as the control circuit 25 b for every two adjacent two of the eight second TFTs 5 b aggregated in each inspection terminal 23, and each adjacent second TFT 5 b. The plurality of third TFTs 5c connected to the source electrode 16c through the second conductive layer 14e, respectively, and the gate electrodes 14d of the two adjacent second TFTs 5b are provided so as to extend in parallel with each other. Two first control signal lines 16ea connected to each other and two second control signals provided so as to extend in parallel with each other and respectively connected to two adjacent gate electrodes 14d of the plurality of third TFTs 5c. The signal line 16eb is provided for every two adjacent third TFTs 5c, and the drain electrode 16d of each of the adjacent third TFTs 5c has a second A plurality of fourth TFTs 5d connected to the drain electrode 16d through the conductive layer 14f and the source electrode 16c connected to the inspection terminal 23 through the fourth conductive layer 14g are provided so as to extend in parallel with each other. Two third control signal lines 16ec connected to two adjacent gate electrodes 14d of the plurality of fourth TFTs 5d. Each control signal line 16ea-ec is provided with input terminals 22a-22c at its ends. The configuration of each third TFT 5c and each fourth TFT 5d is substantially the same as the configuration of each second TFT 5b described in the first embodiment. The third conductive layer 14f connecting each third TFT 5c and each fourth TFT 5d and the fourth conductive layer 14g connecting each fourth TFT 5d and each inspection terminal 23 are formed of the same material in the same layer as the gate electrode 14d. Is done.

  When inspecting the TFT array substrate of this embodiment, in the TFT control step, a plurality of probe pins are brought into contact with the input terminals 22a to 22c and the inspection terminals 23, respectively, and then the input terminals 22a to 22c. By inputting a control signal to one of 22c via each probe pin, a control signal is input to one of the two first control signal lines 16ea, and one of the adjacent second TFTs 5b is turned on. A control signal is input to one of the two second control signal lines 16eb, one of the adjacent third TFTs 5c is turned on, and a control signal is input to one of the two third control signal lines 16ec. Since one of the adjacent fourth TFTs 5d is turned on, one of the eight adjacent second TFTs 5b connected to each inspection terminal 23 is turned on.

  As described above, according to the TFT array substrate and the inspection method thereof according to the present embodiment, a plurality of inspection terminals provided for every eight adjacent second TFTs 5b connected to the connection terminals 21 respectively. 23 and two first control signal lines 16ea, 2 as control circuits for controlling on / off of each of the second TFTs 5b to turn on one of the eight second TFTs 5b collected at each inspection terminal 23. Since the second control signal line 16eb, the second third control signal line 16ec, the plurality of third TFTs 5c, and the plurality of fourth TFTs 5d are provided, in the array inspection of the TFT array substrate, as in the first embodiment. In addition to performing individual writing and reading with respect to each pixel, it is possible to improve the inspection efficiency as much as possible.

<< Embodiment 3 of the Invention >>
FIG. 7 is a plan view of the control circuit 25c constituting the TFT array substrate of the present embodiment.

  In the second embodiment, the current control type second TFTs 5b and the control circuit 25b are exemplified as the current control type third TFTs 5c and the fourth TFTs 5d, and the control signal lines 16ea, 16eb and 16ec. In the embodiment, as shown in FIG. 7, as the current control type second TFT 5x and the control circuit 25c, the voltage control type positive switch TFT 5np and the reverse switch TFT 5pn, and control signal lines 14hx, 14hy for connecting them, 14hz, 14na, 14nb, 14pa, 14pb, 16fxn, 16fyn, 16fzn, 16fxp, 16fyp, 16fzp, 16fa, 16fb, 16fd, 16x, 16y and 16z are exemplified. The control signal lines 14hx, 14hy, 14hz, 14na, 14nb, 14pa, and 14pb are formed of the same material in the same layer as the gate electrode 14d described in the first embodiment. The control signal lines 16fxn, 16fyn, 16fzn, 16fxp, 16fyp, 16fzp, 16fa, 16fb, 16fd, 16x, 16y, and 16z are formed of the same material in the same layer as the source electrode 16c described in the first embodiment. .

  Specifically, as shown in FIG. 7, the control circuit 25c functions as each of the second TFTs 5x functioning as eight AND circuits aggregated in the respective inspection terminals 23, and as the three positive switch TFTs 5np and its NOT circuit. The switch is controlled by three reverse switch TFTs 5pn. That is, the eight AND circuits are respectively operated by the forward switch (“1”) and the reverse switch (“0”) via the input terminals 22Vh (on) and 22Vl (off) connected to the operation power supply. It is configured to be controlled to “111”, “110”, “101”, “100”, “011”, “010”, “001”, and “000”.

  When inspecting the TFT array substrate of the present embodiment, a plurality of probe pins are brought into contact with the input terminals 22x to 22z, 22Vh and 22Vl, and the inspection terminals 23, and then the input terminals 22x to 22x. By inputting a predetermined combination of control signals to each of 22z, 22Vh and 22Vl via each probe pin, one of the eight second TFTs 5x is operated by the AND circuit, and the inspection terminal 23 and the eight connection terminals 21 are connected. A predetermined one is conducted on a one-to-one basis.

  As described above, according to the TFT array substrate of the present embodiment and the inspection method thereof, a plurality of inspection terminals provided for every eight adjacent second TFTs 5x connected to the connection terminals 21 respectively. 23 and a control circuit 25c for controlling on / off of each of the second TFTs 5x to turn on one of the eight second TFTs 5x integrated in each of the inspection terminals 23, a voltage control type forward switch TFT 5np, a reverse switch Since the TFT 5 pn and each control signal line for connecting them are provided, in the array inspection of the TFT array substrate, as in the first and second embodiments, individual writing and reading are performed on each pixel and the inspection is performed. Efficiency can be improved as much as possible.

Moreover, in this embodiment and the said Embodiment 2, although the structure which aggregates the eight connection terminals 21 to the one test | inspection terminal 23 was illustrated, this invention makes two connection terminals into one test | inspection terminal. N (maximum number of N) within the range allowed by the device characteristics and the space to be arranged, such as 4 connection terminals as 1 inspection terminal, 16 connection terminals as 1 inspection terminal, and so on. Can be applied to a configuration in which 2 ⁿ and n are natural numbers) are aggregated into one inspection terminal.

  In addition, according to each of the above embodiments, the electrical array inspection enables high-accuracy and quantitative inspection at high speed. Therefore, the manufacturing process status of the TFT array substrate can be accurately managed, and process feedback can be performed. By correcting the substrate, the manufacturing yield can be improved, and the quality can be improved and the cost can be reduced.

  Moreover, according to each said embodiment, as a result of reducing the number of pins to probe per cell, the number of cell units which can be measured simultaneously can be increased from 2 cells to about 8 cells, for example. Furthermore, the processing that had to be performed 120 times of probing operation (probe pin contact operation) per substrate can be reduced to 30 times of probing operation. The hit processing time can be shortened, for example, from about 20 minutes to about 6 minutes.

  Further, according to each of the above embodiments, since the number of probe pin contact (contact) decreases, wear of the pin tip can be suppressed, the downtime of the manufacturing equipment is shortened, and the operating rate is also increased. Can contribute.

  Further, in each of the above embodiments, the configuration in which the control circuits 25a to 25c for inspection are directly connected to the connection terminals 23 to which the bumps of the bare chip are connected is illustrated, but the present invention is not limited to this, For example, an inspection control circuit for writing and reading out a specific pixel may be provided in a region that is not used in normal driving of the TFT array substrate, such as a non-input side region.

  In each of the above embodiments, a TFT array substrate having a COG mounting structure has been exemplified. However, the present invention is unidirectional by signal conversion such as a digital-to-analog converter (DAC) as in digital full monolithic driving. Therefore, the present invention can also be applied to a display device that can transmit a signal only and cannot output output information for inspection from an input terminal for driving.

  As described above, the present invention can perform individual writing and reading with respect to each pixel and improve the inspection efficiency as much as possible in the TFT array substrate where the pitch between the connection terminals is narrow. This is useful for inspection of a TFT array substrate having a COG mounting structure.

2 is a plan view of a TFT array substrate 30 according to Embodiment 1. FIG. 4 is an enlarged plan view of each pixel of the TFT array substrate 30. FIG. FIG. 3 is a cross-sectional view of a TFT array substrate 30 taken along line III-III in FIG. 2. 4 is a plan view of a mounting area 28 of the TFT array substrate 30. FIG. FIG. 5 is a cross-sectional view of the TFT array substrate 30 taken along the line VV in FIG. 4. 6 is a plan view of a control circuit 25b that constitutes a TFT array substrate according to Embodiment 2. FIG. It is a top view of the control circuit 25c which comprises the TFT array substrate which concerns on Embodiment 3.

Explanation of symbols

P Pixel 3 Auxiliary capacitor 5a First TFT
5b 2nd TFT
5c 3rd TFT
5d 4th TFT
5np positive switch TFT
5pn reverse switch TFT
5x 2nd TFT (AND type TFT)
14a gate lines 14hx to 14hz, 14na, 14nb, 14pa, 14pb control signal line 16a source line 16e control signal line 16ea first control signal line 16eb second control signal line 16ec third control signal line 16fxn, 16fyn, 16fzn, 16fxp, 16 fyp, 16 fzp, 16 fa, 16 fb, 16 fd, 16 x, 16 y, 16 z Control signal line 18 Pixel electrode 21 Connection terminal 22, 22 a to 22 c, 22 Vh, 22 Vl, 22 x to 22 z Input terminal 23 Inspection terminal 25 a to 25 c Control circuit 26 Drive circuit 28 Mounting Area (Integrated Circuit Chip)
30 TFT array substrate

Claims (8)

A plurality of pixels provided in a matrix;
A plurality of first thin film transistors provided in each of the pixels;
A plurality of auxiliary capacitors respectively connected to the first thin film transistors;
A plurality of source lines provided between the plurality of pixels so as to extend in parallel with each other and connected to the first thin film transistors;
A thin film transistor array substrate comprising a plurality of connection terminals respectively connected to the source lines,
A plurality of second thin film transistors respectively connected to the connection terminals;
A plurality of inspection terminals provided for every N adjacent N (N is a natural number of 2 or more) of the plurality of second thin film transistors, and connected to each of the adjacent second thin film transistors;
A thin film transistor array comprising: a control circuit for controlling on / off of each of the second thin film transistors to turn on one of the N second thin film transistors connected to each of the inspection terminals. substrate. The thin film transistor array substrate according to claim 1,
The control circuit includes N control signal lines provided to extend in parallel to each other and connected to N second thin film transistors connected to the respective inspection terminals. . The thin film transistor array substrate according to claim 1,
The control circuit is provided in parallel with a plurality of third thin film transistors provided for every two adjacent N second thin film transistors connected to the respective inspection terminals and respectively connected to the adjacent second thin film transistors. Two first control signal lines provided to extend and connected to the two adjacent second thin film transistors, respectively, and two adjacent ones of the plurality of third thin film transistors provided to extend in parallel with each other A thin film transistor array substrate comprising two connected second control signal lines. In the thin film transistor array substrate according to claim 3,
The control circuit is provided for every two adjacent third thin film transistors, and is connected to each of the adjacent third thin film transistors, and is provided so as to extend in parallel with each other. A thin film transistor array substrate comprising two third control signal lines respectively connected to two adjacent four fourth thin film transistors. The thin film transistor array substrate according to claim 1,
Each of the connection terminals is a terminal for connecting an integrated circuit chip. The thin film transistor array substrate according to claim 1,
A plurality of gate lines provided to extend in parallel to each other in the direction intersecting each source line and connected to each of the first thin film transistors;
Each of the gate lines is connected to a driving circuit formed monolithically. The thin film transistor array substrate according to claim 1,
The control circuit includes N second switches connected to the inspection terminals by switching control of a plurality of forward switch thin film transistors each operating as a forward switch and a plurality of reverse switch thin film transistors each operating as a reverse switch. A thin film transistor array substrate, wherein the thin film transistors each function as an AND circuit. A plurality of pixels provided in a matrix;
A plurality of first thin film transistors provided in each of the pixels;
A plurality of auxiliary capacitors respectively connected to the first thin film transistors;
A plurality of source lines provided between the plurality of pixels so as to extend in parallel with each other and connected to the first thin film transistors;
A plurality of connection terminals respectively connected to the source lines;
A plurality of second thin film transistors respectively connected to the connection terminals;
A plurality of inspection terminals provided for every N adjacent N (N is a natural number of 2 or more) of the plurality of second thin film transistors, and connected to each of the adjacent second thin film transistors;
A method for inspecting a thin film transistor array substrate, comprising: a control circuit for controlling on / off of each of the second thin film transistors to turn on one of N second thin film transistors connected to each of the inspection terminals. And
A TFT control step of turning on one of the N second thin film transistors connected to each of the inspection terminals by inputting a control signal to the control circuit;
By inputting an inspection signal to each inspection terminal, a connection terminal connected to each second thin film transistor turned on in the TFT control step, a source line connected to the connection terminal, and a connection to the source line The charge is written in the auxiliary capacitor connected to the first thin film transistor through the turned-on first thin film transistor, and then the charge written in the auxiliary capacitor is read from each of the inspection terminals. And a defect detection step for detecting the presence or absence of the defect of the thin film transistor array substrate.

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