JP2009194676A - Programmable logic device, construction method thereof, and using method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid propagation delay of data by enabling discrete wiring between basic logic blocks, and to achieve reduction of the area of PLD by allowing SRAM of the basic logic block to be a single port SRAM. <P>SOLUTION: The basic logic block constituting PLD is provided with: additional wiring of address data pair where input/output data line for logic circuit is distributed to each bit; an address line; and a data line. The additional wiring can be added only to a wanted basic logic block as required. The address data pair, address line, and data line may be combined to constitute a single PLD. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a programmable logic device, a construction method thereof, and a usage method thereof. In particular, each basic logic block can also operate as a memory element. The present invention relates to a programmable logic device that enables wiring, a construction method thereof, and a usage method thereof.

  With reference to FIG. 20, the structure of a general programmable logic device (Programmable Logic Device: hereinafter referred to as PLD) using conventional technology will be described. FIG. 20 shows an example of the most common island-style FPGA (Field Programmable Logic Array) 100, which includes a logic element LB, connection elements, switch elements SB and CB, and an input / output element IOB.

  The logic element LB is a programmable element that realizes a combinational circuit, and the logic element LB that realizes a sequential circuit includes a flip-flop circuit therein. As a method for realizing the logical element LB, there are a product term method, a LUT (Look Up Table) method, a MUX (MLUTiplexer) method, and the like. For example, the LUT method is a method in which a truth table of an arbitrary logical function is held in an SRAM (Static Random Access Memory), and output is performed by referring to the truth table according to input.

  The input / output element IOB is a component that serves as an interface between the input / output of the device and the logical element LB.

  The connection element is a component for connecting the logical element LB and the input / output element IOB. The connection elements are wiring channels and switch elements CB and SB, and the logic element LB and the input / output element IOB are connected via this connection element. The wiring channel is a wiring arranged and fixed one-dimensionally, two-dimensionally or hierarchically. The switch element CB is an element that is set between the logic block LB and the wiring channel, and the switch element SB is an element that sets the vertical and horizontal wiring at a portion where the vertical and horizontal wirings intersect.

  Such an FPGA 100 includes an external memory M for writing logic circuit construction information. When constructing a logic circuit, construction information is read from the external memory M, and the read construction data is transferred to the FPGA 100. That is, the FPGA 100 as described above has a problem that the SRAMs constituting the LUT cannot be efficiently used as a single memory in spite of being configured based on the SRAM.

  On the other hand, a memory-based PLD (MPLD) has been proposed as a PLD having both a memory function and a logic circuit function.

  FIG. 21 is a diagram showing an outline of a conventional MPLD 150.

  As shown in FIG. 21A, the MPLD 150 introduces a basic logic block LB ′ that functions as both a memory and an LUT, and devise its arrangement and wiring, thereby eliminating the need for multiplexers and switch elements. Equivalent functions can be realized.

  Specifically, the logical input data lines and the logical output data lines connected to each basic logical block LB ′ are distributed in units of 1 bit to form adjacent address lines and data line pairs as adjacent basic logical blocks LB. 'Connect with each other. As a result, the basic logic block LB ′ operates as a reconfiguration unit, and further, can be used as a signal switch by connecting the LUT, memory, and each basic logic block LB ′ with the alternate wiring shown in FIG. Is available.

  When the MPLD 150 is operated as a memory, it can be operated by the same operation as a conventional memory. When operating as a logic circuit, each basic logic block LB 'can be operated by storing a truth table that acts as a desired circuit or switch signal.

As a result, the MPLD 150 can collectively use all the basic logic blocks LB ′ as one memory as shown in FIG. 21B, and can also operate as a logic circuit (see, for example, Non-Patent Document 1). .)
Yoshihara, 4 others, "Implementation example of a memory (MPLD) that also operates as a reconfigurable device", Shingaku Technique, Hiroshima City University Graduate School, September 2007, RECONF 2007-16, pp. 7-12

  The conventional MPLD shown in FIG. 21 has the following problems.

  First, since the wiring between the basic logical blocks LB ′ is connected only to the adjacent basic logical block LB ′, there is a problem that a propagation delay is large when data is transferred to the separated basic logical block LB ′. It was.

  Second, since the wiring between the basic logical blocks LB ′ is connected only to the adjacent basic logical block LB ′, for example, when connection of a sequential circuit is necessary, the wiring is connected outside the MPLD 150. There was a problem that versatility could not be improved.

  Third, although the operation as a logic circuit and the operation as a memory are not used at the same time, a 2-port SRAM is used as the basic logic block LB ′, so that the area is almost twice as large as that of a normal SRAM. End up. For this reason, there is a problem in that the area of the entire MPLD also increases.

  The present invention has been made in view of such problems, and firstly, it is a programmable logic device having a plurality of basic logic blocks and having a plurality of logic circuits configured according to configuration information. The block includes storage means, a memory address line, a memory data input / output line, a logic address line, and a logic data line. The logic address line and the logic data line are connected to the logic input line. According to the number of bits of output data, each bit is distributed as a unit address line and unit data line, and the unit address line and unit data line are paired and wired in different directions from the basic logic block for each pair. The unit address line and the unit data line are closer to the memory address line and the memory data input / output line. The logic blocks are connected to form a logic block group including logic circuit elements and memory elements, and at least one of the basic logic blocks is solved by having an additional unit address line and / or an additional unit data line. Is.

  Configuration information for realizing a desired logic circuit is held in the storage unit in the first area of the basic logic block group, and the storage unit in the second area of the basic logic block group stores the first information. Switch information for selectively switching the basic logic blocks in the area is retained, and the basic logic block group becomes the logic circuit element.

  Desirable data is held in a third area of the basic logic block group or a non-operating area as the logic circuit element, and at least a part of the basic logic block group is a memory element. To do.

  Further, the additional unit address line and / or the additional unit data line connect the basic logic blocks to each other.

  In addition, a storage element is connected to the additional unit address line and / or the additional data line.

  The storage means is a one-port memory, and the basic logic block switches a memory address line and the unit address line and assigns them to an input port of the first port memory; A second wiring switch that switches between the data input / output line for memory and the unit data line and assigns it to the output port of the one-port memory, and operates as a logic circuit by the first wiring switch and the second wiring switch. The unit address line and the unit data line are sometimes selected, and the memory address line and the memory data input / output line are selected during a memory operation.

  The logical block group includes a first basic logical block having a 1-port memory as the storage means and a second basic logical block having a multi-port memory as the storage means. .

  Secondly, it has a storage means, a memory address line, a memory data input / output line, a logic address line, and a logic data line, and connects basic logic blocks to each other to obtain configuration information. A method of constructing a programmable logic device that constructs a plurality of logic circuits according to the above, wherein the port of the storage means is assigned to the memory address line, memory data input / output line, logic address line and logic data line. And the logical address line and the logical data line are distributed in 1-bit units according to the number of bits of the logical input / output data to form unit address lines and unit data lines. Pairing, wiring each of the pairs in a different direction from the basic logic block, and at least one of the The step of connecting an additional unit address line and / or an additional unit data line to the logical block, the memory address line and the memory data input / output line, and the unit address line and the unit data line closer to each other Connecting the basic logic block and connecting the additional unit address line and / or the additional unit data line to the basic logic block or another element in the basic logic block group to connect a logic circuit element and a memory element. And a step of configuring the provided logical block group.

  A first wiring switch that uses a one-port memory as the storage means, switches the memory address line and the unit address line to the basic logic block, and assigns them to an input port of the first port memory; A second wiring switch that switches between the memory data input / output line and the unit data line and is assigned to the output port of the one-port memory is arranged.

  Third, a basic logic block is constituted by the storage means, the memory address line, the memory data input / output line, the logic address line, and the logic data line, and the port of the storage means is the memory address. Lines and memory data input / output lines, logic address lines and logic data lines, and each of the logic address lines and logic data lines is in units of 1 bit according to the number of bits of logic input / output data. Are divided into unit address lines and unit data lines, and the unit address lines and unit data lines are wired in different directions from the basic logic block for each pair, and the memory address lines and the memory data An input / output line and the basic logic block closer to the unit address line and the unit data line are connected to each other to provide a logic circuit. And an additional unit address line and / or an additional unit data line are connected to at least one basic logical block, and the additional unit address line and / or the additional unit data line are connected to at least one basic logical block. A method of using a programmable logic device in which a unit data line is connected to the basic logic block or other elements in the basic logic block group that are not adjacent to each other, using the memory address line and the memory data input / output line A step of holding configuration information for realizing a desired logic circuit in the storage means in the first area of the basic logic block group, and a logic block group using the memory address line and memory data input / output line The basic logical block in the first area is selectively cut into the storage means in the second area. Holding the switch information to be switched, performing the logic circuit operation using the logic address line and the logic data line, and using the memory address line, a third of the basic logic block group. And holding a desired data in a non-operating area as the logic circuit element and operating at least a part of the basic logic block group as a memory.

  Further, a first port memory is used as the storage means of the basic logic block, and the first wiring assigned to the input port of the first port memory by switching the memory address line and the unit address line to the basic logic block. A switch, and a second wiring switch that switches between the memory data input / output line and the unit data line and assigns to the output port of the one-port memory, the first wiring switch, and the second wiring switch. The logic circuit operation or the memory operation is performed by operating a wiring switch.

  According to the present invention, the following effects can be obtained.

  First, by connecting an additional unit address line and / or unit data line to a desired basic logic block, other wiring is added in addition to the adjacent wiring for wiring between adjacent basic logic blocks. Can do. Thereby, for example, it is possible to wire the separated basic logic blocks.

  By adding a unit address line and a unit data line in each basic logic block as a pair, the number of paths through which data is transmitted in both directions is increased, and versatility is improved.

  On the other hand, when unit address lines and unit data lines are added in pairs, the area of the entire MLUT increases as the number of pairs of unit address lines and unit data lines increases. In such a case, the number of unit address line and unit data line pairs for wiring the separated basic logic blocks selectively to a desired basic logic block is ensured.

  As described above, by limiting the basic logical blocks to which the additional wiring is connected, an increase in the area of the entire MLUT can be suppressed. As a result, wiring between MLUTs separated in the MPLD can be realized while maintaining the symmetry and homogeneity of the adjacent wiring that facilitates handling in CAD, and a highly versatile MPLD can be realized.

  Furthermore, adjacent basic logic blocks can be connected by an additional wiring.

  Second, a storage element (element) such as a flip-flop circuit can be added by connecting an additional unit address line and / or unit data line to a desired basic logic block. Thereby, it is possible to function as a sequential circuit. Alternatively, it is possible to store the calculation result during the logic circuit operation.

  Thus, it is possible to connect a flip-flop circuit or a latch circuit in a region close to a desired basic logic block while maintaining the symmetry and homogeneity of the adjacent wiring that facilitates handling in CAD.

  Third, one or both of the additional unit address lines and unit data lines are connected to only the necessary basic logic blocks as needed, thereby suppressing the increase in the entire area and highly versatile. MPLD can be provided.

  If a unit address line and a unit data line are added to the basic logic block, bidirectional wiring is increased and versatility is improved. However, as the number of unit address line and unit data line pairs increases, the entire MLUT increases. Increases the area. Therefore, if necessary, one of the unit address line and the unit data line for realizing wiring with the separated MLUT is selected and wired. That is, the direction in which data is propagated is fixed, but the area increase can be suppressed.

  Further, by limiting the basic logical block to which additional wiring for realizing wiring with the separated MLUT is limited, an increase in the area of the entire MLUT can be suppressed.

  Fourth, the basic logic block includes a one-port memory and two wiring switching units that switch the input / output memory port for logic circuit operation and memory (reconfiguration) operation, thereby reducing the area of the MPLD. Can be reduced.

  In MPLD, even when a two-port memory is used for the basic logic block, the logic circuit operation and the memory (reconfiguration) operation are not performed simultaneously. Therefore, the area of the MPLD can be reduced by using a 1-port memory instead of the 2-port memory, and switching the logic circuit operation port and the memory port (wiring) by a wiring switch. This is particularly effective when the number of unit address line and unit data line pairs is large (the number of bits of data to be handled is large).

  In addition, since the basic logic block using the 1-port memory can separate the memory operation and the logic circuit operation by the wiring switch, it has an advantage that the partial reconfiguration is easier than a normal FPGA.

  The embodiment of the present invention will be described in detail with reference to FIGS.

  The programmable logic device of the present invention is a memory-based programmable logic device (hereinafter referred to as MPLD) 10, and includes a storage means, a memory address line, a memory data input / output line, and a logic address line. A plurality of basic logic blocks 1 composed of logic data lines are interconnected.

  First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic diagram showing the entire MPLD 10.

  The MPLD 10 includes a block group 2 in which a plurality of basic logic blocks 1 are arranged, a row decoder 3, and a column decoder 4.

  Input / output signals of the MPLD 10 are a memory address input signal MA, a memory data input / output signal MD, a logic address signal LI, and a logic data signal LO.

  The memory address input signal MA is an input signal of an address used for reading and writing data in the memory when the MPLD 10 performs a memory operation.

  The memory data input / output signal MD is a signal for exchanging data with the outside of the MPLD 10 when reading and writing data in the memory.

  The logic address signal LI is used when the MPLD 10 is operated as a logic circuit and used when inputting operation data.

  The logic data signal LO is a signal used when the MPLD 10 is operated as a logic circuit and used to output the operation result of the logic circuit.

  The basic logic block 1 of this embodiment includes a memory element and a logic circuit element.

  An operation when the MPLD 10 is used as a memory (memory function) will be described. Similar to a general memory, the memory address line 11 is input to the row decoder 3 and the column decoder 4, the memory address input signal MA (row address input signal) is input from the memory address line 11, and the control signal is input to the row. The word line WL is operated by being input to the decoder 3. Then, the internal bit line BL is operated by the control signal and the row address input signal, and the data is controlled by the column decoder 4. That is, by inputting a row address input signal and a column address input signal, a location for reading or writing is specified, and writing control, reading control, and precharging are respectively performed using the control signal WE, the control signal RE, and the control signal PRE. Control.

  Next, the operation when the MPLD 10 is used as a logic circuit (logic circuit function) will be described. Although not shown here, each basic logic block 1 is connected to the adjacent basic logic block 1 by wiring.

  In order to operate as a logic circuit, a truth table of a signal switch or a logic circuit to be realized is input to each basic logic block 1 using the memory function described above. Next, by inputting the logic address signal LI to the logic address line 13, the operation result (the logic data signal LO) is output from the logic data line 14.

  Next, the basic logic block 1 will be described with reference to FIGS. As will be described in detail later, the basic logic block 1 of the present embodiment functions as a multi-input multi-output LUT (Look Up Table), and is hereinafter referred to as an MLUT (Multi LUT) 1. In the following, an example of 4 inputs / outputs (number of bits N = 4) is shown.

  First, FIG. 2 is a diagram showing input / output of the MLUT 1. The MLUT 1 includes a two-port memory (for example, SRAM (static random access memory)) 15, an address decoder 16 for memory operation, and an address decoder 17 for a logic circuit. Since the address decoder 16 for memory operation can be shared by all MLUTs 1, it is possible to reduce the area of the MLUT1 by configuring it outside the MLUT1.

  The memory address line 11 is connected to the memory input port 18A, the memory data input / output line 12 is connected to the memory input / output port 18D, and the logic address line 13 is connected to the logic input port 19A. The logic data line 14 is connected to the logic output port 19D.

  FIG. 3 is a diagram showing input / output of the 2-port memory 15 in the MLUT 1.

  In this embodiment, the logic address line 13 and the logic data line 14 connected to the MLUT 1 are distributed bit by bit according to the number of bits N (for example, N = 4) of the logic input / output data. Hereinafter, the logical address line 13 and the logical data line distributed for each bit are referred to as a unit address line 130 and a unit data line 140, respectively.

  That is, the logic address line 13 is distributed to the unit address lines 130 (131, 132,..., 13N), and the logic data line 14 is distributed to the unit data lines 140 (141, 142,... 14N). (FIG. 3A).

  Further, one unit address line 130 and one unit data line 140 are paired. This is called an address / data pair AD. As shown in FIG. 3B, the address / data pair AD1 (unit address line 131 and unit data line 141), the address / data pair AD2 (unit address line 132 and unit data line 142), and the address / data pair AD3 ( A unit address line 133 and a unit data line 143) are wired as an address / data pair AD4 (unit address line 134 and unit data line 144) (see FIG. 2).

  FIG. 4 is a diagram illustrating an example of the wiring of the address / data pair AD of the MLUT 1.

  FIG. 4A is a diagram showing one MLUT 1, and FIG. 4B is a diagram showing a part of the MLUT group 1G.

  As shown in FIG. 4A, the address / data pair AD is wired for each pair from the MLUT 1 to another MLUT 1 arranged in a different direction. As an example, address / data pair AD1 (unit address line 131 and unit data line 141), address / data pair AD2 (unit address line 132 and unit data line 142), address / data pair AD3 (unit address line 133 and unit data) Line 143) and address / data pair AD4 (unit address line 134 and unit data line 144) are wired bidirectionally so as to be derived from the left, top, right and bottom of MLUT1 shown in FIG. A memory address line 11 and a memory data input / output line 12 are also wired.

  The memory address line 11 and the memory data input / output line 12 are respectively connected to the first input port 18A and the first output port 18D of the 2-port memory 15, and the unit address lines 131 to 134 and the unit data lines 141 to 144 are connected to each other. Each is connected to the second input port 19A and the second output port 19D of the 2-port memory 15.

  As shown in FIG. 4B, the MLUT1 is mutually connected to the adjacent MLUT1 by the address / data pair AD. The adjacent MLUTs 1 are, for example, four MLUTs 1 that are adjacent to each other in the vertical and horizontal directions with respect to one of the MLUTs 1 arranged in a matrix. Further, even when MLUT1 is not arranged in a matrix (array) form (for example, shifted in the row direction or the column direction), it is connected to four MLUT1 adjacent in the four directions. Hereinafter, the mutual connection with the adjacent MLUT 1 is referred to as a proximity wiring.

  With reference to FIG. 5, the logic circuit operation of the MLUT 1 will be described. 5A is a diagram illustrating an example of a logic circuit to be constructed, FIG. 5B is an example of a truth table, and FIG. 5C is a diagram illustrating an example of data input to and output from the MLUT 1. It is.

  When the logic circuit operates, the logic circuit wiring, that is, the address / data pair AD (solid arrow) is used. In the case of the logic circuit shown in FIG. 5A, it can be expressed by a truth table as shown in FIG. The truth table is stored in the 2-port memory 15 in the MLUT 1 using the memory address line 11 and the memory data input / output line, so that the MLUT 1 can be used as a logic circuit element, and data is stored in the MLUT 1. When input, the result is output with reference to the truth table (FIG. 5C).

  As described above, the MLUT 1 of this embodiment functions as a multi-input multi-output LUT by distributing the logical address line 13 and the logical data line 14 to form an address / data pair AD and wiring them in different directions.

  In MLUT1, since the unit address line is in the input direction with respect to MLUT1, and the unit data line is in the output direction from MLUT1, MLUT1 has directionality by connecting a plurality of address / data pairs AD in different directions. And can function as a switch element.

  With reference to FIG. 6, the switching operation of the MLUT 1 will be described. FIG. 6A is an example of a truth table, FIG. 6B is a diagram illustrating an example of data input to and output from the MLUT 1, and FIG. 6C is a diagram illustrating an overview as a switch element.

  As shown in FIG. 6A, the input / output direction information (switching information) can be expressed by a truth table. In MLUT1, each address / data pair AD has directionality (FIG. 6B). Therefore, for example, a truth table that realizes a logical expression in which the input (A0) and the output (Y1) are equivalent (A0 = Y1) is obtained by using the memory address line 11 and the memory data input / output line 12. By holding the data in the memory 15, the wiring can be connected in the directions of arrows of a solid line, a broken line, a one-dot chain line, and a two-dot chain line. That is, the MLUT 1 can function as a switch element by inputting data (FIG. 6C).

  The memory operation of the MLUT 1 will be described with reference to FIG. FIG. 7 is a diagram illustrating an example of data input to and output from the MLUT 1.

  When used as a memory element, memory wiring (memory address line 11, memory data input / output line 12) is used. By operating the MLUT 1 in a memory, the truth table as a logical element or a switch element is read or rewritten. The truth table can also be used as data.

  With the configuration as described above, the MLUT 1 can include a memory element and a logic circuit element. Unlike the conventional PLD (FIG. 20), the MPLD 10 according to the present embodiment does not require the wiring elements CB and SB. Memory operation and logic circuit operation can be performed as a PLD close to a simple memory.

  That is, using the memory address line 11 and the memory data input / output line 12, the configuration information is written into a desired MLUT 1 and the switching information is written into another MLUT 1. After that, the logic address line 13 is used to operate the basic logic block group (MLUT group) 1G as a logic circuit, and an operation result is output from the logic data line 14.

  This will be specifically described with reference to FIG. FIG. 8 is a diagram showing an example of the configuration of the MPLD 10, and is an enlarged view of a part of the MLUT group 1G shown in FIG. Here, a case where a 4-bit adder is configured as a logic circuit will be described as an example.

  MLUT1 is mutually wired by MLUT1 and address data pair AD (thin arrow) which adjoin each other. The memory address line 11 and the memory data input / output line 12 are shared by each column. In FIG. 7, for example, the leftmost address / data pair AD and the upper left address / data pair AD are connected to the logic address line and logic data line of FIG.

  In order to operate as a logic circuit, first, configuration information and switch information of a logic circuit to be realized in a desired MLUT 1 are input using a memory function.

  That is, a configuration for obtaining a logical sum in the 2-port memory 15 in the MLUT 1 of the first region R1 (for example, the leftmost column) of the MLUT group 1G using the memory address line 11 and the memory data input / output line 12. Hold information (truth table).

  Further, using the memory address line 11 and the memory data input / output line 12, a logic circuit element is selected for the 2-port memory 15 in the MLUT 1 in the second region R2 (for example, the second column from the left) of the MLUT group 1G. A truth table as switch information to be switched automatically is held. For example, a truth table is selected so that the wiring for carrying the addition result of the leftmost column is selected.

  The logic address line 13 and the logic data line 14 (each address / data pair AD) are used to operate as a logic circuit as indicated by a thick arrow. That is, by inputting operation data from the logic address line 13, the MLUT group in the leftmost column (first region R1) and the second column from the left (second region R2) is added and carried logic. The circuit operation is performed, and the operation result is output from the logic data line 14.

  At this time, the MLUT 1 in the third region R3 (for example, the third column from the left and other columns from the left) of the MLUT group 1G is not used for the logic circuit operation. These data can be held and function as a memory element.

  In addition, for example, a region not operating in a logic circuit in the first region R1 or the second region R2 can function as a memory element.

  It is appropriately selected by the designer how to configure the logic circuit or how the switch element functions, more specifically, what truth table is held in which MLUT1.

  On the other hand, in order to operate as a memory element, an operation similar to that of a normal memory is performed. That is, referring again to FIG. 1, a memory address input signal MA is input to the row decoder 3 and the column decoder 4, thereby specifying a memory to be operated, and a memory data input / output signal MD is input as data to be written. Data is read out in the same manner, and data is output from the memory data input / output line. The control signal WE performs write control, the control signal RE performs read control, and the control signal PRE controls precharge.

  The MPLD 10 of the present embodiment can use a part of the MLUT group 1G as a PLD and a function of other areas as a memory without using an external memory. In addition, a logic circuit can be constructed in the same manner as a general memory write operation, and a part of the MLUT group 1G can be easily rewritten partially. Therefore, it is possible to flexibly cope with the increase / decrease of the area as the PLD, and when it is not necessary to use it as the PLD, the whole can function as one memory.

  Further, each MLUT 1 serving as a logic circuit element holds construction information, so that the construction speed can be increased as compared with a conventional PLD that reads construction information from an external memory.

  The basic operation of the MLUT 1 is as described above. In this embodiment, the address / data pair AD or any one of the address line 13 and the data line 14 is added to at least one MLUT 1 of the MLUT group 1G. This will be described with reference to FIGS.

  FIG. 9 is a diagram illustrating an example of data propagation in the MLUT group 1G, where thin arrows indicate address / data pairs, and broken thick arrows indicate how data is propagated.

  For example, when data is propagated from the upper left MLUT 1 to the lower right MLUT 1, depending on the logic circuit to be constructed, it is necessary to pass through a large number of MLUTs 1 as shown by thick arrows.

  Therefore, in the present embodiment, by performing additional wiring on the MLUT 1, wiring with other separated MLUTs (hereinafter, separated wiring) is realized, and propagation delay is suppressed.

  FIG. 10 is a diagram illustrating a part of the MLUT group 1G in which additional wiring is performed.

  As described above, each MLUT 1 is wired (proximity wiring) with the MLUT 1 adjacent in the four directions by, for example, four pairs of address / data pairs AD (thin arrows).

  In the present embodiment, an additional address / data pair AD ′ (thick arrow) is connected while maintaining the address / data pair AD used for the proximity wiring. As a result, the number of address / data pairs AD and AD 'connected to each MLUT 1 increases. In FIG. 10, the total number of address / data pairs AD and AD 'is shown in each MLUT 1 as AD logarithm.

  The other address / data pair AD ′ to be added is connected to the MLUT 1 farther from the adjacent MLUT 1, thereby enabling wiring (separated wiring) to another MLUT 1 that is separated.

  Depending on the logic circuit, in such a case, the data propagation delay can be greatly reduced by adding the separated wiring. Moreover, the flexibility of wiring can be improved.

  FIG. 11 is a diagram illustrating another example of the separated wiring. FIG. 11A is a diagram showing one MLUT1, and FIG. 11B is a diagram showing an example of the MLUT group 1G. A thin arrow indicates an address / data pair AD for performing proximity wiring.

  The unit address line 130 and the unit data line 140 do not always need to be wired as an address / data pair AD. If necessary, the unit address line 130 ′ and the unit data line 140 ′ can be independently set as MLUT1 as indicated by a thick arrow. Can be added to. The numbers of unit address lines and unit data lines after the addition are shown in MLUT 1 as A lines and D lines, respectively. When a unit data line 140 ′ is added to the sending side MLUT 1 as shown in the figure, a unit address line 130 ′ is added to the receiving side MLUT 1.

  In this case, unlike the case where the additional address / data pair AD ′ is connected, the wiring is not bidirectional, but in the case of an ordinary combinational circuit, it is not necessary to use the bidirectional line, and data is propagated in a certain direction. . Therefore, the added unit address line 130 'and unit data line 140' do not necessarily have to be paired.

  In the following description, the additional address / data pair AD ′, the unit address line 13 ′, and the unit data line 14 ′ are collectively referred to as additional wiring, and adding these is referred to as performing additional wiring.

  In the present embodiment, the additional address / data pair AD ′, the unit address line 13 ′, and the unit data line 14 ′ can be added uniformly to all MLUTs 1. Thereby, the freedom degree of wiring can be improved significantly and the delay at the time of propagating data can be avoided.

  However, the additional wiring directly increases the area of the MPLD. Therefore, as shown in FIG. 10, only the necessary MLUT1 is selectively added to the address / data pair AD '. As a result, it is possible to make the routing between the MLUTs 1 more flexible during the operation of the logic circuit while suppressing an increase in the area as the MPLD. Accordingly, it is possible to avoid a delay when data is propagated to the MLUT 1 that is not adjacent.

  Further, as shown in FIG. 11, only the necessary MLUT 1 is selectively added to either the unit address line 130 'or the unit data line 140'. Thereby, although the wiring direction is limited, it can contribute to the reduction of the area. As shown in FIG. 11A, the number of bits of the memory address line 11 and the memory data input / output line 12 also increases uniformly or non-uniformly depending on the application.

  Further, as shown in FIG. 12, it is also possible to add each of the additional wirings irregularly and unevenly only to a necessary portion with respect to the desired MPLD 11. In this way, MLUT1 having different additional wirings can be mixed in one MLUT group 1G.

  Proximity wiring is easy to handle with CAD due to its symmetry and homogeneity. In this embodiment, by connecting the address / data pair AD ′, the address line 13 ′, and the data line 14 ′ for the separated wiring in addition to the neighboring wiring, the objectivity and homogeneity that are the advantages of the neighboring wiring are maintained. Thus, it is possible to provide an MPLD that can flexibly cope with the construction of a logic circuit and avoids a data propagation delay.

  Further, by securing the number of address / data pairs AD ′, address lines 13 ′, and data lines 14 ′ as necessary and limiting the MLUT 1 to be connected, an increase in the area of the entire MPLD can be suppressed.

  Further, if the additional address / data pair AD ′, the address line 13 ′, and the data line 14 ′ are three-dimensionally wired, an MPLD suitable for use in a three-dimensional LSI can be realized.

  In the above example, the MLUT 1 is connected to each other by an additional wiring. However, the present invention is not limited to this, and a storage element (storage element) such as a flip-flop circuit or a latch circuit can be added by an additional wiring, for example. As a result, the MLUT group 1G can function as a sequential circuit.

  Conventionally, when a flip-flop circuit or a latch circuit is connected to the MLUT 1, it is connected outside the MLUT group 1G. For example, the MLUT 1 near the center of the MLUT group 1G has a problem that the distance to the circuit becomes long. It was.

  However, according to the present embodiment, a flip-flop circuit or a latch circuit can be connected at a position close to the MLUT 1 to be connected.

  Furthermore, not only the separated wiring but also the adjacent MULTs 1 can be connected by an additional wiring. Thereby, the number of adjacent wirings can be selectively increased (or in total).

  FIG. 13 is a flowchart showing an example of the design process of the MPLD 10, which will be described below with reference to this.

  Step 1 (S1): The first input port 18A of the two-port memory 15 in the MLUT1 is assigned to the memory input port in the MLUT1, that is, the memory address line 11, and the first output port 18D is assigned to the memory input / output port in the MLUT1. That is, it is allocated to the memory data input / output line 12 (see FIG. 2).

  Further, the second input port 19A of the 2-port memory 15 is assigned to the logic input port in the MLUT1, that is, the logic address line 13, and the second output port 19D is assigned to the logic output port in the MLUT1, that is, the logic data line 14. .

  Step 2 (S2): The logical address line 13 and the logical data line 14 are distributed in 1-bit units, and a pseudo bidirectional line is formed by an address / data pair AD in which each one bit is paired ( (See FIG. 3B).

  Step 3 (S3): A plurality of address / data pairs AD are connected to MLUT1 so as to be derived in different directions, respectively, so as to have directionality (see FIG. 4A).

  Step 4 (S4): An additional unit address line and / or an additional unit data line are connected to at least one MLUT1. Additional wiring (address / data pair AD ′, unit address line 130 ′, unit data line 140 ′) is selectively connected to a desired MLUT 1.

  Step 5 (S5): A plurality of MLUTs 1 are arranged in an array, for example, and wiring is performed. That is, the MLUT 1 that is closer to the memory address line 11 and the memory data input / output line 12 is connected to the unit address line 130 and the unit data line 140 (address / data pair AD). Further, an additional unit address line 130 ′ and / or an additional unit data line 140 ′ (additional address data pair AD ′) are connected to MLUT1 or other elements in the MLUT group 1G to connect a logic circuit element and a memory. A logical block group including elements is configured (see FIGS. 10 to 12).

  Note that Step 2 and Step 3 described above are in no particular order.

  Next, a second embodiment of the present invention will be described with reference to FIGS.

  The MLUT 1 of the first embodiment uses the 2-port memory 15, but the logic circuit operation and memory (reconfiguration) operation of the MLUT 1 are not performed simultaneously. Therefore, in the second embodiment, instead of the 2-port memory 15, a 1-port memory 25 and wiring switchers 22 and 23 are used to form a basic logic block. Hereinafter, the basic logical block of the second embodiment will be described as SMLUT (Single-port MLUT) 2.

  14 and 15 are diagrams illustrating SMLUT2 (for example, 4 bits) according to the second embodiment. FIG. 14 is a diagram showing input / output of SMLUT2, and FIG. 15 is a diagram showing an example of wiring of SMLUT2. In addition, the same component as 1st Embodiment is shown with the same code | symbol, and description is abbreviate | omitted about the part which overlaps with 1st Embodiment.

  The operation as the MPLD 10 is the same as that of the first embodiment. That is, when operating as a logic circuit, each SMLUT 2 is operated by storing desired logic circuit construction information and information that acts as a switch signal as a truth table. When operating as a memory, it is operated by the same operation as a general memory.

  Referring to FIG. 14, SMLUT 2 includes a 1-port memory (for example, SRAM) 25, an address decoder 27, a first wiring switch 22, and a second wiring switch 23.

  The memory address line 11 and the logic address line 13 are assigned to the memory input port 28A, and the memory data input / output line 12 and the logic data line 14 are assigned to the memory input / output port 28D.

  Similarly to the MLUT 1 of the first embodiment, the SMLUT 2 also distributes the logical address lines 13 and the logical data lines 14 to unit address lines 131 to 134 and unit data lines 141 to 144, respectively.

  Referring to FIG. 15, an example of the wiring of the address / data pair AD is shown.

  The address / data pairs AD are wired in different directions from the SMLUT 2 for each pair. As an example, address / data pair AD1 (unit address line 131 and unit data line 141), address / data pair AD2 (unit address line 132 and unit data line 142), address / data pair AD3 (unit address line 133 and unit data) Line 143) and address / data pair AD4 (unit address line 134 and unit data line 144) are wired so as to be derived from the left, top, right and bottom of SMLUT2 shown in FIG. The memory address line 11 and the memory data input / output line 12 are also wired so as to be shared by each column, for example.

  The unit address lines 131 to 134 and the memory address line 11 are connected to the first wiring switch 22 provided in the SMLUT 2. The unit data lines 141 to 144 and the memory data input / output line 12 are connected to a second wiring switch 23 provided in the SMLUT 2.

  The first wiring switch 22 is connected to the input port 28A of the 1-port memory 25, and the second wiring switch 23 is connected to the output port 28D of the 1-port memory 25.

  Specifically, when the logic circuit operates, the unit address lines 131 to 134 are selected by the first wiring switch 22 and connected to the input port 28A of the 1-port memory 25, and the unit data line 141 is connected by the second wiring switch 23. ˜144 are selected and connected to the output port 28D of the 1-port memory 25.

  On the other hand, during the memory operation, the memory address line 11 is selected by the first wiring switch 22 and connected to the input port 28A of the 1-port memory 25, and the memory data input / output line 12 is selected by the second wiring switch 23. And connected to the output port 28D of the 1-port memory 25.

  By switching the first wiring switch 22 and the second wiring switch 23, the input / output at the time of logic circuit operation and the input / output at the time of memory operation can be switched, so that the one-port memory 25 is used as a storage means inside the SMLUT 2. Can be adopted.

  As a result, the SMLUT 2 can include a logic circuit element and a memory element as in the first embodiment. Further, SMLUT2 is mutually connected to neighboring SMLUT2 by address / data pairs AD1 to AD4. Since the address / data pairs AD1 to AD4 have directionality, they can function as switch elements as in the first embodiment.

  FIG. 16 is a schematic diagram showing a part of the SMLUT group 2G. The address data pair AD is indicated by a thin arrow in a single direction. SMLUT2 is arranged in a matrix, for example, and adjacent SMLUT2 is connected to each other by an address / data pair AD, a memory address line and a memory data input / output line (not shown here), and all SMLUT2 are closely wired MPLD Can be realized.

  By employing the 1-port memory 25, the area of the MPLD can be greatly reduced as compared with the 2-port memory when the memory capacity is the same.

  FIG. 17 shows, as an example, an MPLD (first embodiment) configured by the MLUT 1 of the 2-port memory 15 when the number of bits N (number of address / data pairs AD) is 4, 6, 7, and 8, and 1 The result of having estimated the area of MPLD (2nd Embodiment) comprised by SMLUT2 of the port memory 25 is shown.

The first embodiment is calculated as MPLD with no additional wiring (only adjacent wiring). Thus, by adopting the 1-port memory 25, the number of address / data pairs AD is N = 8. In some cases, an area reduction effect of about 15% is obtained, and in the case of N = 4, an area reduction effect of about 40% is obtained.

  In addition, since the first wiring switch 22 and the second wiring switch 23 can be used as a single address decoder in the SMLUT 2, the area of the MPLD 10 can be reduced as compared with the first embodiment.

  Furthermore, since the address decoder can be shared by all the SMLUTs 2 as in the MLUT 1 of the first embodiment, the area can be further reduced by arranging one address decoder outside the SMLUT 2.

  The method of using the MPLD of the second embodiment is as follows.

  First, the first wiring switch 22 and the second wiring switch 23 are operated to connect the memory address line 11 and the memory data input / output line 12 to the 1-port memory 25 in the SMLUT 2.

  Next, in order to operate as a logic circuit, configuration information and switch information of the logic circuit to be realized in a desired SMLUT 2 are input using a memory function. That is, using the memory address line 11 and the memory data input / output line 12, desired configuration information (truth table) is held in the 1-port memory 25 in the SMLUT1 in the first region R1 of the SMLUT group 2G. Let

  In addition, the truth serving as switch information for selectively switching logic circuit elements to the 1-port memory 25 in the SMLUT 2 in the second region R2 of the SMLUT group 2G using the memory address line 11 and the memory data input / output line 12 The value table holds it.

  Then, the first wiring switch 22 and the second wiring switch 23 are operated to operate as a logic circuit using the logic address line 13 and the logic data line 14 (each address / data pair AD).

  At this time, the SMLUT 2 in the third region R3 of the SMLUT group 2G that is not used for the logic circuit operation can hold desired data in each 1-port memory 25 and function as a memory element, if necessary. Furthermore, a region that does not perform a logic circuit operation in the first region R1 and the second region R2 can also function as a memory.

  A third embodiment will be described with reference to FIGS. 18 and 19.

  Referring to FIG. 18, in the third embodiment, additional wiring is performed on SMLUT 2 that is adjacently wired. That is, an additional address / data pair AD 'is added to at least one SMLUT 2 as in the first embodiment. Alternatively, either the unit address line 130 'or the unit data line 140' is added independently. As a result, it is possible to realize wiring between MLUTs separated from each other while maintaining the symmetry and homogeneity of short-distance wiring, so that data propagation delay can be avoided. In addition, it can flexibly cope with the construction of many logic circuits.

  The additional wiring may be connected to all the SMLUTs 2, or may be selectively connected only to the desired SMLUT2. Further, SMLUT2 for adding the address / data pair AD ', SMLUT2 for adding the unit address line 130', and SMLUT2 for adding the unit data line 140 'may be mixed in one SMLUT group 2G.

  Further, similarly to the first embodiment, a storage element such as a flip-flop circuit or a latch circuit can be connected to the added wiring so as to function as a sequential circuit.

  In the third embodiment, since the SMLUT 2 is composed of the 1-port memory 25, the area increase due to the additional wiring is smaller than that of the MLUT 1 using the 2-port memory 15, and even when a wiring is added, the area is small. This makes it possible to configure an MPLD.

  FIG. 19 is a flowchart showing an example of the design process of the MPLD 10 according to the third embodiment, which will be described below with reference to this.

  Step 1 (S1): The first wiring switch 25 and the second wiring switch 26 for switching the wiring are arranged in the SMLUT 2, and the input port 18A of the 1-port memory 25 in the SMLUT 2 is connected to the memory address line in the SMLUT 2. 11 and the logical address line 13, and the output port 18D is assigned to the memory data input / output line 12 and the logical data line 14 in the SMLUT 2 (see FIG. 14).

  Step 2 (S2): The logical address line 13 and the logical data line 14 are distributed in 1-bit units, and a pseudo bidirectional line is formed by an address / data pair AD in which each one bit is paired ( FIG. 15).

  Step 3 (S3): A plurality of address / data pairs AD are connected to the SMLUT 2 so as to be derived in different directions, so as to have directionality.

  Step 4 (S4): An additional unit address line and / or an additional unit data line are connected to at least one SMLUT2. Additional wiring (address / data pair AD ′, unit address line 130 ′, unit data line 140 ′) is selectively connected to a desired SMLUT 1. Note that the additional wiring step is not necessary in the case of the MPLD having only the adjacent wiring shown in the second embodiment.

  Step 5 (S5): A plurality of SMLUTs 2 are arranged in an array, for example, and wiring is performed. That is, the memory address line 11 and the memory data input / output line 12 are connected to the adjacent SMLUT 1 by the unit address line 130 and the unit data line 140 (address / data pair AD). Further, an additional unit address line 130 ′ and / or an additional unit data line 140 ′ (additional address / data pair AD ′) are connected to SMLUT2 or other elements in the SMLUT group 2G to connect a logic circuit element and a memory. A logical block group including elements is configured (see FIG. 18).

  Steps 2 and 3 above are in no particular order.

  Furthermore, as a fourth embodiment, the MPLD may be configured by a basic logical block group in which the SMLUT 2 shown in the second embodiment and a basic logical block (MLUT) having a plurality of ports are mixed.

  For example, the two-port memory MLUT1 shown in the first embodiment and the one-port memory SMLUT2 shown in the second embodiment are mixed.

  In this case, the control method is different between the MPLD configured with MLUT1 and the MPLD configured with SMLUT1. That is, in the case of an MPLD configured with MLUT1, MLUT1 uses a two-port memory 15, and therefore the wirings used for the logic function and the memory function are independent and different wirings. Therefore, control for switching between these is unnecessary.

  On the other hand, in the case of an MPLD configured with SMLUT1, since SMLUT2 uses a 1-port memory, the first wiring switch 22 and the second wiring switch 23 make it a pseudo 2 port. The logic function wiring and the memory function wiring are different from each other outside the SMLUT 2, but the logic function and the memory function wiring are switched by switching the first wiring switch 22 and the second wiring switch 23 inside the SMLUT 2. Since they are shared, switching between the memory function and the logic function in the whole must be controlled by a switch.

  The basic logical block mixed with the SMLUT 2 is not limited to the one using a two-port memory, and one using a multi-port memory such as a three-port memory or a four-port memory can be applied.

  It can be used as a new device in place of the FPGA used in the conventional reconfigurable system.

  Further, it can be used as a substitute for a memory mounted on a SoC (System-on-Chip). Since it can be reconfigured according to the situation, it is possible to reconfigure and implement the functions required after mounting the SoC using the PLD of the present invention.

  Furthermore, by mounting the PLD of the present invention on the SoC, the present invention can be applied to repairs in the case where a failure occurs in any of the circuits mounted on the SoC and the assistance of the CPU or the like mounted on the SoC.

  Further, it can be used as an FPGA mounted on a SoC, and the number of name wiring layers required for mounting from a conventional FPGA is small, so that it can be widely used.

It is a schematic diagram explaining the programmable logic device of the embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is (A) logic circuit diagram, (B) truth table, (3) schematic diagram explaining the programmable logic device of the 1st Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is (A) truth table, (B) schematic diagram, (C) schematic diagram explaining the programmable logic device of the 1st Embodiment of this invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a schematic diagram explaining the programmable logic device of a 1st embodiment of the present invention. It is a flowchart explaining the construction method of the programmable logic device of the 1st Embodiment of this invention. It is a schematic diagram explaining the programmable logic device of the 2nd Embodiment of this invention. It is a schematic diagram explaining the programmable logic device of the 2nd Embodiment of this invention. It is a schematic diagram explaining the programmable logic device of the 2nd Embodiment of this invention. It is a figure for comparing the programmable logic device of the 1st and 2nd embodiment of this invention. It is a schematic diagram explaining the programmable logic device of the 3rd Embodiment of this invention. It is a flowchart explaining the construction method of the programmable logic device of the 3rd Embodiment of this invention. It is a schematic diagram explaining the conventional programmable logic device. It is a schematic diagram explaining the conventional programmable logic device.

Explanation of symbols

1 Basic logical block (MLUT)
2 Basic logic block (SMLUT)
3 row decoder 4 column decoder 10 MPLD
11 memory address line 12 memory data input / output line 13 logic address line 14 logic data line 15 2-port memory 16, 17 decoder 18A first input port 18D first output port 19A second input port 19D second output port 25 1-port memory 22 1st wiring switch 23 2nd wiring switch 27 Decoder 28A Input port 28D Output port 130, 131, 132, 133, 134 Unit address line 140, 141, 142, 143, 144 Unit data line AD, AD1, AD2, AD3, AD4 address / data pair

Claims (11)

A programmable logic device having a plurality of basic logic blocks and having a plurality of logic circuits configured according to configuration information,
Each of the basic logic blocks has storage means, a memory address line, a memory data input / output line, a logic address line, and a logic data line,
The logical address line and the logical data line are distributed for each bit according to the number of bits of the logical input / output data to form unit address lines and unit data lines, and the unit address lines and unit data lines are paired. Are wired in different directions from the basic logic block for each pair,
The basic logic block closer to the unit address line and the unit data line and the memory address line and the memory data input / output line is connected to form a logic block group including a logic circuit element and a memory element. ,
The programmable logic device, wherein at least one basic logic block has an additional unit address line and / or an additional unit data line.   Configuration information for realizing a desired logic circuit is held in the storage means in the first area of the basic logic block group, and the storage means in the second area of the basic logic block group stores information on the first area. The programmable logic device according to claim 1, wherein switch information for selectively switching the basic logic block is held, and the basic logic block group becomes the logic circuit element.   The desired data is held in a third area of the basic logic block group or an area not operating as the logic circuit element, and at least a part of the basic logic block group is a memory element. Item 3. The programmable logic device according to Item 2.   The programmable logic device according to claim 1, wherein the additional unit address line and / or the additional unit data line connects the basic logic blocks.   The programmable logic device of claim 1, wherein a storage element is connected to the additional unit address line and / or the additional data line.   The storage means is a one-port memory, and the basic logic block switches a memory address line and the unit address line and assigns them to an input port of the first port memory, and the memory A second wiring switch that switches between the data input / output line and the unit data line and assigns it to the output port of the one-port memory, and when the logic circuit is operated by the first wiring switch and the second wiring switch, 2. The programmable logic device according to claim 1, wherein a unit address line and the unit data line are selected, and the memory address line and the memory data input / output line are selected during a memory operation.   2. The logical block group according to claim 1, wherein a first basic logical block having a 1-port memory as the storage means and a second basic logical block having a multi-port memory as the storage means coexist. Programmable logic devices. A storage unit, a memory address line, a memory data input / output line, a logic address line, and a logic data line are connected to each other, and a plurality of basic logic blocks are connected to each other according to configuration information. A programmable logic device construction method for constructing a logic circuit,
Assigning ports of the storage means to the memory address lines, memory data input / output lines, logic address lines and logic data lines;
The logical address line and the logical data line are distributed in 1-bit units according to the number of bits of the logical input / output data to form unit address lines and unit data lines, and the unit address lines and unit data lines are paired. And steps to
Wiring in a different direction from the basic logic block for each pair;
Connecting an additional unit address line and / or an additional unit data line to at least one of the basic logic blocks;
The memory address line and the memory data input / output line are connected to the basic logical block closer to the unit address line and the unit data line, and the additional unit address line and / or the additional unit data line are connected. Connecting to the basic logic block or other elements in the basic logic block group to configure a logic block group comprising logic circuit elements and memory elements;
A method for constructing a programmable logic device, comprising:   A first wiring switch that uses a one-port memory as the storage means, switches the memory address line and the unit address line to the basic logic block, and assigns them to an input port of the first port memory; 9. The method of constructing a programmable logic device according to claim 8, further comprising: a second wiring switching unit that switches between a data input / output line and the unit data line and assigns it to an output port of the one-port memory. A basic logic block is configured by the storage means, the memory address line, the memory data input / output line, the logic address line, and the logic data line,
Ports of the storage means are assigned to the memory address lines and memory data input / output lines, logic address lines and logic data lines,
The logical address lines and the logical data lines are distributed in units of 1 bit according to the number of bits of the logical input / output data to form unit address lines and unit data lines, and the unit address lines and unit data lines are paired. For each pair, wire in a different direction from the basic logic block,
A logic block group including a logic circuit element and a memory element by interconnecting the memory address line and the memory data input / output line and the basic logic block closer to the unit address line and the unit data line. Configure
An additional unit address line and / or an additional unit data line connected to at least one of the basic logic blocks;
A method of using a programmable logic device in which the additional unit address line and / or the additional unit data line are connected to the basic logic block or other elements in the basic logic block group that are not adjacent to each other.
Using the memory address line and the memory data input / output line to hold configuration information for realizing a desired logic circuit in the storage means in the first area of the basic logic block group;
Using the memory address line and the memory data input / output line to cause the storage means in the second area of the logical block group to hold switch information for selectively switching the basic logical block in the first area When,
Performing logic circuit operation using the logic address line and the logic data line;
The memory address line is used to hold desired data in a third area of the basic logic block group or a non-operating area as the logic circuit element, and at least a part of the basic logic block group operates as a memory. Step to
A method of using a programmable logic device comprising:   A first-port switch that uses a one-port memory as the storage means of the basic logic block, switches the memory address line and the unit address line to the basic logic block, and assigns them to the input port of the first port memory And a second wiring switch that switches between the memory data input / output line and the unit data line and allocates to the output port of the one-port memory, and the first wiring switch and the second wiring switching The method of using the programmable logic device according to claim 10, wherein the logic circuit operation or the memory operation is performed by operating a device.

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