JP2009188508A - Data transmission and reception device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission and reception device whose transmission performance can be improved in a state where a TLP is received without deviating from the PCI Express standard. <P>SOLUTION: The data transmission and reception device comprises: a packet transmission timer for flow control; a receiving buffer which stores data of a received transaction layer packet and outputs a packet transmission request signal for flow control when the data are transmitted to a higher system; a transmission performance setting register which stores the value of a transmission period of the packet for flow control for each transmission performance setting calculated from the band etc., of a link; and a packet transmission circuit for flow control, which makes the packet transmission timer for flow control start measurement by using the value of the transmission period corresponding to transmission performance needed as the expiration value of the packet transmission timer for flow control when the packet transmission request signal for flow control is received, and starts transmission of packets for flow control when the measurement is completed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data transmission / reception device, and more particularly to a data transmission / reception device employing a PCI Express standard communication method.

  One of the high-speed I / O interfaces is PCI Express formulated by PCI-SIG. This PCI Express is a serial bus, adopts a full-duplex method, and has a packet transmission side and a reception side path. In addition to TLP (Transaction Layer Packet) that handles data read / write processing, there are packets that manage PCI Express Link. Both packets are transmitted and received using the same path (serial bus).

  A data transmission / reception device (hereinafter referred to as a “PCIe device”) conforming to the PCI Express standard includes a reception buffer that temporarily stores TLP data in order to transmit the data to a host system. In PCI Express, flow control is performed using the reception buffer empty information. In other words, when the receiving PCIe device receives the TLP, it temporarily stores it in the reception buffer. After that, when the TLP data in the reception buffer is transmitted to the upper system and the reception buffer becomes empty, the reception buffer becomes empty. Information is transferred to the PCIe device on the transmission side as flow control information. This transmitting side PCIe device controls the amount of TLP transmission according to the received flow control information. In PCI Express, this flow control information is transmitted in a packet called UpdateFC DLLP (Update Flow Control Data Link Layer Packet).

  According to the PCI Express standard, if there is no TLP received, there is no need to send an UpdateFC DLLP associated with TLP reception, so the TLP can be sent with the maximum transmission performance. Here, the transmission (reception) performance means a bandwidth obtained by subtracting a bandwidth occupied by a link management packet from the bandwidth of the PCI Express Link. In other words, it means the number of TLP bytes that Link can send (receive) per second.

  However, in a state where a large amount of TLP is received, the aforementioned UpdateFC DLLP occurs frequently. Therefore, there is a problem that the transmission performance is reduced by the amount used for the transmission of UpdateFC DLLP.

Conventionally, there has been a communication system that optimizes the size of the packet retransmission buffer and the transmission interval of the acknowledgment (Ack DLLP) for the purpose of improving transmission performance (Patent Document 1). The deterioration of transmission performance due to the occurrence was inevitable.
JP 2007-180611 A

  An object of the present invention is to provide a data transmitting / receiving apparatus capable of improving transmission performance in a state where a TLP is received without departing from the PCI Express standard.

  According to the present invention, the flow control packet transmission timer that measures the time of the set expiration value and the data of the received transaction layer packet are stored, and when the data is transmitted to the host system, the flow control packet transmission is performed. The transmission cycle of the flow control packet for each transmission performance setting calculated from the reception buffer that outputs the request signal, the bandwidth of the link, the necessary transmission performance, and the bandwidth necessary for transmitting packets other than the transaction layer packet. When the transmission performance setting register for storing the value and the flow control packet transmission request signal are received, the value of the transmission cycle corresponding to the required transmission performance is used as the expiration value of the flow control packet transmission timer. The flow control packet transmission tie To initiate the measurement, the measurement starts transmission of the flow control packet to be completed, the data transmitting and receiving apparatus and a flow control packet transmission circuit is provided.

  According to the present invention, transmission performance can be improved in a state where a TLP is received without departing from the PCI Express standard.

  Before describing an embodiment of the present invention, an overview of PCI Express will be described.

  The PCI Express link is composed of units called Lanes, and 1, 2, 4, 8, 16, and 32 are defined as the number of Lanes. Each Lane performs 2.5Gbps serial transfer, and the bandwidth can be increased by increasing the number of Lanes. A link composed of one Lane is called x1 Link, and a link composed of four Lanes is called x4 Link.

  As serial transfer, the data that appears on the link is 8b / 10b converted packets, and each 8 bits (1 byte) contains 2 bits of redundant data. Considering the 8b / 10b conversion, the number of packet bytes that can flow on the Link per second is 250,000,000 Bytes (250 MByte) for x1 Link and 1,000,000,000 Bytes (1 GByte) for x4 Link.

  In addition to UpdateFC DLLP, there are Ack DLLP (Acknowledge Data Link Layer Packet) and SKP-OS (SKiP Order Set) as Link management packets that occur when TLP is transmitted and received in a normal Link state.

The Ack DLLP is a DLLP packet that is generated when a TLP is received, and is not generated unless a TLP is received. As described above, UpdateFC DLLP does not occur unless the TLP data stored in the reception buffer is processed and there is no free space in the reception buffer. On the other hand, the Ack DLLP occurs even if the data in the reception buffer is not processed when the CRC (Cyclic Redundancy Check) of the received TLP is confirmed. The time from receiving the TLP to transmitting the Ack DLLP is defined by the PCI Express standard. Specifically, when the maximum size of data length that can be placed on one TLP is 128 bytes, the link width is within 292 ns for x4, and within 948 ns for x1.

  SKP-OS is a packet that is generated periodically regardless of the presence or absence of TLP. In the PCI Express standard, scheduling is performed such that transmission is performed once during 4720 ns to 6152 ns when no other packet is transmitted.

  The recommended value and the minimum value are defined in the PCI Express standard for the timing of transmitting UpdateFC DLLP, and any timing can be transmitted as long as the timing is earlier than the minimum value (short transmission cycle). The recommended value is 292 ns when the maximum data length that can be placed in one TLP is 128 bytes, and the link width is x4, and 948 ns when x1. The minimum value is 30μs regardless of the Link width. In addition, the UpdateFC DLLP is transmitted once every 30 μs even when no TLP is received according to the PCI Express standard.

Table 1 shows the TLP transmission performance when no TLP is received (no TLP reception) and when TLP is always received (TLP reception without any interval) between x4 Link and x1 Link. Each case is shown. This performance value is calculated assuming that the maximum size of data length that can be placed in one TLP is 128 bytes and the transmission interval of SKP-OS is 5440 ns. In the case of no TLP reception, as can be seen from Table 1, SKP-OS and UpdateFC DLLP with a period of 30μs are periodically transmitted, so the transmission performance is smaller than the total bandwidth of Link. On the other hand, when TLP is being received without an interval, Ack DLLP and UpdateFC DLLP are transmitted every 292 ns with the reception of TLP, in addition to packets that are periodically transmitted. Therefore, as can be seen from Table 1, the TLP transmission performance in this case is reduced by 5.5% for x4 Link and 6.7% for x1 Link compared to the case where no TLP is received.

  The present invention is intended to suppress a decrease in transmission performance during such TLP reception.

  Hereinafter, two embodiments according to the present invention will be described with reference to the drawings.

In both the first embodiment and the second embodiment, transmission performance is improved by deferring transmission of UpdateFC DLLP within the allowable range in the standard. One of the differences between the two embodiments is that the first embodiment delays the transmission timing of the UpdateFC DLLP according to a predetermined transmission performance setting, whereas the second embodiment is different from the TLP transmission status. In response, the update timing of UpdateFC DLLP is automatically changed.

(First embodiment)
First, the standard configuration of the PCIe device will be described, and then the PCIe device according to the present embodiment will be described.

  The PCIe device according to the standard configuration includes a reception buffer 1 and an UpdateFC DLLP transmission circuit 2.

  The reception buffer 1 temporarily stores the received TLP data and transmits it to a higher system. When the TLP data is transmitted to the host system, an UpdateFC DLLP transmission request signal is transmitted to the UpdateFC DLLP transmission circuit 2.

  When the UpdateFC DLLP transmission circuit 2 receives the UpdateFC DLLP transmission request signal from the reception buffer 1, the UpdateFC DLLP transmission circuit 2 starts UpdateFC DLLP transmission processing.

  More specifically, UpdateFC DLLP transmission processing is performed using a timer. That is, when the UpdateFC DLLP transmission circuit 2 receives the UpdateFC DLLP transmission request signal, it causes an UpdateFC DLLP transmission timer (not shown) to start measurement. When measurement is complete, it starts to send UpdateFC DLLP to the connection partner.

  The UpdateFC DLLP transmission timer measures the time (hereinafter referred to as UpdateFC DLLP transmission cycle) from when the received TLP data is transmitted to the host system until transmission of UpdateFC DLLP is started. Here, 292ns (recommended value for x4 Link) is measured.

  When the UpdateFC DLLP transmission cycle (292ns) by the first TLP is measured, another TLP (late arrival TLP) is received and the information of this late arrival TLP is transmitted to the host system. After the UpdateFC DLLP transmission timer by the first TLP has expired, transmission of one UpdateFC DLLP indicating that the first TLP information and the second TLP information have left the reception buffer is started.

  In this standard configuration, the transmission performance of TLP is 941,997,636 Byte / s (in the case of x4 Link) in a state where TLP is continuously received as described above.

  Next, the relationship between the transmission performance and the UpdateFC DLLP transmission cycle will be described.

  Here, as an example, the UpdateFC DLLP transmission period when the x4 Link transmission performance is improved by 1% is calculated. As shown in Table 1, since the transmission performance during TLP reception without any interval is 941,997,636 Byte / s, the transmission performance improved by 1% is 951,417,613 Byte / s. As described above, since the total bandwidth of x4 Link is 1,000,000,000 Byte / s, the bandwidth that can be allocated to packets other than TLP is 48,582,387 Byte / s. From this, the bandwidth consumed by the packet that is regularly transmitted is subtracted from the bandwidth that can be used by UpdateFC DLLP and Ack DLLP generated by TLP reception. Since UpdateFC DLLP and Ack DLLP are both 64 bits in size, the value obtained by dividing this bandwidth by the total of 128 bits is the number of packets transmitted per second. The UpdateFC DLLP transmission cycle is obtained as the reciprocal of this number.

Table 2 shows the UpdateFC DLLP transmission cycle obtained as described above for each transmission performance setting for each of x4 Link and x1 Link. This table also shows transmission performance and reception performance for each setting. As an example, the reception performance in the table is calculated assuming that the size of the reception buffer 1 is a size that can store four 128-byte TLP data, and the internal latency is 200 ns. Here, the internal latency means that after the UpdateFC DLLP transmission timer expires and the receiving PCIe device starts sending UpdateFC DLLP, the sending PCIe device receives UpdateFC DLLP, updates flow control information, and updates This is the time from when a TLP is transmitted until the receiving PCIe device receives the TLP.

  Next, the PCIe device 10 according to the first embodiment will be described.

  The configuration of the PCIe device 10 is shown in FIG. As can be seen from FIG. 1, the PCIe device 10 further includes a transmission performance setting register 3 and a TLP detection circuit 4 in addition to the reception buffer 1 and UpdateFC DLLP transmission circuit 2 which are standard configurations.

  The transmission performance setting register 3 has UpdateFC DLLP transmission cycle values shown in Table 2 (292 ns, 529 ns, 668 ns, 904 ns, 1402 ns, 3119 ns, 30000 ns in the case of x4 Link). As shown in Table 2, there are seven patterns for setting the transmission performance. That is, the transmission performance of 941,997,636 Byte / s, which is the state where TLP is continuously received, is set as a reference value, and the transmission performance is set to improve by 1%, set to improve by 2%, and improved by 3% compared to the reference value. There are seven patterns: setting to perform, setting to improve 4%, setting to improve 5%, setting to give priority to the transmission side completely, and no setting. The setting in which the transmission side is completely prioritized is a setting in which the UpdateFC DLLP transmission cycle is set to the standard minimum value of 30 μs, the UpdateFC DLLP is transmitted at the lowest frequency allowed by the standard, and the transmission performance is maximized. If there is no setting, the recommended standard value that is the smallest transmission cycle is used as the UpdateFC DLLP transmission cycle.

  When the PCIe device 10 is activated, the software reads the value of the UpdateFC DLLP transmission period corresponding to the transmission performance set by the user from the transmission performance setting register 3, and sets the value as the expiration value of the UpdateFC DLLP transmission timer.

  For example, in the case of setting to improve by 1% in x4 Link, the expiration value of the UpdateFC DLLP transmission timer is changed from the standard recommended value of 292 ns to 529 ns. This reduces the frequency of UpdateFC DLLP transmissions and improves the performance available for TLP transmissions by 1%. That is, as can be seen from Table 2, the transmission performance is improved by 1% to 951,417,613 Byte / s.

  However, as can be seen from Table 2, if the frequency of UpdateFC DLLP transmission is reduced to improve transmission performance, the frequency at which flow control information is transmitted to the connection partner decreases, and the connection partner restricts TLP transmission. As a result, reception performance decreases.

  Next, the TLP detection circuit 4 will be described. The TLP detection circuit 4 detects the presence or absence of TLP transmission, and sets an expiration value of the UpdateFC DLLP transmission timer for the UpdateFC DLLP transmission circuit 2. In other words, when there is a TLP transmission, the expiration value of the UpdateFC DLLP transmission timer is set to a value corresponding to the transmission performance setting (for example, 529 ns when x4 Link is improved by 1%). On the other hand, when there is no TLP transmission, the expiration value of the UpdateFC DLLP transmission timer is set to the standard recommended value (292 ns for x4 Link). By doing so, it is possible to prevent the reception performance from deteriorating when TLP is not transmitted.

  As described above, according to the first embodiment, it is possible to ensure preset transmission performance in a state where a TLP is received without departing from the PCI Express standard. From this, this embodiment is suitable when the necessary transmission performance is known in advance.

(Second Embodiment)
Next, a second embodiment will be described. One of the differences from the first embodiment is that the UpdateFC DLLP transmission timing (UpdateFC DLLP transmission cycle) is automatically changed according to the TLP transmission status, as described above.

  FIG. 2 shows a configuration of the PCIe device 20 according to the second embodiment.

  As can be seen from FIG. 2, the PCIe device 20 includes a reception buffer 11, an UpdateFC DLLP transmission circuit 12, and a TLP transmission performance automatic setting circuit 13.

  The reception buffer 11 temporarily stores the received TLP data and transmits it to the host system. When the TLP data is transmitted to the host system, an UpdateFC DLLP transmission request signal is transmitted to the UpdateFC DLLP transmission circuit 12.

  When the UpdateFC DLLP transmission circuit 12 receives the UpdateFC DLLP transmission request signal from the reception buffer 11, it causes the UpdateFC DLLP transmission timer to start measuring the set time (expiration value). When the measurement is completed, a timer expiration signal is transmitted to the TLP transmission performance automatic setting circuit 13. When an UpdateFC DLLP transmission start signal is received from the TLP transmission performance automatic setting circuit 13, transmission of UpdateFC DLLP to the connected PCIe device is started. It also has transmission history information such as the type of packet transmitted.

  The TLP transmission performance automatic setting circuit 13 has UpdateFC DLLP transmission cycle values (292 ns, 529 ns, 668 ns, 904 ns, 1402 ns, 3119 ns, 30000 ns in the case of x4 Link) corresponding to each transmission performance setting shown in Table 2. . Also, the presence or absence of TLP transmission is detected. Further, the UpdateFC DLLP transmission circuit 12 reads and writes the expiration value of the UpdateFC DLLP transmission timer, and receives from the UpdateFC DLLP transmission circuit 12 a timer expiration signal indicating that this timer has expired.

  The operation of the TLP transmission performance automatic setting circuit 13 will be described with reference to the flowchart of FIG.

First, the recommended standard value (292 ns for x4 Link and 948 ns for x1 Link), which is the smallest transmission cycle, is set as the initial value of the expiration value of the UpdateFC DLLP transmission timer (step S11).

  Next, it is determined whether or not a timer expiration signal has been received from the UpdateFC DLLP transmission circuit 12 (step S12).

  When the timer expiration signal is received, the expiration value of the UpdateFC DLLP transmission timer is read, and it is determined whether or not it is the standard minimum value (30 μs) (step S13).

  If it is the minimum standard value, an UpdateFC DLLP transmission start signal is transmitted to the UpdateFC DLLP transmission circuit 12 (step S16).

  If it is not the minimum standard value, it is checked whether there is a TLP transmission (step S14).

  If there is a TLP transmission, the UpdateFC DLLP is not transmitted at that timing, and the expiration value of the UpdateFC DLLP transmission timer is changed so that the transmission performance is improved by 1% from the current state (step S15). For example, when the current transmission performance setting is improved by 1% (UpdateFC DLLP transmission cycle is 529 ns), 668 ns improved by 2% is written as the expiration value. In this case, the UpdateFC DLLP transmission timer further measures 139 ns (668 ns-529 ns), and again transmits a timer expiration signal when the measurement is completed. Similarly, if the current transmission performance setting is set to improve by 5%, the setting of the UpdateFC DLLP transmission period is changed from 3,119 ns to 30,000 ns.

  After that, when the UpdateFC DLLP transmission timer expires again, similarly, the presence or absence of TLP transmission is confirmed. If there is TLP transmission, the transmission performance setting is increased by one step.

  When such an operation is repeated and the expiration value of the UpdateFC DLLP transmission timer reaches the minimum standard value, UpdateFC DLLP is preferentially transmitted (steps S13 and S16). That is, if there is TLP transmission at the timing of UpdateFC DLLP transmission, the transmission of UpdateFC DLLP is postponed up to the minimum standard value, and TLP transmission is given priority. Thereby, transmission performance can be improved without departing from the standard.

  Based on the transmission history of the UpdateFC DLLP transmission circuit 12, whether or not there is a TLP transmission from the transmission of the UpdateFC DLLP in the previous step S16 to the transmission of the current UpdateFC DLLP. Determination is made (step S17).

  If there is no TLP transmission, the expiration value of the UpdateFC DLLP transmission timer is returned to the standard recommended value (step S18). As a result, useless waiting time of UpdateFC DLLP can be reduced, and degradation of reception performance can be suppressed.

  Note that after the step S17 is deleted and the UpdateFC DLLP is transmitted, the expiration value of the UpdateFC DLLP transmission timer may be unconditionally returned to the standard recommended value.

  As described above, according to the second embodiment, transmission performance in a state of receiving TLP is improved as much as possible according to TLP transmission status without departing from the PCI Express standard. Can do. In addition, since the UpdateFC DLLP transmission cycle is automatically reduced, it is possible to reduce useless waiting time and suppress deterioration in reception performance.

It is a figure which shows the structure of the PCIe apparatus which concerns on 1st Embodiment. It is a figure which shows the structure of the PCIe apparatus which concerns on 2nd Embodiment. It is a flowchart which shows the operation | movement which concerns on 2nd Embodiment.

Explanation of symbols

1,11 Receive buffer 2,12 UpdateFC DLLLP transmission circuit 3 Transmission performance setting register 4 TLP detection circuit 10, 20 PCIe device 13 TLP transmission performance automatic setting circuit

Claims (5)

A packet transmission timer for flow control that measures the time of the set expiration value, and
A receiving buffer for storing received transaction layer packet data, and outputting a flow control packet transmission request signal when the data is transmitted to an upper system;
A transmission performance setting register for storing the value of the transmission period of the flow control packet for each transmission performance setting, calculated from the bandwidth of the link, the required transmission performance, and the bandwidth required for transmission of packets other than the transaction layer packet;
When the flow control packet transmission request signal is received, the flow control packet transmission timer is measured using the value of the transmission period corresponding to the necessary transmission performance as the expiration value of the flow control packet transmission timer. A flow control packet transmission circuit that starts transmission of the flow control packet when the measurement is completed;
A data transmitting / receiving apparatus comprising: The data transmitting / receiving apparatus according to claim 1,
If the transaction layer packet is transmitted as the expiration value of the flow control packet transmission timer, the presence or absence of transmission of the transaction layer packet is detected, the transmission period stored in the transmission performance setting register Among the values, the value of the transmission cycle corresponding to the required transmission performance is set, and when there is no transmission of the transaction layer packet, the value of the transmission cycle stored in the transmission performance setting register is the most A transaction layer packet detection circuit for setting a small value;
A data transmitting / receiving apparatus characterized by the above. A packet transmission timer for flow control that measures the time of the set expiration value, and
A receiving buffer for storing received transaction layer packet data, and outputting a flow control packet transmission request signal when the data is transmitted to an upper system;
When the flow control packet transmission request signal is received, the flow control packet transmission timer starts measuring the expiration value. When the measurement is completed, the timer expiration signal is transmitted and the flow control packet transmission start signal is received. Then, flow control packet transmission circuit that starts transmission of the flow control packet,
Stores the value of the transmission period of the flow control packet for each transmission performance calculated from the bandwidth of the link, the transmission performance, and the bandwidth required for transmission of packets other than the transaction layer packet, and receives the timer expiration signal When the transmission of the transaction layer packet is detected and the transmission of the transaction layer packet is detected, the expiration value of the flow control packet transmission timer is set to the transmission performance improved from the current transmission cycle value. A transmission performance automatic setting circuit that outputs the flow control packet transmission start signal when there is no transmission of the transaction layer packet;
A data transmitting / receiving apparatus comprising: The data transmitting / receiving apparatus according to claim 3,
The transmission performance automatic setting circuit is configured to transmit the transaction layer packet, and when the expiration value of the flow control packet transmission timer is the largest value among the transmission cycle values, A data transmission / reception apparatus that outputs the flow control packet transmission start signal even when a packet is transmitted. The data transmitting / receiving apparatus according to claim 3 or 4,
The transmission performance automatic setting circuit, when there is no transaction layer packet transmission between the previous transmission of the transaction layer packet and the transmission of the current transaction layer packet, the expiration value of the flow control packet transmission timer Is changed to the smallest value among the values of the transmission cycles.

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