CN116627869A - Data transmission method and device applied to electronic equipment - Google Patents
Data transmission method and device applied to electronic equipment Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000000872 buffer Substances 0.000 claims abstract description 73
- 238000004590 computer program Methods 0.000 claims description 23
- 238000012546 transfer Methods 0.000 claims description 8
- 238000004891 communication Methods 0.000 description 12
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a data transmission method and a device applied to electronic equipment, wherein the electronic equipment comprises a master equipment and a slave equipment, a master DMA controller, a master SPI controller and a master memory are arranged in the master equipment, a slave DMA controller, a slave SPI controller and a slave memory are arranged in the slave equipment, and the master equipment is connected with the slave equipment through an SPI interface, and the method comprises the following steps: when the master device transmits data to the slave device, reading the first data to be transmitted from the main memory through the master DMA controller, and writing the first data to be transmitted into a master buffer area of the master device; transmitting the sub data of the main buffer area to the slave device through an SPI interface by the main SPI controller; writing the received sub data into a slave buffer of the slave device by the slave SPI controller; by reading sub-data of the slave buffer from the DMA controller and writing the sub-data of the slave buffer to the slave memory. The technical scheme of the application can improve the efficiency of the master device to transmit data to the slave device.
Description
Technical Field
The present application relates to the field of data transmission technologies, and in particular, to a data transmission method and apparatus applied to an electronic device.
Background
SPI (Serial Peripheral Interface) is a serial peripheral interface protocol for transferring data between microcontrollers or digital signal processors. The SPI interface is typically comprised of a master device that is responsible for initiating data transfer requests and controlling the transfer process, and one or more slave devices that respond to the master device's requests and provide data. In the SPI interface, the master device generally adopts an interrupt mode to transmit data to the slave device, however, when the data is transmitted in the interrupt mode, the data transmission process is frequently interfered by software, so that the data transmission efficiency is reduced.
Disclosure of Invention
In view of the above, embodiments of the present application provide a data transmission method, apparatus, electronic device and computer readable storage medium applied to electronic devices, so as to solve the technical problem that the efficiency of data transmission is reduced due to frequent intervention of software in the data transmission process when data is transmitted in an interrupt manner in the related art.
In a first aspect of the embodiment of the present application, there is provided a data transmission method applied to an electronic device, where the electronic device includes a master device and a slave device, the master device is configured with a master DMA controller, a master SPI controller, and a master memory, the slave device is configured with a slave DMA controller, a slave SPI controller, and a slave memory, and the master device and the slave device are connected through an SPI interface, the method includes: when the master device transmits data to the slave device, reading the first data to be transmitted from the main memory through the master DMA controller, and writing the first data to be transmitted into a master buffer area of the master device; transmitting the sub data of the main buffer area to the slave device through an SPI interface by the main SPI controller; writing the received sub data into a slave buffer of the slave device by the slave SPI controller; by reading sub-data of the slave buffer from the DMA controller and writing the sub-data of the slave buffer to the slave memory.
In a second aspect of the embodiment of the present application, there is provided a data transmission apparatus applied to an electronic device, where the electronic device includes a master device and a slave device, the master device is disposed with a master DMA controller, a master SPI controller, and a master memory, the slave device is disposed with a slave DMA controller, a slave SPI controller, and a slave memory, and the master device and the slave device are connected through an SPI interface, the apparatus includes: the first writing module is used for reading the first data to be transmitted from the main memory through the main DMA controller and writing the first data to be transmitted into a main buffer area of the main device when the main device transmits the data to the slave device; the transmission module is used for transmitting the sub data of the main buffer area to the slave equipment through the SPI interface by the main SPI controller; the second writing module is used for writing the received sub data into a slave buffer area of the slave device through the slave SPI controller; and a third writing module for reading the sub data of the slave buffer by the slave DMA controller and writing the sub data of the slave buffer to the slave memory.
In a third aspect of the embodiment of the present application, an electronic device is provided, where the electronic device includes a master device and a slave device, and the master device and the slave device are connected through an SPI interface; the main equipment is provided with a main DMA controller, a main SPI controller, a main processor, a main memory and a computer program which is stored in the main memory and can run on the main processor, and the main processor controls the main DMA controller and the main SPI controller to realize the corresponding steps of the method when executing the computer program; the slave device is provided with a slave DMA controller, a slave SPI controller, a slave processor, a slave memory, and a computer program stored in the slave memory and executable on the slave processor, which when executed controls the slave DMA controller and the slave SPI controller to implement the corresponding steps of the above method.
In a fourth aspect of the embodiments of the present application, there is provided a computer-readable storage medium storing a computer program, the computer program being executed by a host processor to control a host DMA controller and a host SPI controller to implement corresponding steps of the above method; the execution of the computer program by the slave processor controls the slave DMA controller and the slave SPI controller to implement the corresponding steps of the above method.
Compared with the prior art, the embodiment of the application has the beneficial effects that: according to the embodiment of the application, when the master device transmits data to the slave device, the first data to be transmitted is read from the master memory through the master DMA controller, the first data to be transmitted is written into the master buffer area of the master device, the sub data of the master buffer area is transmitted to the slave device through the SPI interface through the master SPI controller, the received sub data is written into the slave buffer area of the slave device through the slave SPI controller, the sub data of the slave buffer area is read from the DMA controller, and the sub data of the slave buffer area is written into the slave memory, so that the data is transmitted in such a way that the data is not interfered by software, and the efficiency of the master device transmitting the data to the slave device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a data transmission method applied to an electronic device according to an embodiment of the present application;
FIG. 2 is a flow chart of another data transmission method applied to an electronic device according to an embodiment of the present application;
FIG. 3 is a timing diagram of a master device transmitting data to a slave device according to an embodiment of the present application;
FIG. 4 is a timing diagram of a slave device transmitting data to a master device according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a data frame queue according to an embodiment of the application;
fig. 6 is a block diagram of a data transmission apparatus applied to an electronic device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to better understand the data transmission method applied to the electronic equipment, which is provided by the application, the following explanation is given to some technical terms related to the method, and the specific terms are as follows:
SPI (Serial Peripheral Interface) is a serial peripheral interface protocol, the SPI interface is a serial peripheral interface, and the SPI controller is a serial peripheral interface controller;
master: a master device;
slave: a slave device;
DMA controller: a DMA (Direct Memory Access ) controller is a hardware device that can be used to manage data transfers in a computer, and can directly access system memory and transfer data from an external device to memory or from memory to an external device without the intervention of a CPU. In this way, the CPU can focus on processing other tasks without waiting for the data transmission to complete, thereby improving the overall performance of the computer.
MTI signal: is an abbreviation of Master Transmit Interrupt, when a master initiates a data transfer, the MTI signal will be pulled high, indicating that the master is transferring data and that the slave should be ready to receive data. The slave device may use the MTI signal for interrupt control.
STI signal: is an abbreviation of Slave Transmit Interrupt, when a slave transmits data to a master, the STI signal will be pulled high, indicating that the slave is transmitting data. The master device can use the STI signal for interrupt control
CS signal: is an abbreviation for Chip Select, which indicates a Chip Select signal. Which is a signal in the communication interface for selecting the chip with which to communicate.
SCLK signal: is an abbreviation for Source Clock, which represents the Clock signal. Which is a clock signal used in the communication interface for synchronizing data transmission.
MISO signal: is an abbreviation of Master Input Slave Output, which indicates that the master inputs signals output from the device. Which is a signal in the communication interface that the slave device transmits data to the master device.
MOSI signal: is an abbreviation of Master Output Slave Input, which indicates that the master outputs a signal input from the slave. Which is a signal in the communication interface that the master transmits data to the slave.
MBuffer: representing a buffer in the host device for storing data.
SBuffer: representing buffers in the slave device for storing data.
Payload: representing the payload.
ACK (Acknowledge) signal: an acknowledgement signal representing a data frame.
In the embodiment of the application, the problems encountered in the traditional SPI communication can be solved from a physical layer, a link layer and a driving layer. The physical layer realizes two-way handshake communication by adding two signal lines, such as an STI signal line and an MTI signal, and improves transmission efficiency by adopting a DMA technology. The link layer is mainly in the logic level, defines the data frame format, and adds a check field to improve the utilization rate of the link bandwidth and check the correctness of the received data. The driving layer is mainly added with a confirmation mechanism and a buffer management mechanism, so that reliable data transmission is ensured, and the data transmission efficiency of the SPI is comprehensively improved.
A data transmission method and apparatus applied to an electronic device according to embodiments of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart of a data transmission method applied to an electronic device according to an embodiment of the present application, where the method provided by the embodiment of the present application may be executed by any electronic device having computer processing capability, where the electronic device includes a master device and a slave device, the master device is connected to the slave device through an SPI interface, a master DMA controller, a master SPI controller, and a master memory are disposed in the master device, and a slave DMA controller, a slave SPI controller, and a slave memory are disposed in the slave device.
As shown in fig. 1, the method includes steps S210 to S240.
In step S110, when the master transmits data to the slave, the first data to be transmitted is read from the main memory by the master DMA controller and written to the master buffer of the master.
In step S120, the sub data of the master buffer is transmitted to the slave device through the SPI interface by the master SPI controller.
In step S130, the received sub data is written to the slave buffer of the slave device by the slave SPI controller.
In step S140, the sub data of the slave buffer is read from the DMA controller and written to the slave memory.
The method can read the first data to be transmitted from the main memory through the main DMA controller and write the first data to be transmitted into the main buffer area of the main device when the main device transmits the data to the slave device, transmit the sub data of the main buffer area to the slave device through the SPI interface through the main SPI controller, write the received sub data into the slave buffer area of the slave device through the slave SPI controller, read the sub data of the slave buffer area from the DMA controller and write the sub data of the slave buffer area into the slave memory, and the data is transmitted in such a way that the data is not interfered by software, thereby improving the efficiency of the data transmission from the main device to the slave device.
In the related art, SPI communication has two roles of Master and Slave, and Master is responsible for read-write control of communication, and Slave responds according to the chip select signal and the clock signal of Master. The SPI communication system consists of 4 signal lines, CS is a chip selection signal, and when the Master pulls down the CS signal, the SPI controller of the Slave enters a ready state and transmits data when a clock is received. SCLK is a clock signal for outputting a communication clock to Slave. MISO and MOSI are data transfer signals, MISO is used to read data from Slave, and MOSI is used to write data to Slave. SPI communication is a loop communication, and a clock period Master end reads one bit data from the Slave through MISO, and simultaneously writes one bit data into the Slave through MOSI. In general, when the SPI controller configures and completes transmission of one byte or two bytes, an interrupt is generated, and the interrupt handler reads the data received in the buffer and resumes transmission, so that the data transmission in an interrupt manner is frequently interfered by the interrupt handler due to the process of data transmission, thereby reducing the efficiency of data transmission.
Aiming at the problems, in the method provided by the application, a Master DMA controller is deployed in a Master, and a Slave DMA controller is deployed in a Slave. Therefore, when the Master transmits data to the Slave, DMA can be adopted to improve the transmission efficiency. And the DMA transmission is used, software intervention in the data transmission process is eliminated, and the transmission efficiency is improved. In this embodiment, the size of the data frame sent by each SPI may be limited to a fixed value (for example, limited to 2 kbytes, which may be adjusted according to an actual application scenario) by using DMA, when the sending of the 2k data frame is completed, the DMA may trigger an interrupt, and at this time, software reads and processes the SBuffer data, and the data transmission process does not need software intervention.
In some embodiments, before the master device transmits data to the slave device, the method further comprises: the MTI signal is pulled up by the master device, and a first interrupt signal is sent to the slave device; receiving a first interrupt signal by the slave device, associating the storage space allocated by the slave memory to the slave DMA control according to the first interrupt signal, raising the STI signal by the slave device, and returning a second interrupt signal to the master device; and receiving a second interrupt signal through the main equipment, pulling down the MTI signal and the CS signal according to the second interrupt signal, and starting the main DMA controller.
In some embodiments, SPI bidirectional transmission is achieved using two conventional GPIO interfaces as interrupt acknowledgement signals. For example, the MTI is an interrupt signal output from the Master to the Slave, the STI is an interrupt signal output from the Slave to the Master, and the method of using the interrupt signal is described in the timing sequence, specifically, the timing sequence of transmitting data from the Master to the Slave is shown in fig. 3.
Referring to fig. 3, when the Master transmits data to the Slave, the SPI interface needs to be ensured to be idle before transmission, CS is high level, and STI and MTI are low level, specifically as follows:
a1: the Master pulls up the MTI signal and outputs a first interrupt signal to the Slave to inform the Slave that the Slave is ready to receive data.
A2: slave receives the MTI interrupt (i.e., first interrupt signal), and associates the memory space allocated from memory to the Slave DMA control ， And pulls the STI signal high, returning a second interrupt signal to the Master.
A3: the Master receives the STI interrupt (i.e., the second interrupt signal) and begins transmitting data while pulling down the MTI signal and the CS signal while the Master DMA controller is enabled.
A4: when the Master finishes transmitting data to the Slave, the Master pulls the CS signal high and the Slave pulls the STI signal low, and the SPI interface returns to an idle state.
In some embodiments, the first data to be transmitted is a first data frame generated according to a preset frame format, where the first data frame includes a first payload or a plurality of first payloads, a length of the first payload is smaller than a length of the first data frame, and a length of the plurality of first payloads and is smaller than a length of the first data frame. In the application, a preset frame format is customized according to actual requirements, and the specific table is as follows:
wherein, SOF: a start of frame, a frame start identifier, configured to determine whether valid data is loaded in a frame, where the frame is a fixed value of 0xCD 5A; multiple: a multiple of 256, an effective range of 1-127, with a highest bit of 1 indicating that this is an ACK frame; length: a byte count of less than 256; effective payload length of data frame: multiple 256+length, i.e., the number of bytes of payload1+ … … payload n; index: numbering of data frames, effective range 1-255, and the field is effective when effective data is transmitted; ACK-index: the number of the data frame is confirmed, and the effective range is 1 to 255. One data frame can carry valid data and ACK of the last data transmission at the same time, when bit7 of multiple is not 0, the data frame carries ACK, and the frame with ACK-index number is successfully received by the opposite terminal. When the index value is not 0, it indicates that the data frame carries valid data. TID: the receiving end is responsible for processing the module ID of the data packet, and the effective range is 1-255; len: the length of the data packet occupies 2 bytes; data: valid data of the data packet; CRC32: byte 0 to N-3, and the initial verification code calculated by the transmitting end.
Based on the foregoing embodiments, the sub-data is part of the content of the first data frame. The length of the first data frame may be set according to the actual transmission requirement, for example, fixed to 2k (2048 bytes), and the transmission time is T. When the length of the data packet to be transmitted by the upper layer is less than 2k, the time T is also consumed, and this time will cause bandwidth waste, and based on the above-mentioned custom data frame format, one data frame may contain multiple payload, and multiple payload is loaded in one data frame as much as possible, so as to improve the SPI bandwidth utilization.
Based on the foregoing embodiment, a CRC check field is added in the frame format, and after the link layer receives the data frame, it first determines whether the frame header is valid data, if so, the CRC is checked, and the data transmission is confirmed to be submitted to the driving layer.
In some embodiments, the method further includes pulling down the STI signal by the slave device and returning an acknowledgement signal of the first data frame to the master device when the transmission of data by the master device to the slave device ends, receiving the acknowledgement signal of the first data frame by the master device and pulling up the CS signal according to the acknowledgement signal of the first data frame, in this way, reliable transmission of data can be ensured to some extent, avoiding data errors. For example, for the driving layer, an ACK acknowledgement message (i.e. an acknowledgement signal of a data frame) is added to ensure reliable data transmission. The driving layer immediately gives a reply to the transmitting end (i.e. the master device) after receiving the data frame, and at this time, if the receiving end (i.e. the slave device) just has the data frame to transmit, an ACK acknowledgement message may be encapsulated into the data frame to be transmitted, where the ACK acknowledgement message indicates an acknowledgement signal of the previous transmission (i.e. an acknowledgement signal of the data frame transmitted from the master device to the slave device).
In some embodiments, the method further includes transmitting, by the master device, a data frame adjacent to the current first data frame to the slave device according to an acknowledgement signal of the current first data frame when the master device has a plurality of first data frames to transmit; if the master device does not receive an acknowledgement signal for the current first data frame, the transmission of the current first data frame to the slave device is continued, in this way the master buffer can be managed effectively. For example, for the driver layer, in cooperation with the ACK mechanism, the driver layer needs to increase a management policy for the data frame queue, so as to ensure reliable transmission of the SPI. Referring to fig. 5, the driving layer maintains a transmit data frame queue, black arrows point to the head of the frame queue, representing the next data frame to be transmitted, gray arrows represent the tail of the frame queue, and fills the data frame of gray arrows when there is a new data packet to be transmitted at the upper layer, and moves the gray arrow to the next data frame if the data frame is full. And after receiving the ACK confirmation message, the transmitting end releases the data frame pointed by the black arrow, namely the data frame adjacent to the current data frame.
In some embodiments, the data frame transmitted to the slave device is a first data frame when the master device is a sender, and the data frame transmitted to the master device is a second data frame when the slave device is a sender.
In some embodiments, the method further includes when the slave device receives the first data frame, determining, by the slave device, whether a frame start identifier of the first data frame is a first preset identifier, if the frame start identifier of the first data frame is the first preset identifier, generating a first target check code of the first data frame based on all bytes in the first data frame except bytes corresponding to the first initial check code, and determining whether the first data frame is valid according to the first initial check code and the first target check code, so that the correctness of the data can be checked.
Fig. 2 is a flowchart of another data transmission method applied to an electronic device according to an embodiment of the present application.
As shown in fig. 2, the above method may further include steps S210 to S260.
In step S210, a third interrupt signal is transmitted to the master device by pulling up the STI signal from the slave device.
In step S220, the third interrupt signal is received by the host device, and the CS signal is pulled down and the host DMA controller is started according to the third interrupt signal.
In step S230, the second data to be transferred is read from the slave memory by the slave DMA controller and written to the slave buffer of the slave device.
In step S240, the sub data of the slave buffer is transmitted to the master device through the SPI interface by the slave SPI controller.
In step S250, the received sub data is written to the main buffer of the master device by the master SPI controller.
In step S260, the sub data of the main buffer is read by the main DMA controller and written to the main memory.
According to the method, the STI signal can be pulled up by the slave device, the third interrupt signal is sent to the master device, the third interrupt signal is received by the master device, the CS signal is pulled down according to the third interrupt signal, the master DMA controller is started, the second data to be transmitted is read from the slave memory by the slave DMA controller, the second data to be transmitted is written into the slave buffer area of the slave device, the sub data of the slave buffer area is transmitted to the master device through the SPI interface by the slave SPI controller, the received sub data is written into the master buffer area of the master device by the master SPI controller, the sub data of the master buffer area is read by the master DMA controller, and the sub data of the master buffer area is written into the master memory, so that the slave device can actively initiate data transmission to the master device, and the data transmission efficiency can be improved based on the data transmission by the DMA controller.
In some embodiments, SPI bidirectional transmission is achieved using two conventional GPIO interfaces as interrupt acknowledgement signals. For example, the MTI is an interrupt signal output from the Master to the Slave, the STI is an interrupt signal output from the Slave to the Master, and the method of using the interrupt signal is described in the timing sequence, specifically, the timing sequence of transmitting data from the Slave to the Master as shown in fig. 4.
Referring to fig. 4, when the Slave transmits data to the Master, the SPI interface needs to be ensured to be idle before transmission, CS is high level, and STI and MTI are low level, specifically as follows:
b1: slave pulls up the STI signal, outputs a third interrupt signal to the Master, informing the Master that data is ready to be received.
B2: the Master receives the STI interrupt (i.e., the third interrupt signal), correlates the memory space allocated by the main memory to the main DMA controller, and pulls down the CS signal to begin receiving data.
B3: when the data transmission from the Slave to the Master is finished, the Master pulls the CS signal high, the Slave pulls the STI signal low, and the SPI interface returns to an idle state.
In some embodiments, the second data to be transmitted is a second data frame generated according to a preset frame format, wherein the second data frame includes a second payload or a plurality of second payloads, a length of the second payload is less than a length of the second data frame, and a length of the plurality of second payloads and is less than a length of the second data frame. In this embodiment, the frame format of the second data frame is the same as the frame format of the first data frame described above.
In some embodiments, the method further includes pulling up the CS signal by the master device and returning an acknowledgement signal of the second data frame to the slave device when the transmission of the data from the slave device to the master device is completed, and receiving the acknowledgement signal of the second data frame by the slave device and pulling down the STI signal according to the acknowledgement signal of the second data frame in such a way that reliable transmission of the data can be ensured to some extent, avoiding data errors. In this embodiment, the ACK mechanism is the same as the above-described acknowledgement manner when the master transmits data to the slave.
In some embodiments, the method further includes transmitting, by the slave device, a data frame adjacent to the current second data frame to the master device according to an acknowledgement signal of the current second data frame when the slave device has a plurality of second data frames to transmit; if the slave device does not receive an acknowledgement signal for the current second data frame, the transmission of the current second data frame to the master device continues in such a way that the slave buffer can be managed effectively. In this embodiment, the management policy of the data frame queue of the slave device is the same as that of the master device described above.
In some embodiments, the method further includes when the master device receives the second data frame, determining, by the master device, whether a frame start identifier of the second data frame is a second preset identifier, if the frame start identifier of the second data frame is the second preset identifier, generating a second target check code of the second data frame based on all bytes in the second data frame except bytes corresponding to the second initial check code, and determining whether the second data frame is valid according to the second initial check code and the second target check code, so that the correctness of the data can be checked.
Fig. 6 is a block diagram of a data transmission apparatus applied to an electronic device according to an embodiment of the present application. In the embodiment of the application, the electronic equipment comprises a master equipment and a slave equipment, wherein the master equipment is connected with the slave equipment through an SPI interface, a master DMA controller, a master SPI controller and a master memory are arranged in the master equipment, and a slave DMA controller, a slave SPI controller and a slave memory are arranged in the slave equipment.
As shown in fig. 6, the data transmission apparatus 600 applied to an electronic device includes a first writing module 610, a transmission module 620, a second writing module 630, and a third writing module 640.
Specifically, the first writing module 610 is configured to, when the master device transfers data to the slave device, read, by the master DMA controller, the first data to be transferred from the master memory, and write the first data to be transferred to the master buffer of the master device.
And the transmission module 620 is configured to transmit, by the master SPI controller, the sub data of the master buffer to the slave device through the SPI interface.
A second writing module 630 is configured to write the received sub data to the slave buffer of the slave device by the slave SPI controller.
A third writing module 640 for reading the sub data of the slave buffer from the DMA controller and writing the sub data of the slave buffer to the slave memory.
The data transmission apparatus 600 applied to an electronic device may read first data to be transmitted from a main memory through a main DMA controller and write the first data to be transmitted to a main buffer of the main device when the main device transmits data to the slave device, transmit sub data of the main buffer to the slave device through an SPI interface through the main SPI controller, write received sub data to a slave buffer of the slave device through the slave SPI controller, and read sub data of the slave buffer from the DMA controller and write sub data of the slave buffer to the slave memory, in such a way that the transmission data is not interfered by software, thereby improving the efficiency of the main device transmitting data to the slave device.
In some embodiments, the data transmission apparatus 600 applied to the electronic device described above is further used for, before the master device transmits data to the slave device: the MTI signal is pulled up by the master device, and a first interrupt signal is sent to the slave device; receiving a first interrupt signal by the slave device, associating the storage space allocated by the slave memory to the slave DMA controller according to the first interrupt signal, pulling up the STI signal by the slave device, and returning a second interrupt signal to the master device; and receiving a second interrupt signal through the main equipment, pulling down the MTI signal and the CS signal according to the second interrupt signal, and starting the main DMA controller.
In some embodiments, when the slave device transmits data to the master device, the data transmission apparatus 600 applied to the electronic device is further configured to: sending a third interrupt signal to the master device by pulling up the STI signal by the slave device; receiving a third interrupt signal through the main equipment, pulling down the CS signal according to the third interrupt signal, and starting the DMA controller; reading second data to be transmitted from the slave memory by the slave DMA controller, and writing the second data to be transmitted into a slave buffer of the slave device; transmitting the sub data of the slave buffer to the master device through the SPI interface by the slave SPI controller; writing the received sub data into a main buffer area of the main equipment through a main SPI controller; the sub data of the main buffer is read by the main DMA controller and written to the main memory.
In some embodiments, the data transmission apparatus 600 applied to the electronic device is further configured to: when the transmission of data from the master device to the slave device is finished, pulling down the STI signal by the slave device, returning an acknowledgement signal of the first data frame to the master device, receiving the acknowledgement signal of the first data frame by the master device, and pulling up the CS signal according to the acknowledgement signal of the first data frame; when the transmission of data from the slave device to the master device is finished, the CS signal is pulled up by the master device, an acknowledgement signal of the second data frame is returned to the slave device, the acknowledgement signal of the second data frame is received by the slave device, and the STI signal is pulled down according to the acknowledgement signal of the second data frame.
In some embodiments, the data transmission apparatus 600 applied to the electronic device is further configured to: when the master device has a plurality of first data frames to be transmitted, transmitting data frames adjacent to the current first data frames to the slave device through the master device according to the acknowledgement signals of the current first data frames; if the master device does not receive the acknowledgement signal of the current first data frame, continuing to transmit the current first data frame to the slave device; when the slave device has a plurality of second data frames to be transmitted, transmitting the data frames adjacent to the current second data frames to the master device through the slave device according to the acknowledgement signals of the current second data frames; if the slave device does not receive an acknowledgement signal for the current second data frame, continuing to transmit the current second data frame to the master device.
In some embodiments, the data transmission apparatus 600 applied to the electronic device is further configured to: when a first data frame is received by a slave device, judging whether a frame start identifier of the first data frame is a first preset identifier by the slave device, if the frame start identifier of the first data frame is the first preset identifier, generating a first target check code of the first data frame based on all bytes except bytes corresponding to the first initial check code in the first data frame, and determining whether the first data frame is valid or not according to the first initial check code and the first target check code; when the main equipment receives the second data frame, judging whether the frame starting identification of the second data frame is a second preset identification through the main equipment, if the frame starting identification of the second data frame is the second preset identification, generating a second target check code of the second data frame based on all bytes except bytes corresponding to the second initial check code in the second data frame, and determining whether the second data frame is valid or not according to the second initial check code and the second target check code.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
As shown in fig. 7, the electronic device 700 of this embodiment includes a master device 710 and a slave device 720, and the master device 710 and the slave device 720 are connected through an SPI interface. The master device 710 is provided with a master DMA controller, a master SPI controller, a master processor, a master memory, and a computer program stored in the master memory and executable on the master processor, which when executed controls the master DMA controller and the master SPI controller to implement the corresponding steps of the above-described method.
The slave device 720 is provided with a slave DMA controller, a slave SPI controller, a slave processor, a slave memory, and a computer program stored in the slave memory and executable on the slave processor, which when executed controls the slave DMA controller and the slave SPI controller to carry out the corresponding steps of the above method.
In this embodiment, when the host processor executes the computer program, the host DMA controller and the host SPI controller are controlled to implement the functions of the corresponding modules in the embodiments of the apparatus described above.
In this embodiment, the slave processor, when executing the computer program, controls the slave DMA controller and the slave SPI controller to realize the functions of the corresponding modules in the above-described respective device embodiments.
The electronic device 700 may be a desktop computer, a notebook computer, a palm computer, a cloud server, or the like. It will be appreciated by those skilled in the art that fig. 7 is merely an example of an electronic device 700 and is not limiting of the electronic device 700 and may include more or fewer components than shown, or different components.
The processor may be a central processing unit (Central Processing Unit, CPU) or other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.
The memory may be an internal storage unit of the electronic device 700, for example, a hard disk or a memory of the electronic device 700. The memory may also be an external storage device of the electronic device 700, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device 700. The memory may also include both internal and external memory units of the electronic device 700. The memory is used to store computer programs and other programs and data required by the electronic device.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit.
The integrated modules, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. The computer program may comprise computer program code, which may be in source code form, object code form, executable file or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the content of the computer readable medium can be appropriately increased or decreased according to the requirements of the jurisdiction's jurisdiction and the patent practice, for example, in some jurisdictions, the computer readable medium does not include electrical carrier signals and telecommunication signals according to the jurisdiction and the patent practice.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The data transmission method applied to the electronic equipment is characterized in that the electronic equipment comprises a master equipment and a slave equipment, wherein a master DMA controller, a master SPI controller and a master memory are arranged in the master equipment, a slave DMA controller, a slave SPI controller and a slave memory are arranged in the slave equipment, and the master equipment is connected with the slave equipment through an SPI interface, and the method comprises the following steps:
when the master device transmits data to the slave device, reading first data to be transmitted from the main memory through the main DMA controller, and writing the first data to be transmitted into a main buffer area of the master device;
transmitting the sub data of the main buffer area to the slave device through the SPI interface by the main SPI controller;
writing the received sub data into a slave buffer of the slave device through the slave SPI controller;
and reading the sub data of the slave buffer by the slave DMA controller, and writing the sub data of the slave buffer into the slave memory.
2. The method of claim 1, wherein prior to the master device transmitting data to the slave device, the method further comprises:
pulling up an MTI signal through the master device, and sending a first interrupt signal to the slave device;
receiving the first interrupt signal by the slave device, and associating the storage space allocated by the slave memory to the slave DMA controller according to the first interrupt signal;
pulling up an STI signal through the slave device and returning a second interrupt signal to the master device;
and receiving the second interrupt signal through the master device, pulling down the MTI signal and the CS signal according to the second interrupt signal, and starting the master DMA controller.
3. The method of claim 2, wherein when the slave device transmits data to the master device, the method further comprises:
pulling up the STI signal by the slave device, and sending a third interrupt signal to the master device;
receiving the third interrupt signal by the master device, pulling down the CS signal according to the third interrupt signal, and starting the master DMA controller;
reading second data to be transmitted from the slave memory by the slave DMA controller, and writing the second data to be transmitted into a slave buffer of the slave device;
transmitting the sub data of the slave buffer area to the master device through the SPI interface by the slave SPI controller;
writing the received sub data into a main buffer area of the main equipment through the main SPI controller;
and reading the sub data of the main buffer area through the main DMA controller, and writing the sub data of the main buffer area into the main memory.
4. A method according to claim 1 or 3, wherein the first data to be transmitted is a first data frame generated according to a preset frame format, wherein the first data frame comprises a first payload or a plurality of first payloads, the length of a first payload being smaller than the length of the first data frame, the sum of the lengths of a plurality of first payloads being smaller than the length of the first data frame;
the second data to be transmitted is a second data frame generated according to the preset frame format, wherein the second data frame comprises a second payload or a plurality of second payloads, the length of one second payload is smaller than the length of the second data frame, and the length of the plurality of second payloads is smaller than the length of the second data frame.
5. The method according to claim 4, wherein the method further comprises:
when the transmission of data to the slave device by the master device is finished, pulling down the STI signal by the slave device, returning an acknowledgement signal of the first data frame to the master device, receiving the acknowledgement signal of the first data frame by the master device, and pulling up the CS signal according to the acknowledgement signal of the first data frame;
and when the transmission of data from the slave device to the master device is finished, pulling up the CS signal through the master device, returning an acknowledgement signal of the second data frame to the slave device, receiving the acknowledgement signal of the second data frame through the slave device, and pulling down the STI signal according to the acknowledgement signal of the second data frame.
6. The method of claim 5, wherein the method further comprises:
when the master device has a plurality of first data frames to be transmitted, transmitting data frames adjacent to the current first data frames to the slave device through the master device according to acknowledgement signals of the current first data frames; if the master device does not receive the acknowledgement signal of the current first data frame, continuing to transmit the current first data frame to the slave device;
when the slave device has a plurality of second data frames to be transmitted, transmitting data frames adjacent to the current second data frames to the master device through the slave device according to acknowledgement signals of the current second data frames; and if the slave device does not receive the acknowledgement signal of the current second data frame, continuing to transmit the current second data frame to the master device.
7. The method according to claim 4, further comprising
When the slave device receives the first data frame, judging whether a frame start identifier of the first data frame is a first preset identifier by the slave device, if the frame start identifier of the first data frame is the first preset identifier, generating a first target check code of the first data frame based on all bytes except bytes corresponding to a first initial check code in the first data frame, and determining whether the first data frame is valid or not according to the first initial check code and the first target check code;
when the master device receives the second data frame, judging whether a frame start identifier of the second data frame is a second preset identifier by the master device, if the frame start identifier of the second data frame is the second preset identifier, generating a second target check code of the second data frame based on all bytes except bytes corresponding to a second initial check code in the second data frame, and determining whether the second data frame is valid according to the second initial check code and the second target check code.
8. A data transmission device applied to an electronic device, wherein the electronic device includes a master device and a slave device, a master DMA controller, a master SPI controller, and a master memory are disposed in the master device, a slave DMA controller, a slave SPI controller, and a slave memory are disposed in the slave device, and the master device is connected with the slave device through an SPI interface, the device comprising:
a first writing module, configured to read, by the master DMA controller, first data to be transferred from the master memory and write the first data to be transferred to a master buffer of the master device when the master device transfers data to the slave device;
the transmission module is used for transmitting the sub data of the main buffer area to the slave equipment through the SPI interface through the main SPI controller;
the second writing module is used for writing the received sub data into a slave buffer area of the slave device through the slave SPI controller;
and the third writing module is used for reading the sub data of the slave buffer area through the slave DMA controller and writing the sub data of the slave buffer area into the slave memory.
9. The electronic equipment is characterized by comprising a master device and a slave device, wherein the master device and the slave device are connected through an SPI interface;
a main DMA controller, a main SPI controller, a main processor, a main memory, and a computer program stored in the main memory and executable on the main processor, which when executed by the main processor controls the main DMA controller and the main SPI controller to implement the corresponding steps of the method according to any one of claims 1 to 7;
the slave device having disposed therein a slave DMA controller, a slave SPI controller, a slave processor, a slave memory, and a computer program stored in the slave memory and executable on the slave processor, when executing the computer program, controlling the slave DMA controller and the slave SPI controller to implement the corresponding steps of the method according to any one of claims 1 to 7.
10. A computer readable storage medium storing a computer program, wherein execution of the computer program by a host processor controls a host DMA controller and a host SPI controller to implement the corresponding steps of the method according to any one of claims 1 to 7;
the computer program being executed by a slave processor controls the slave DMA controller and the slave SPI controller to carry out the corresponding steps of the method according to any one of claims 1 to 7.
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| CN117234977A (en) * | 2023-11-10 | 2023-12-15 | 浪潮电子信息产业股份有限公司 | Data processing method, system, device and computer readable storage medium |
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