JP2009186616A - Liquid crystal display device, drive device for liquid crystal display device, method of driving liquid crystal display device, and television receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a display noise in the screen central part when the number of lines is fluctuated, in a liquid crystal display device combined with a screen division system and a pixel division system (Cs swing type). <P>SOLUTION: The liquid crystal display device defines scanning timing of a pixel in the second area in response to actual scan starting timing GSCx in the first area, in scanning of a current frame in the second area performed after starting the scanning of the current frame in the first area, level-shifts a holding capacitive wire signal supplied to each of holding capacitive wires Cs542, etc. forming a pixel and a capacity of the second area, to previous side by a prescribed time (for example, 9H period) or more than the defined scanning timing of the pixel in the second area, and sets the same level to be maintained till the scanning timing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device that divides a display unit into a plurality of regions and scans scanning signal lines for each region.

The display unit is divided into multiple areas and each area is driven separately in order to cope with the shortening of the writing time to each pixel accompanying the high definition of the liquid crystal display and the dullness of the signal waveform accompanying the enlargement of the display. The structure which performs is proposed (refer the screen division system, for example, patent document 1). In this screen division method, for example, when one screen is divided vertically (the upper area is the first area and the lower area is the second area), the first half of the frame is displayed in the first area and the second area is displayed. Displays the second half of the frame. On the other hand, in order to improve the viewing angle dependency of the γ characteristic (for example, to suppress whitening of the screen), a plurality of subpixels provided in one pixel are controlled to have different luminances, and the area gradation of these subpixels is controlled. A configuration for displaying a halftone (screen division method, for example, see Patent Document 2) has also been proposed. In the liquid crystal display device described in Patent Document 2, a plurality of subpixels in one pixel have different luminances by supplying a Cs signal to a storage capacitor wiring (Cs wiring) that forms a storage capacitor with a pixel electrode in the subpixel. Controlled (Cs swing type).
JP 10-268261 A (publication date: October 9, 1998) Japanese Patent Laying-Open No. 2004-62146 (released on February 26, 2004)

  Here, in the liquid crystal display device that combines the screen division method and the pixel division method (Cs swing type), the inventors of the present application have changed the number of lines of the Nth frame and the previous frames by switching channels or fast-forwarding. Display noise occurs at the upper end of each of the first and second areas, and particularly the display noise at the upper end of the second area (lower area) located at the center of the screen is of display quality. We found the problem that caused the decline and the cause. This will be described below.

  First, FIG. 24 illustrates a screen configuration example of a screen division type liquid crystal display device. As shown in FIG. 24, scanning signal lines g1 to g540 and storage capacitor lines cs1 to cs541 are provided in the first region, and scanning signal lines g541 to g1080 and storage capacitor wires cs542 to cs1082 are provided in the second region. Is provided. In this liquid crystal display device, as shown in FIG. 27B, the first half ax of the first frame a is written in the first area, and then the second half ay of the first frame a is written in the second area. The first half bx of the second frame b is written in the first area so as to overlap with the writing period of the second half ay of the frame a, and then the second half by of the second frame b is written in the second area. Write. Then, the first half cx of the third frame c is written to the first area so as to overlap with the writing period of the second half by of the frame b, and then the second half Cy of the third frame c is written to the second area. Write to. FIG. 27A shows the input timing of frames a to d. In FIG. 27, the vertical synchronization signals of frames a to d are VSa to VSd, and the periods (Vta to Vtd) is equally 1120 lines (of which the blanking period is 40 lines).

  In FIG. 27B, the gate start pulse of the first half frame ax is GSax, the gate start pulse of the first half frame bx is GSbx, the gate start pulse of the first half frame cx is GScx, and the gate start pulse of the first half frame dx is GSdx. The gate start pulse GSax of the frame ax and the vertical synchronization signal VSa of the frame a are synchronized, the gate start pulse GSbx of the first half frame bx and the vertical synchronization signal VSb of the frame b are synchronized, and the gate start pulse GScx of the first frame cx The vertical synchronization signal VSc of the frame c is synchronized, and the gate start pulse GSdx of the first half frame dx and the vertical synchronization signal VSd of the frame d are synchronized. Further, the periods (Vtax to Vtdx) of the first half frames ax to dx are equally set to 560 lines (of which the blanking period is 20 lines).

  In FIG. 27B, the gate start pulse of the second half frame ay is GSay, the gate start pulse of the second half frame by is GSby, the gate start pulse of the second half frame cy is GScy, and the gate start pulse of the second half frame dy is GSdy. The gate start pulse GSay in the second half frame ay becomes active after the period w (a period equal to the scanning period of 540 lines) has elapsed from the gate start pulse GSax in the first half frame ax. The gate start pulse GScy of the second half frame cy becomes active after the period w has elapsed from the gate start pulse GSbx of the first half frame bx, and the period w from the gate start pulse GScx of the first half frame cx becomes active. After over, the gate start pulse GSdy of the second half frame dy is active, has become after the lapse of the period w from the gate start pulse GSdx of the first half frame dx. Further, the respective periods (Vtay to Vtdy) of the latter half frames ay to dy are equally set to 560 lines (of which the blanking period is 20 lines).

  As shown in FIGS. 27 (a) and 27 (b), in the split screen type liquid crystal display device, for example, it is only necessary to output (scan) 540 lines during an input period of 1080 lines. The horizontal scanning period) can be twice as long as 1H (one horizontal scanning period) on the input side, and the charging rate of each pixel can be increased.

  FIGS. 25A, 25B and 26A, 26B are schematic views showing specific configurations of the respective regions of the liquid crystal display device. In the first region, as shown in FIGS. 25A and 25B, two subpixels arranged in the column direction (data signal line direction) are provided in one pixel, and these subpixels are provided with separate storage capacitor wirings. And form a storage capacitor. That is, if an i-th pixel (i is an integer of 1 to 540) in an arbitrary pixel column is defined as a pixel pi, the pixel pi includes two sub-pixels spai, which are connected to the scanning signal line gi and the data signal line sl. The pixel electrode in the sub-pixel spi forms a storage capacitor line csi and a storage capacitor, and the pixel electrode in the sub-pixel spbi forms a storage capacitor line cs (i + 1) and a storage capacitor. For example, the pixel p1 connected to the scanning signal line g1 and the data signal line sl has two subpixels spa1 and spb1, and the pixel electrode in the subpixel spa1 forms a storage capacitor line cs1 and a storage capacitor. In addition, the pixel electrode in the sub-pixel spb1 forms the storage capacitor line cs2 and the storage capacitor.

  Also in the second region, as shown in FIGS. 26A and 26B, two subpixels arranged in the column direction (data signal line direction) are provided in one pixel, and these subpixels are provided with separate storage capacitor wirings. And form a storage capacitor. That is, if the j-th pixel (j is an integer from 541 to 1080) in the arbitrary pixel column is defined as a pixel pj, the pixel pj includes two sub-pixels spaj, which are connected to the scanning signal line gj and the data signal line sL. a pixel electrode in the sub-pixel spaj forms a storage capacitor with a storage capacitor line cs (j + 1), and a pixel electrode in the sub-pixel spbj forms a storage capacitor with a storage capacitor line cs (j + 2). . For example, the pixel p541 connected to the scanning signal line g541 and the data signal line sL has two subpixels spa541 and spb541, and the pixel electrode in the subpixel spa541 forms a storage capacitor and a storage capacitor cs542. The pixel electrode in the sub-pixel spb 541 forms a storage capacitor with the storage capacitor line cs 543.

  29 and 30 show the input vertical synchronization signal VSYNC, video data DAT, gate start pulse (GSP) supplied to each gate driver for driving the first and second regions, and each scan of the first and second regions. 5 is a timing chart showing a gate-on pulse supplied to a signal line and a Cs signal (Scs) supplied to each storage capacitor wiring in the first and second regions. As shown in FIGS. 29 and 30, the storage capacitor wiring signal (Cs signal) supplied to the storage capacitor wiring has “H (High)” and “L (Low)” alternately by a periodic level shift. This is a pulse signal that is switched, and the period (pulse width) of the level shift is, for example, 12H (1H is one horizontal scanning period on the output side).

  That is, in the first region, as shown in FIGS. 25A and 25B and FIGS. 29 and 30, the Cs signal scsi and the storage capacitor wiring supplied to the storage capacitor wiring csi (i is an integer of 1 to 540). The Cs signal scs (i + 1) supplied to cs (i + 1) is level-shifted in the opposite direction (push-up / down direction) after the scanning of the scanning signal line gi. Thus, one potential of the two subpixels (spai / spbi) can be swung up with respect to the writing potential from the data signal line sl, and the other potential can be swung down with respect to the writing potential. The pixels spai and spbi can be controlled to have different luminances. For example, the Cs signal scs1 supplied to the storage capacitor line cs1 is level-shifted (pushed up) from “L” to “H” after the scanning of the scanning signal line g1 is finished, while the Cs signal scs2 supplied to the storage capacitor line cs2 The level shifts from “H” to “L” (pushes down) after the scanning of the scanning signal line g1 is completed. As a result, the potential of the subpixel spa1 can be swung up with respect to the writing potential from the data signal line sl, and the potential of the subpixel spb1 can be swung down with respect to the writing potential. For example, the subpixels spa1 and spb1 can be a bright subpixel and a dark subpixel, respectively.

  Similarly, in the second region, as shown in FIGS. 26A and 26B and FIGS. 29 and 30, the Cs signal scs supplied to the storage capacitor wiring cs (j + 1) (j is an integer of 541 to 1080). The Cs signal scs (j + 2) supplied to (j + 1) and the storage capacitor wiring cs (j + 2) is level-shifted in the opposite directions (pushing up / down direction) after the scanning of the scanning signal line gj. Thus, one potential of the two sub-pixels (spaj / spbj) can be swung up with respect to the writing potential from the data signal line sL, and the other potential can be swung down with respect to the writing potential. The pixels spaj and spbj can be controlled to have different luminances. For example, the Cs signal scs 542 supplied to the storage capacitor line cs 542 is level-shifted (pushed up) from “L” to “H” after the scanning of the scanning signal line g 541 is completed, while the Cs signal scs 543 supplied to the storage capacitor line cs 543. Shifts (lowers) the level from “H” to “L” after the scanning of the scanning signal line g541 is completed. Accordingly, the potential of the sub-pixel spa 541 can be swung up with respect to the writing potential from the data signal line sl, and the potential of the sub-pixel spb 541 can be swung down with respect to the writing potential. For example, the subpixels spa541 and spb541 can be a bright subpixel and a dark subpixel, respectively.

  Here, the Cs signal is set as follows in order to control each sub-pixel in one pixel to the expected luminance in consideration of the dullness of the potential waveform of the storage capacitor wiring to some extent. That is, as shown in FIG. 30, the Cs signal scsi and the Cs signal scs (i + 1) given to the first region are leveled for a predetermined period (for example, 9H) or more before scanning of the scanning signal line gi (pixel pi). The Cs signal scs (j + 1) and the Cs signal scs (j + 2) given to the second region are set to be shifted to maintain the same level until the scanning and to shift the level after the scanning. It is set so that the level is shifted a predetermined period (for example, 9H) or more before the scanning of the line gj (pixel pj), the same level is maintained until the scanning timing, and the level is shifted after this scanning.

  For example, the Cs signal scs2 applied to the first region is level-shifted from “H” to “L” 10H before scanning of the scanning signal line g1, so that the Cs signal scs2 is 10H of scanning of the scanning signal line g1. It is set to shift the level from “L” to “H” before. Further, the Cs signal scs 543 given to the second region is level-shifted from “H” to “L” 10H before the scanning start of the scanning signal line g541, so that the Cs signal scs 543 starts scanning 10H of the scanning signal line g541. It is set to shift the level from “L” to “H” before.

  However, in order to shift the level of the Cs signal scs1 or the Cs signal scs2 10H before the scanning of the scanning signal line g1, it is necessary to predict the scanning timing of the scanning signal line g1. Therefore, as shown in FIGS. 27C and 30, assuming that Vtbx = Vtax, the predictive scanning start timing Tcxu of the first half cx of the current frame c is set to the gate start pulse of the first half bx of the previous frame b. It is assumed that Vtax has elapsed since GSbx (same timing as the vertical synchronization signal VSb of frame b). That is, the Cs signal scs1 is level-shifted from “H” to “L” 10H before the timing Tcxu, and the Cs signal scs2 is level-shifted from “L” to “H” 10H before the timing Tcxu. Set to. The odd-numbered Cs signals after the Cs signal scs1 are level-shifted from “L” to “H” with a delay of 2H, and the even-numbered Cs signals after the Cs signal scs2 are delayed by 2H with a delay of “H” to “L”. "Is set to level shift.

  Similarly, the scanning timing of the scanning signal line g541 is predicted in order to level shift the Cs signal scs542 and the Cs signal scs543 10H before the scanning of the scanning signal line g541. That is, as shown in FIGS. 27C and 30, assuming that Vtby = Vtay, the predictive scanning start timing Tcyu of the second half cy of the current frame c is set to the gate start pulse of the second half by the previous frame b. After GSby (timing after the elapse of the period w from the vertical synchronization signal VSb of the frame b), it is after the elapse of Vtay. That is, the Cs signal scs 542 is level-shifted from “H” to “L” 10H before the timing Tcyu, and the Cs signal scs 543 is level-shifted from “L” to “H” 10H before the timing Tcxu. Set to. The even-numbered Cs signals after the Cs signal Scs542 are level-shifted from “H” to “L” with a delay of 2H, and the odd-numbered Cs signals after the Cs signal Scs543 are delayed by “2H” from “L” to “H”. "Is set to level shift.

  However, when each Cs signal is set as described above, the following problems occur when there is a variation in the frame period (Vtby ≠ Vtay) or when the input vertical synchronization signal is disturbed. appear.

  For example, as shown in FIGS. 28A and 28B, when Vta = 1120, Vtb = 1110, Vtay = 560, and Vtby = 555, as shown in FIG. 28C and FIG. The actual scanning start timing of the first half cx of the current frame c is earlier than the predictive scanning start timing Tcxu of the first half cx of the current frame c by 5 line scanning periods, and 5H before scanning of the scanning signal line g1. The Cs signal scs1 and the Cs signal scs2 are level shifted. For this reason, the potentials of the storage capacitor wirings cs1 and cs2 are not completely “L” during scanning of the scanning signal line g1 (charging of cs1 and cs2 is insufficient), and the sub-pixels (spa1 and spb1) of the pixel p1 are There is a risk that the brightness cannot be controlled as expected (resulting in display noise).

  In this case (when Vtay = 560 and Vtby = 555), as shown in FIGS. 28C and 31, the actual scanning start timing of the second half cy of the current frame c is the second half cy of the current frame c. Thus, the Cs signal scs 542 and the Cs signal scs 543 are level-shifted 5H before the scanning of the scanning signal line g541. For this reason, the potentials of the storage capacitor wirings cs542 and cs543 are not completely “L” during scanning of the scanning signal line g541 (the charge of cs542 and cs543 is insufficient), and the subpixels (spa541 and spb541) of the pixel p541 are set. There is a risk that the brightness cannot be controlled as expected (resulting in display noise). In FIG. 31, each Cs signal is corrected at the timing of GScy. However, the scanning signal lines g541 to g548 and the storage capacitor lines cs542 to cs550 (for nine lines) that form the capacitance are as described above. The problem of insufficient charging occurs.

  As described above, in the liquid crystal display device that combines the screen division method and the pixel division method (Cs swing type), when the fluctuation of one frame period (number of one frame line) or the disturbance of the vertical synchronization signal occurs, Display noise occurs at the upper end of each of the first and second areas (which varies depending on the charging characteristics of the storage capacitor wiring, for example, about 9 lines), and particularly the display of the upper end of the second area (lower area) located at the center of the screen. It is thought that noise causes a reduction in display quality.

  The present invention has been made in view of the above problems, and an object of the present invention is to propose a configuration in which display noise hardly occurs in the center of the screen in a liquid crystal display device that combines the screen division method and the pixel division method (Cs swing type). There is.

  In the present liquid crystal display device, a data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display unit, and the first region is scanned by scanning in the first region of the current frame. A liquid crystal display device in which a part of a current frame is written in an area, and the remainder of the current frame is written in the second area by scanning in the second area of the current frame, and a plurality of pixels provided in one pixel Each of the sub-pixels is connected to the same scanning signal line and forms a different storage capacitor line and capacitance, and each storage capacitor line is supplied with a storage capacitor line signal whose level is switched by a periodic level shift. In scanning in the second region of the current frame, which is performed after the start of scanning in the first region of the frame, the scanning timing of the pixels in the second region is the actual scanning start timing in the first region. And a storage capacitor wiring signal that is supplied to each of the plurality of storage capacitor wirings that form a capacitance with the pixels in the second region is a predetermined period of time than the scanning timing defined for the pixels in the second region. It is characterized in that it is set so that the level is shifted before and the same level is maintained until the scanning timing.

  In this way, the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings that form the capacitance with the pixels in the second region is more predetermined than the timing defined according to the actual scanning start timing in the first region. If it is set so that the level is shifted before the period and the same level is maintained until the scanning timing (substantially), the number of lines varies (the frame period varies between the current frame and the previous frame). The storage capacitor wiring that forms a capacitance with an arbitrary pixel in the second region (particularly, the pixel at the scanning upstream edge of the second region) is sufficiently charged before the scanning timing of the pixel. be able to. As a result, insufficient charge of the storage capacitor wiring that forms the capacitance with the pixels of the edge portion when the number of lines varies can be solved, and display noise at the center of the screen can be suppressed.

  In the present liquid crystal display device, the prescribed scanning timing of the pixels in the second region is a timing after the passage of a period corresponding to this pixel from the actual start of scanning in the first region, and the pixels in the second region The storage capacitor line signal supplied to each of the plurality of storage capacitor lines forming the capacitor is at least a predetermined period before the timing after the period corresponding to the pixel has elapsed from the start of actual scanning in the first region. It is also possible to adopt a configuration in which the level is shifted and set to maintain the same level until the timing.

  In the present liquid crystal display device, the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming a capacitor with the pixel in the second region is set based on a signal notifying the actual start of scanning in the first region. It can also be set as the structure made.

  In the present liquid crystal display device, the pixel in the second region forms a capacity with two storage capacitor lines, and the storage capacitor line signal supplied to each of the two storage capacitor lines is scanned as defined above. It is also possible to adopt a configuration in which the level is shifted in the reverse direction after the timing.

  In the present liquid crystal display device, the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming the capacitance with the pixels in the first region is the prediction of the first region obtained from the frame period of the frame before the current frame. Based on the typical scanning start timing, the level is shifted a predetermined period or more before the predictive scanning timing of the pixels in the first region, and the level is set to be maintained until the scanning timing. You can also.

  In the present liquid crystal display device, when the predictive scan start timing of the first region is different from the actual scan start timing, each of the plurality of storage capacitor wirings forming a capacitance with the predetermined pixel of the first region is provided. The supplied storage capacitor wiring signal is level-shifted more than a predetermined period before the scanning timing of the predetermined pixel defined based on the actual scanning start timing in the first region, and the same level is maintained until the scanning timing. It can also be set as the structure reset so that.

  In the present liquid crystal display device, the predetermined pixel may be a pixel arranged other than the scanning upstream edge portion of the first region.

  In the present liquid crystal display device, the difference between the actual scan start timing in the first area and the scan start timing in the second area may be equal to the scan period of the first area.

  In the present liquid crystal display device, the predetermined period may be set based on the charging characteristics of the storage capacitor wiring.

  In the present liquid crystal display device, a plurality of subpixels provided in one pixel may be connected to the same data signal line.

  In the present liquid crystal display device, the actual scanning start timing in the first region may be based on the vertical synchronization signal of the current frame.

  In the present liquid crystal display device, the actual scanning start timing in the first region may be based on the data enable signal of the current frame.

  In the present liquid crystal display device, when the extending direction of the data signal line is the vertical direction, if the scanning direction is from the top to the bottom, the first region is located on the upper side of the display unit and the second region is located on the lower side of the display unit. If the scanning direction is from bottom to top, the first area is located on the lower side of the display unit, and the second area is located on the upper side of the display unit.

  In the driving device of the present liquid crystal display device, a data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display portion, and a plurality of sub-pixels provided in one pixel are formed. Each pixel is connected to the same scanning signal line and forms a different storage capacitor line and capacitance, and a part of the current frame is written to the first area by scanning in the first area of the current frame, and A driving device for a liquid crystal display device used in a liquid crystal display device in which the remaining portion of the current frame is written in the second region by scanning in the second region of the frame, wherein each holding capacitor wiring is leveled by a periodic level shift In the scan in the second area of the current frame, which is performed after the storage capacitor wiring signal is exchanged and the scan in the first area of the current frame is started, the scan timing of the pixels in the second area Is determined according to the actual scanning start timing in the first region, and the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming a capacitor with the pixel in the second region is supplied to the pixel in the second region. The level shift is performed a predetermined period or more before the prescribed scanning timing, and the level is set so as to be maintained until the scanning timing.

  In the driving method of the present liquid crystal display device, a data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display portion, and a plurality of sub-pixels provided in one pixel are formed. Each pixel is connected to the same scanning signal line and forms a different storage capacitor line and capacitance, and a part of the current frame is written to the first area by scanning in the first area of the current frame, and A driving method of a liquid crystal display device for driving a liquid crystal display device in which the remaining portion of the current frame is written in the second region by scanning in the second region of the frame, wherein a periodic level shift is applied to each storage capacitor line In the scanning in the second region of the current frame, which is performed after the storage capacitor wiring signal whose level is switched by the first and second scannings in the first region of the current frame is started. The storage capacitor wiring signal that is supplied to each of the plurality of storage capacitor wirings that form capacitance with the pixels in the second region is defined according to the actual scanning start timing in the first region. The level shift is performed for a predetermined period or more before the prescribed scanning timing, and the level is set so as to be maintained until the scanning timing.

  The present television receiver includes the above-described liquid crystal display device and a tuner unit that receives a television broadcast.

  As described above, according to the present invention, in the liquid crystal display device that combines the screen division method and the pixel division method (Cs swing type), it is possible to reduce display noise at the center of the screen.

  An embodiment according to the present invention will be described with reference to FIGS.

  FIG. 16A is a block diagram showing a configuration of the present television receiver. As shown in the figure, the present television receiver 50 includes a tuner 40 and a liquid crystal display device 10. The liquid crystal display device 10 includes a liquid crystal panel 3 divided into first and second regions, a first display control circuit 20x, a first source driver SDx, a first gate driver GDx, a first Cs (holding capacity wiring) control circuit 30x, A second display control circuit 20y, a second source driver SDy, a second gate driver GDy, and a second Cs control circuit 30y are provided. The first display control circuit 20x, the first source driver SDx, the first gate driver GDx, and the first Cs control circuit 30x are for driving the first region, and the second display control circuit 20y, the second source driver SDy, The second gate driver GDy and the second Cs control circuit 30y are for driving the second region.

  The first display control circuit 20x receives from the tuner 40 a vertical synchronization signal VSYNC (x), a horizontal synchronization signal HSYNC (x), a data enable signal DE (x), video data DAT (x), and a 1-dot period clock signal. CLK (x) is inputted, and the vertical synchronization signal VSYNC (y), horizontal synchronization signal HSYNC (y), data enable signal DE (y), and video data DAT (y) are inputted from the tuner 40 to the second display control circuit 20y. ) And a 1-dot period clock signal CLK (y). The first display control circuit 20x outputs a gate start pulse GSP (x) for the first region to the first gate driver GDx, and outputs a Cs control signal for the first region to the first Cs control circuit 30x. The second display control circuit 20y outputs a gate start pulse GSP (y) for the second region to the second gate driver GDy, and outputs a Cs control signal for the second region to the second Cs control circuit 30y. Further, the first Cs control circuit 30x supplies a Cs signal to each storage capacitor line in the first region, and the second Cs control circuit 30y supplies a Cs signal to each storage capacitor wire in the second region.

  In the present liquid crystal display device 10, as shown in FIGS. 16A and 2B, the first half Ax of the first frame A is written in the first area, and then the second half Ay of the first frame A is changed to the first. The first half Bx of the second frame B is written to the first area so that it overlaps the writing period of the second half Ay of the frame A in time, and then the second half By of the second frame B is written. Is written in the second area. Then, the first half Cx of the third frame C is written to the first area so as to overlap with the writing period of the second half By of this frame B, and then the second half Cy of the third frame C is written to the second area. Write to. 2A shows the input timing of the frames A to D. In FIG. 2, the vertical synchronizing signals of the frames A to D are VSA to VSD, and the periods (VtA to Vt of each of the frames A to D are shown. VtD) is equally 1120 lines (of which the blanking period is 40 lines).

  In FIG. 2B, the gate start pulse of the first half frame Ax is GSAx, the gate start pulse of the first half frame bx is GSBx, the gate start pulse of the first half frame Cx is GSCx, and the gate start pulse of the first half frame Dx is GSDx. The gate start pulse GSAx of the frame Ax and the vertical synchronization signal VSA of the frame A are synchronized, the gate start pulse GSBx of the first half frame Bx and the vertical synchronization signal VSB of the frame B are synchronized, and the gate start pulse GSCx of the first half frame Cx The vertical synchronization signal VSC of frame C is synchronized, and the gate start pulse GSDx of the first half frame Dx and the vertical synchronization signal VSD of frame D are synchronized. In addition, the periods (VtAx to VtDx) of the first half frames Ax to Dx are equally set to 560 lines (of which the blanking period is 20 lines).

  In FIG. 2B, the gate start pulse of the second half frame Ay is GSAy, the gate start pulse of the second half frame By is GSBy, the gate start pulse of the second half frame Cy is GSCy, and the gate start pulse of the second half frame Dy is GSDy. The gate start pulse GSAy of the second half frame Ay becomes active because the gate start pulse GSBy of the second half frame By becomes active after W (540 line period) from the gate start pulse GSAx of the first half frame Ax. After the period W has elapsed from the gate start pulse GSBx of the frame Bx, the gate start pulse GSCy of the second half frame Cy becomes active after the period W has elapsed from the gate start pulse GSCx of the first half frame Cx. The gate start pulse GSDy is active, and has a post-period W elapsed since the gate start pulse GSDx of the first half frame Dx. Further, the respective periods (VtAy to VtDy) of the latter half frames Ay to Dy are equally set to 560 lines (of which the blanking period is 20 lines).

  As shown in FIGS. 2A and 2B, in the present liquid crystal display device 10 of the screen division type, for example, it is only necessary to output (scan) 540 lines during an input period of 1080 lines, and 1H on the output side. (One horizontal scanning period) can be doubled by 1H (one horizontal scanning period) on the input side, and the charging rate of each pixel can be increased.

  13 to 15 are schematic views showing specific configurations of the respective regions of the liquid crystal panel 3. As shown in FIG. 13, scanning signal lines G1 to G540 and storage capacitor lines Cs1 to Cs541 are provided in the first region, and scanning signal lines G541 to G1080 and storage capacitor wires Cs542 to Cs1082 are provided in the second region. Is provided.

  In the first region, as shown in FIGS. 14A and 14B, two subpixels arranged in the column direction (data signal line direction) are provided in one pixel, and these subpixels are provided with separate storage capacitor lines. And form a storage capacitor. That is, if an i-th pixel (i is an integer of 1 to 540) in an arbitrary pixel column is defined as a pixel Pi, the pixel Pi includes two sub-pixels Spai, connected to the scanning signal line Gi and the data signal line Sl. The pixel electrode in the sub-pixel Spai forms a storage capacitor line Csi and a storage capacitor, and the pixel electrode in the sub-pixel Spbi forms a storage capacitor line Cs (i + 1) and a storage capacitor. Note that the storage capacitor line Cs (i + 1) also forms a storage capacitor with the pixel electrode in the sub-pixel Spa (i + 1) included in the pixel P (i + 1), and each storage capacitor line has two adjacent pixel rows (rows). The direction is shared by the scanning signal line extending direction). For example, the pixel P1 connected to the scanning signal line G1 and the data signal line Sl has two subpixels Spa1 and Spb1, and the pixel electrode in the subpixel Spa1 forms a storage capacitor with the storage capacitor line Cs1. The pixel electrode in the subpixel Spb1 forms a storage capacitor line Cs2 and a storage capacitor. Note that the storage capacitor line Cs2 also forms a storage capacitor with the pixel electrode in the sub-pixel Spa2 included in the pixel P2.

  Also in the second region, as shown in FIGS. 15A and 15B, two subpixels arranged in the column direction (data signal line direction) are provided in one pixel, and these subpixels are provided with separate storage capacitor wirings. And form a storage capacitor. That is, if the j-th pixel (j is an integer from 541 to 1080) in the arbitrary pixel column is defined as a pixel Pj, the pixel Pj includes two subpixels Spaj, which are connected to the scanning signal line Gj and the data signal line SL. The pixel electrode in the sub-pixel Spaj forms a storage capacitor line Cs (j + 1) and a storage capacitor, and the pixel electrode in the sub-pixel Spbj forms a storage capacitor line and a storage capacitor line Cs (j + 2). . Note that the storage capacitor line Cs (j + 2) also forms a storage capacitor with the pixel electrode in the sub-pixel Spa (j + 1) included in the pixel P (j + 1), and each storage capacitor line is shared by two adjacent pixel rows. Has been. For example, the pixel P541 connected to the scanning signal line G541 and the data signal line SL has two subpixels Spa541 and Spb541, and the pixel electrode in the subpixel Spa541 forms a storage capacitor and a storage capacitor Cs542. The pixel electrode in the subpixel Spb 541 forms a storage capacitor line Cs 543 and a storage capacitor. Note that the storage capacitor wiring Cs 543 also forms a storage capacitor with the pixel electrode in the sub-pixel Spa 542 included in the pixel P542.

  FIGS. 3 and 4 show the input vertical synchronization signal VSYNC, video data DAT, gate start pulse (GSP) supplied to the first and second gate drivers GDx and GDy, and the scanning signal lines of the first and second regions. 6 is a timing chart showing a gate-on pulse supplied to, and a Cs signal (Scs) supplied to each storage capacitor wiring in the first and second regions.

  As shown in FIGS. 3 and 4, the Cs signal (retention capacitor line signal) supplied to each retention capacitor line is alternately “H (High)” and “L (Low)” by a periodic level shift. The basic period (pulse width) of the level shift is 12H (1H is one horizontal scanning period on the output side).

  In the first region, as shown in FIGS. 14A and 14B and FIGS. 3 and 4, the Cs signal Scsi and the storage capacitor line Cs (i) supplied to the storage capacitor line Csi [i is an integer of 1 to 540]. The Cs signal Scs (i + 1) supplied to i + 1) is level-shifted in the opposite direction (push-up / down direction) after the scanning of the scanning signal line Gi. Thus, one potential of the two sub-pixels (Spai / Spbi) can be swung up with respect to the writing potential from the data signal line Sl, and the other potential can be swung down with respect to the writing potential. The pixels Spai and Spbi can be controlled to have different luminances. For example, the Cs signal Scs1 supplied to the storage capacitor line Cs1 is level-shifted (pushed up) from “L” to “H” after the scanning of the scanning signal line G1 is completed, while the Cs signal Scs2 supplied to the storage capacitor line Cs2 Shifts (lowers) the level from “H” to “L” after the scanning of the scanning signal line G1 is completed. As a result, the potential of the subpixel Spa1 can be swung up with respect to the writing potential from the data signal line S1, and the potential of the subpixel Spb1 can be swung down with respect to the writing potential. For example, the subpixels Spa1 and Spb1 can be a bright subpixel and a dark subpixel, respectively.

  Similarly, in the second region, as shown in FIGS. 15A and 15B and FIGS. 3 and 4, the Cs signal Scs supplied to the storage capacitor wiring Cs (j + 1) [j is an integer of 541 to 1080]. The Cs signal Scs (j + 2) supplied to (j + 1) and the storage capacitor line Cs (j + 2) is level-shifted in the opposite direction (push-up / down direction) after the scanning of the scanning signal line Gj. Thus, one potential of the two subpixels (Spaj · Spbj) can be swung up with respect to the writing potential from the data signal line SL, and the other potential can be swung down with respect to the writing potential. The pixels Spaj and Spbj can be controlled to have different luminances. For example, the Cs signal Scs 542 supplied to the storage capacitor line Cs 542 is level-shifted (pushed up) from “L” to “H” after the scanning of the scanning signal line G 541 is completed, while the Cs signal Scs 543 supplied to the storage capacitor line Cs 543. Shifts (lowers) the level from “H” to “L” after the scanning of the scanning signal line G541 is completed. Accordingly, the potential of the sub-pixel Spa 541 can be swung up with respect to the writing potential from the data signal line SL, and the potential of the sub-pixel Spb 541 can be swung down with respect to the writing potential. For example, the subpixels Spa541 and Spb541 can be a bright subpixel and a dark subpixel, respectively.

  In this liquid crystal display device, the Cs signal is set as follows in order to control each subpixel within one pixel to the expected brightness even if the potential waveform of the storage capacitor wiring is somewhat dull.

  That is, for the first region, as shown in FIG. 4, the Cs signal Scsi [i is an integer of 1 to 540] and the Cs signal Scs (i + 1) are more predetermined than the scanning of the scanning signal line Gi (pixel Pi). The level is shifted before a period (for example, 9H) or more to maintain the same level until the scanning, and the level is shifted after the scanning. For example, the Cs signal Scs1 is shifted from “L” 10H before scanning of the scanning signal line G1, so that the Cs signal Scs1 is level-shifted from “H” to “L” 10H before scanning of the scanning signal line G1. The level is set to “H”.

  However, in order to level-shift the Cs signal scs1 and the Cs signal scs2 10H before the scanning of the scanning signal line G1, the scanning timing of the scanning signal line G1, that is, the scanning start timing (Cx in the first region of the current frame C). It is necessary to predict the scanning start timing). Therefore, as shown in FIGS. 2C and 4, assuming that VtBx = VtAx, predictive scan start timing (predictive scan start timing of Cx) TCxu in the first region is set to the previous frame. It is after VtAx has elapsed from the gate start pulse GSBx (synchronized with the vertical synchronization signal VSB of frame B) in the first half Bx of B. That is, the Cs signal Scs1 is level-shifted from “H” to “L” 10H before the timing TCxu, and the Cs signal Scs2 is level-shifted from “L” to “H” 10H before the timing TCxu. Is set. The odd-numbered Cs signals after the Cs signal Scs1 are level-shifted from “L” to “H” with a delay of 2H, and the even-numbered Cs signals after the Cs signal Scs2 are delayed by 2H with a delay of “H” to “L”. "Is set to level shift.

  On the other hand, for the second region, as shown in FIG. 4, the Cs signal Scs (j + 1) [j is an integer of 541 to 1080] and the Cs signal Scs (j + 2) given to the second region are the scanning signal lines Gj. It is set so that the level is shifted a predetermined period (for example, 9H) or more before the scanning of (pixel Pj), the same level is maintained until the scanning timing, and the level is shifted after this scanning. For example, the Cs signal Scs 542 is level-shifted from “H” to “L” 10 H before scanning of the scanning signal line G 541, and the Cs signal Scs 543 is switched from “L” 10 H before scanning of the scanning signal line G 541. The level is set to “H”.

  Specifically, as shown in FIGS. 2B and 4, the scanning timing of the scanning signal line G541 is after w (540 line period) has elapsed from the scanning start timing in the first region of the current frame C. Focusing on the fact that it is defined by the timing TCyk, the Cs signal Scs 542 is changed from “H” at a timing after 529 (= 540-11) line period from GSCx (scanning start timing in the first region of the current frame C). The level is shifted to “L”, and the Cs signal Scs 543 is set to “L” at a timing after the 529 (= 540-11) line period has elapsed from GSCx (scanning start timing in the first region of the current frame C). It is set to shift the level from “H” to “H”. The even-numbered Cs signals after the Cs signal Scs542 are level-shifted from “H” to “L” with a delay of 2H, and the odd-numbered Cs signals after the Cs signal Scs543 are delayed by “2H” from “L” to “H”. "Is set to level shift.

  1A to 1C and FIGS. 5 and 6, when a change in frame period (number of frame lines) occurs in the present liquid crystal display device, for example, as shown in FIG. A case where the period VtA of the frame A is 1120, the period VtB of the frame B is 1110, VtAx = VtAy = 560, VtBx = VtBy = 555, and VtCx = VtCy = 555 will be described.

  In this case, in the first region, as shown in FIGS. 1B and 1C and FIG. 5, the actual scanning start timing in the first region of the current frame C is 5 than the predictive scanning start timing TCxu. It will be accelerated by the line period. Therefore, in FIG. 5, the Cs signals (Scs1 to Scs541) are reset at the timing of GSCx. Specifically, as shown in FIG. 6, the Cs signals Scs1, 3, 5, 7, 9, and 11 are simultaneously reset to “L” at the timing of GSCx (if the timing is “L”) As is, the level is shifted 2H after GSCx, 4H after GSCx, 6H after GSCx, 8H after GSCx, 10H after GSCx, and 12H after GSCx, and the odd number Cs signals after Cs signal Scs11 are 2H. The level is shifted from “H” to “L” with a delay. The Cs signals Scs2, 4, 6, 8, 10, and 12 are simultaneously reset at the timing of GSCx to be “H” (if it is “H” at that timing), respectively, and after 2H of GSCx, After 4H of GSCx, 6H of GSCx, 8H of GSCx, 10H of GSCx, and 12H of GSCx, the even-numbered Cs signal after Cs signal Scs12 is delayed by 2H from “L” to “H”. Is set to level shift.

  In this way, the Cs signal Scsi [i is an integer of 1 to 9] and the Cs signal Scs (i + 1) are level-shifted by a predetermined period (for example, 9H) or more before the scanning of the scanning signal line Gi (pixel Pi). However, for the Cs signal Scsi (i is an integer of 10 to 540) and the Cs signal Scs (i + 1), the scanning signal line Gi ( It is possible to set so that the level is shifted a predetermined period (for example, 9H) or more before the scanning of the pixel Pi), the same level is maintained until the scanning, and the level is shifted after this scanning. Note that display noise at the upstream edge (upper edge of the screen) of the first region does not significantly affect the display quality.

  On the other hand, in the second area, as shown in FIGS. 1B and 1C and FIG. 5, the Cs signals Scs542 and Scs543 are changed from GSCx (scanning start timing in the first area of the current frame C) to 530 (= 540-10) Since the level shift is set at the timing after the lapse of the line period, unlike the case of FIG. 21C, it is not affected by the fluctuation of the frame period. That is, the Cs signals Scs 542 and Scs 543 are level-shifted 10H before scanning of the scanning signal line G541.

  Thus, in the present liquid crystal display device, the Cs signal Scs (j + 1) [j is an integer of 541 to 1080] and the Cs signal Scs (j + 2) are (j−10) from the scanning start timing in the first region of the current frame C. ) To (j-12) The level shift is set after the line period. Therefore, even if the frame period (the number of frame lines) varies, the Cs signal Scs (j + 1) [j is an integer of 541 to 1080] and the Cs signal Scs (j + 2) are obtained by scanning the scanning signal line Gj (pixel Pj). Also, the level is shifted 9 to 11H before, and the same level is maintained until the scanning, and the level is shifted after this scanning. That is, the storage capacitor line Cs (j + 1) [j is an integer of 541 to 1080, j = 541 to 549] and the storage capacitor line Cs (j + 2) are sufficiently charged until the scanning signal line Gj (pixel Pj) is scanned. The In particular, since the storage capacitor line Cs (j + 1) [j = 541 to 548] and the storage capacitor line Cs (j + 2) are sufficiently charged until the scanning signal line Gj (pixel Pj) is scanned, the upstream side of the second region. Display noise at the edge (center of the screen) is eliminated, and display quality is improved.

  Here, as shown in FIG. 16A, the first display control circuit 20x receives the vertical synchronization signal VSC of the frame C, and transmits the scan start notification signal SSAP to the second display control circuit 20y, which (SSAP) The second display control circuit 20y that receives the signal generates a gate start pulse GSP (y) (for example, GSCy) by appropriately calculating a necessary period, and also sends a Cs control signal for the second region to the second Cs control circuit 30y. Is output. By this Cs control signal, the Cs signal Scs (j + 1) [j is an integer of 541 to 1080] and the Cs signal Scs (j + 2) are (j-10) to (j-10) to (j-10) to (j) from the scanning start timing in the first region of the current frame C. j-12) The level is shifted after the line period to maintain the same level until the scanning of the scanning signal line Gj (pixel Pj), and the level is shifted after this scanning.

  As shown in FIG. 16B, the second display control circuit 20y has a counter circuit 18 to which the output side 1H cycle clock CLK (1H) and the scan start notification signal SSAP are input. The gate start pulse GSP (y) (for example, GSCy) and the Cs control signal may be generated from the output Cout of the counter circuit 18.

  1 to 5, the last scan of the first region (scan of the scanning signal line G540) and the first scan of the second region (scan of the scanning signal line G541) for the same frame are separated by 1H. It is not limited. For example, as shown in FIGS. 7 and 8, the last scan of the first area and the first scan of the second area for the same frame may be synchronized. 7 shows the case of FIG. 2 (when there is no line number variation), and FIG. 8 shows the case of FIG. 1 (when there is a line number variation). 7 and 8, since the scanning timing of the scanning signal line G541 is defined as the timing TCyk after the 539 (W) line period has elapsed from the scanning start timing in the first region of the current frame C, the Cs signal Scs542 is The level is shifted from “H” to “L” at the timing after 529 (= 539−10) line period from GSCx (scanning start timing in the first area of the current frame C), and the Cs signal Scs543 is set. , GSCx (scanning start timing in the first area of the current frame C) is set so that the level shifts from “L” to “H” at the timing after the passage of the 529 (= 539-10) line period. The even-numbered Cs signals after the Cs signal Scs542 are level-shifted from “H” to “L” with a delay of 2H, and the odd-numbered Cs signals after the Cs signal Scs543 are delayed by “2H” from “L” to “H”. "Is set to level shift.

  Also, as shown in FIGS. 9 and 10, the last scan of the first area and the first scan of the second area for the same frame may be separated by 2H. FIG. 9 shows the case of FIG. 2 (when there is no line number variation), and FIG. 10 shows the case of FIG. 1 (when there is a line number variation). 9 and 10, since the scanning timing of the scanning signal line G541 is defined as the timing TCyk after the 541 (W) line period has elapsed from the scanning start timing in the first region of the current frame C, the Cs signal Scs542 is The level is shifted from “H” to “L” at the timing after 531 (= 541-10) line period from GSCx (scanning start timing in the first region of the current frame C), and the Cs signal Scs543 is set. , GSCx (scanning start timing in the first region of the current frame C) is set so as to shift the level from “L” to “H” at the timing after the elapse of the 531 (= 541-10) line period. The even-numbered Cs signals after the Cs signal Scs542 are level-shifted from “H” to “L” with a delay of 2H, and the odd-numbered Cs signals after the Cs signal Scs543 are delayed by “2H” from “L” to “H”. "Is set to level shift.

  FIG. 13 shows a configuration in which the pixel P540 at the end of the first region and the pixel P541 at the end of the second region do not share the storage capacitor wiring, but the present invention is not limited to this. For example, as shown in FIG. 17, the pixel P540 connected to the scanning signal line G540 and the pixel P541 connected to the scanning signal line G541 share the storage capacitor line Cs541 provided in the first or second region. A configuration in which one subpixel of the pixel P540 forms a storage capacitor and a storage capacitor, and the storage capacitor wiring Cs541 forms a storage capacitor and one subpixel of the pixel P541 may be used.

  In the configuration of FIG. 17, when the scanning of the scanning signal line G540 and the scanning of the scanning signal line G541 are separated by 1H, the Cs signal (Scs541) and the subsequent Cs signal to the storage capacitor wiring Cs541 are as shown in FIGS. Set to 18 shows the case of FIG. 2 (when there is no line number variation), and FIG. 19 shows the case of FIG. 1 (when there is a line number variation). In FIGS. 18 and 19, since the scanning timing of the scanning signal line G541 is defined as the timing TCyk after the 540 (W) line period has elapsed from the scanning start timing in the first region of the current frame C, the Cs signal Scs541 is The level changes from “H” to “L” at a timing after 530 (= 540−10) line period has elapsed from GSCx (scanning start timing in the first region of the current frame C) (9H before scanning of the scanning signal line G540). The Cs signal Scs 542 is set to shift from “L” to “H” at a timing after 530 (= 540−10) line period from GSCx (scanning start timing in the first region of the current frame C). It is set to level shift. The odd numbered Cs signal after the Cs signal Scs541 is level-shifted from “H” to “L” by 2H, and the even numbered Cs signal after the Cs signal Scs542 is delayed by “2H” from “L” to “H”. "Is set to level shift.

  In the configuration of FIG. 17, when the scanning of the scanning signal line G540 and the scanning of the scanning signal line G541 are synchronized, the Cs signal (Scs541) and the subsequent Cs signal to the storage capacitor wiring Cs541 are shown in FIGS. It is set like this. 20 shows the case of FIG. 2 (when there is no line number variation), and FIG. 21 shows the case of FIG. 1 (when there is a line number variation). 20 and 21, since the scanning timing of the scanning signal line G541 is defined as the timing TCyk after the 539 (W) line period has elapsed from the scanning start timing in the first region of the current frame C, the Cs signal Scs541 is The level changes from “H” to “L” at a timing after 530 (= 539-9) line period has elapsed from GSCx (scanning start timing in the first region of the current frame C) (9H before scanning of the scanning signal line G540). The Cs signal Scs 542 is changed from “L” to “H” at a timing after 529 (= 539−10) line period from GSCx (scanning start timing in the first region of the current frame C). Level shift is set, and the Cs signal Scs543 is changed from “H” to “L” at the timing after the 531 line period from GSCx. It is set so as to Rushifuto. The even-numbered Cs signal after the Cs signal Scs542 is level-shifted from “L” to “H” by 2H, and the odd-numbered Cs signal after the Cs signal Scs543 is delayed by “2H” from “H” to “L”. "Is set to level shift.

  In the configuration of FIG. 17, when the scanning of the scanning signal line G540 and the scanning of the scanning signal line G541 are separated by 2H, the Cs signal (Scs541) and the subsequent Cs signal to the storage capacitor wiring Cs541 are shown in FIGS. It is set like this. 22 shows the case of FIG. 2 (when there is no line number variation), and FIG. 23 shows the case of FIG. 1 (when there is a line number variation). 22 and 23, since the scanning timing of the scanning signal line G541 is defined as the timing TCyk after the 541 (W) line period has elapsed from the scanning start timing in the first region of the current frame C, the Cs signal Scs541 is The level changes from “H” to “L” at the timing after 530 (= 541-11) line period has elapsed from GSCx (scanning start timing in the first region of the current frame C) (9H before scanning of the scanning signal line G540). The Cs signal Scs 542 is changed from “L” to “H” at the timing after the passage of the 531 (= 541-10) line period from GSCx (scanning start timing in the first region of the current frame C). The level is set to shift, and the Cs signal Scs543 is changed from “H” at the timing after the 533 line period has elapsed from the start of the GSCx scan. It is set so as to level shift to L ". The even-numbered Cs signal after the Cs signal Scs542 is level-shifted from “L” to “H” by 2H, and the odd-numbered Cs signal after the Cs signal Scs543 is delayed by “2H” from “H” to “L”. "Is set to level shift.

  In the above description, the gate start pulses GSAx, GSBx, GSCx, GSDx, GSAy, GSBy, GSCy, and GSDy are generated based on the vertical synchronization signals VSA to VSD, but are not limited thereto. For example, as shown in FIGS. 11 and 12, the gate start pulses GSAx, GSBx, GSCx, GSDx, GSAy, GSBy, GSCy, and GSDy may be generated based on the data enable signal DE.

  In the above description, the gate start pulses GSAx, GSBx, GSCx, and GSDx are synchronized with the vertical synchronization signal VSYNC and the data enable signal DE, but the present invention is not limited to this. As long as the gate start pulses GSAx, GSBx, GSCx, and GSDx are generated based on the vertical synchronization signal VSYNC and the data enable signal DE, they may not be synchronized with these.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The display device of the present invention is particularly suitable for a liquid crystal display device (for example, a liquid crystal television).

(A)-(c) is a schematic diagram which shows the drive method of this liquid crystal display device. (A)-(c) is a schematic diagram which shows the drive method of this liquid crystal display device. It is a timing chart which shows the drive method (in the case of no fluctuation | variation of a frame period) of this liquid crystal display device. It is a timing chart which shows the drive method (in the case of no fluctuation | variation of a frame period) of this liquid crystal display device. 4 is a timing chart showing a driving method of the present liquid crystal display device (in the case where there is a change in frame period). 4 is a timing chart showing a driving method of the present liquid crystal display device (in the case where there is a change in frame period). 12 is a timing chart showing another driving method of the present liquid crystal display device (when there is no change in frame period). It is a timing chart which shows the other drive method (when there exists a fluctuation | variation of a frame period) of this liquid crystal display device. 12 is a timing chart showing still another driving method of the present liquid crystal display device (in the case where there is no change in the frame period). 14 is a timing chart showing still another driving method of the present liquid crystal display device (when there is a change in the frame period). It is a schematic diagram which shows the other drive method of this liquid crystal display device. It is a schematic diagram which shows the other drive method of this liquid crystal display device. It is a schematic diagram which shows the structure of the display part (1st * 2nd area | region) of this liquid crystal display device. (A) (b) is a schematic diagram which shows the structure of a 1st area | region. (A) (b) is a schematic diagram which shows the structure of a 2nd area | region. (A) is a block diagram showing a configuration of the present liquid crystal display device, and (b) is a block diagram showing a configuration of a second display control circuit. It is a schematic diagram which shows the structure of the other display part (1st * 2nd area | region) of this liquid crystal display device. 12 is a timing chart showing another driving method of the present liquid crystal display device (when there is no change in frame period). It is a timing chart which shows the other drive method (when there exists a fluctuation | variation of a frame period) of this liquid crystal display device. 12 is a timing chart showing still another driving method of the present liquid crystal display device (in the case where there is no change in the frame period). 14 is a timing chart showing still another driving method of the present liquid crystal display device (when there is a change in the frame period). 12 is a timing chart showing still another driving method of the present liquid crystal display device (in the case where there is no change in the frame period). 14 is a timing chart showing still another driving method of the present liquid crystal display device (when there is a change in the frame period). It is a schematic diagram which shows the structure of the display part (1st * 2nd area | region) of a common liquid crystal display device. It is a schematic diagram which shows the structure of the 1st area | region of FIG. It is a schematic diagram which shows the structure of the 2nd area | region of FIG. (A)-(c) is a schematic diagram which shows the drive method of the conventional liquid crystal display device. (A)-(c) is a schematic diagram which shows the drive method of the conventional liquid crystal display device. It is a timing chart which shows the drive method (when there is no change of a frame period) of the conventional liquid crystal display device. It is a timing chart which shows the drive method (when there is no change of a frame period) of the conventional liquid crystal display device. It is a timing chart which shows the drive method (when there exists a fluctuation | variation of a frame period) of the conventional liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 Liquid crystal panel 10 Liquid crystal display device 20x 1st display control circuit 20y 2nd display control circuit 50 Television receiver GDx 1st gate driver GDy 2nd gate driver GSP Gate start pulse VSYNC Vertical synchronizing signal Cs1-1082 Retention capacity wiring Scs1 1082 Retention capacitance wiring signal G1 to 1080 Scanning signal line P1 to P1080 Pixel Spa1 to Spa1080 Subpixel Spb1 to Spb1080 Subpixel

Claims (16)

A data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display portion, and one of the current frame is placed in the first region by scanning in the first region of the current frame. A liquid crystal display device in which a portion is written and the remainder of the current frame is written to the second region by scanning in the second region of the current frame,
A plurality of sub-pixels provided in one pixel are connected to the same scanning signal line and form different storage capacitor lines and capacitors, and the levels of the storage capacitor lines are switched by a periodic level shift. Retention capacitance wiring signal is supplied,
In scanning in the second area of the current frame performed after the start of scanning in the first area of the current frame, the scanning timing of the pixels in the second area is defined according to the actual scanning start timing in the first area. The storage capacitor line signal supplied to each of the plurality of storage capacitor lines forming a capacitor with the pixels in the second region is level-shifted by a predetermined period or more before the scanning timing defined for the pixels in the second region. The liquid crystal display device is set to maintain the same level until the scanning timing.   The prescribed scanning timing of the pixels in the second region is a timing after a period corresponding to this pixel has elapsed from the start of actual scanning in the first region, and a plurality of pixels forming a capacitance with the pixels in the second region. The storage capacitor wiring signal supplied to each of the storage capacitor wirings is level-shifted by a certain period or more before the timing corresponding to the pixel after the actual scanning start in the first region, and the timing 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is set so as to maintain the same level.   The storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming a capacitor with the pixel in the second region is set based on a signal for notifying actual start of scanning in the first region. The liquid crystal display device according to claim 1.   The pixel in the second region forms a capacity with two storage capacitor lines, and the storage capacitor line signal supplied to each of the two storage capacitor lines is in the reverse direction after the prescribed scanning timing. 2. The liquid crystal display device according to claim 1, wherein the level shift is set.   The storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings that form the capacitance with the pixels in the first region is at the predictive scan start timing of the first region obtained from the frame period of the frame before the current frame. 2. The level shift based on a predetermined period before the predictive scanning timing of the pixels in the first region based on the predetermined timing is set, and the same level is maintained until the scanning timing. Liquid crystal display device.   When the predictive scanning start timing of the first area is different from the actual scanning start timing, the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming a capacitor with a predetermined pixel in the first region Is level-shifted more than a predetermined period before the scanning timing of the predetermined pixel defined based on the actual scanning start timing in the first region, and is reset so as to maintain the same level until the scanning timing. The liquid crystal display device according to claim 5.   The liquid crystal display device according to claim 6, wherein the predetermined pixel is a pixel arranged in a region other than the scanning upstream edge portion of the first region.   The difference between the actual scanning start timing in the first area and the scanning start timing in the second area is equal to the scanning period of the first area. Liquid crystal display device.   The liquid crystal display device according to claim 1, wherein the predetermined period is set based on a charging characteristic of the storage capacitor wiring.   The liquid crystal display device according to claim 1, wherein each of a plurality of subpixels provided in one pixel is connected to the same data signal line.   The liquid crystal display device according to claim 1, wherein the actual scanning start timing in the first region is based on a vertical synchronization signal of the current frame.   11. The liquid crystal display device according to claim 1, wherein the actual scanning start timing in the first region is based on a data enable signal of the current frame.   When the extending direction of the data signal line is the vertical direction, if the scanning direction is from the top to the bottom, the first area is located above the display unit, the second area is located below the display part, and the scanning direction is from bottom to top. If there is, the liquid crystal display device according to any one of claims 1 to 12, wherein the first region is located below the display unit and the second region is located above the display unit. A data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display portion, and each of the plurality of sub-pixels provided in one pixel has the same scanning signal line. And a different storage capacitor line and capacitance are formed, a part of the current frame is written in the first area by scanning in the first area of the current frame, and by scanning in the second area of the current frame A driving device for a liquid crystal display device used in a liquid crystal display device in which the remainder of the current frame is written in the second region,
In the scanning in the second area of the current frame performed after the scanning in the first area of the current frame is started by supplying a holding capacity wiring signal whose level is switched by a periodic level shift to each holding capacity wiring. The scanning timing of the pixels in the region is defined in accordance with the actual scanning start timing in the first region, and the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming the capacitance with the pixels in the second region, A driving device for a liquid crystal display device, wherein a level shift is performed a predetermined period or more before a prescribed scanning timing of pixels in the second region and the same level is maintained until the scanning timing. A data signal line, a scanning signal line, a pixel, and a storage capacitor line are formed in each of the first and second regions provided in the display portion, and each of the plurality of sub-pixels provided in one pixel has the same scanning signal line. And a different storage capacitor line and capacitance are formed, a part of the current frame is written in the first area by scanning in the first area of the current frame, and by scanning in the second area of the current frame A driving method of a liquid crystal display device for driving a liquid crystal display device in which the remainder of the current frame is written in the second region,
In the scanning in the second area of the current frame performed after the scanning in the first area of the current frame is started by supplying a holding capacity wiring signal whose level is switched by a periodic level shift to each holding capacity wiring. The scanning timing of the pixels in the region is defined in accordance with the actual scanning start timing in the first region, and the storage capacitor wiring signal supplied to each of the plurality of storage capacitor wirings forming the capacitance with the pixels in the second region, A driving method of a liquid crystal display device, characterized in that a level shift is performed a predetermined period or more before a prescribed scanning timing of pixels in the second region, and the same level is maintained until the scanning timing.   14. A television receiver comprising: the liquid crystal display device according to claim 1; and a tuner unit that receives a television broadcast.

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