JP2009181473A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be used as various type of memories and is capable of corresponding to the input of data having a data width of not more than the data width of the device, and to provide its operational method. <P>SOLUTION: The semiconductor memory device includes: a memory array part 3 with the memory array accessed by the predetermined data bus width formed; an interface part 2 for interfacing between an external device and the memory array part 3; and a converting part 31 having a converting function of the data and a control signal between the interface part and the memory array, and having the converting function corresponding to the specification of the memory array. The interface part 2 includes a plurality of interface modules respectively corresponding to a plurality of memory types, and selectively applied to the interface processing between the external device and the memory array 3, and the data bus width of the interface part is set to the data bus width wider than that set corresponding to the predetermined memory type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  As a semiconductor memory device used as a RAM chip in various electronic devices, various memory types are currently known with different circuit configurations and operation functions.

  In terms of circuit configuration and operation, DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) are known.

  In addition, SDRAM (Synchronous Dynamic Random Access Memory), which is a kind of DRAM and outputs data in synchronization with a clock supplied from the outside, includes SDR-SDRAM (Single Data Rate SDRAM), DDR-SDRAM (Double Data Rate). SDRAM), DDR2-SDRAM, DDR3-SDRAM... DDR (n) -SDRAM and the like are known.

  Further, there is a DPRAM (Dual Port RAM) having a plurality of access ports from a structural point of view, and a FIFO (First in First Out) type RAM that does not require addressing from a functional point of view.

  These various memory types are selectively used according to the necessity in the electronic device.

  In the following description, DR-SDRAM is "SDR", DDR-SDRAM is "DDR", DDR2-SDRAM is "DDR2", DDR3-SDRAM ... DDR (n) -SDRAM is "DDR3" -"DDR (n)" and the FIFO type will be called "FIFO".

JP 2006-65533 A JP 2004-318500 A

In various electronic devices, a memory type of a semiconductor memory device (semiconductor memory IC chip) to be mounted is determined in consideration of a required function, performance, cost, or the like.
When a semiconductor memory device of a certain memory type is mounted, the memory controller (memory control device) that writes (reads) / reads (reads) information on the memory chip naturally depends on the memory type. Designed or selected to perform a memory access operation.

However, the following problems often occur due to various circumstances.
Various semiconductor memory devices are not always stably supplied. Particularly in recent years, in accordance with technological innovations and market demands, the diversification of semiconductor memory devices has rapidly expanded, and new types of development have been actively conducted. Conversely, semiconductor memory devices of the type whose demand has declined are frequently discontinued by memory manufacturers.
For an equipment manufacturer that incorporates a certain type of semiconductor memory device into an electronic device to produce a product, discontinuing the manufacture of the memory type semiconductor memory device employed is a major problem.

For example, assume that a device manufacturer manufactures a device that employs SDR.
If the supply of SDR becomes unstable, a device manufacturer needs to consider installing a semiconductor memory device instead of SDR in the device.
Therefore, for example, DDR is installed instead of SDR. In this case, it is necessary not only to change the chip as the semiconductor memory device from SDR to DDR but also to change the specifications of the memory controller that accesses the semiconductor memory device.
In some cases, the memory controller and peripheral circuits have to be redesigned, which may cause a great burden in terms of manufacturing efficiency and cost.

Also, when designing new electronic devices, it is necessary to anticipate the future supply status of semiconductor memory devices.
However, it is necessary to adopt a semiconductor memory device with a higher processing capacity than necessary, or it is necessary to design the circuit in advance assuming a change in the specifications of the memory controller. May be hindered.

It is also conceivable to mount a plurality of memory interfaces corresponding to various memory types in a semiconductor memory device.
However, in this case, there is a disadvantage that it is not possible to cope with the case where data other than the data width of the semiconductor memory device 1 is input.

  It is an object of the present invention to provide a semiconductor memory device that can be used as a memory of various memory types and can cope with the case where data less than the data width of the device is input.

  A semiconductor memory device according to a first aspect of the present invention includes a memory array unit in which a memory array accessed with a predetermined data bus width is formed, and an interface unit that performs an interface between an external device and the memory array unit. A converter having a function of converting data and control signals between the interface unit and the memory array and having a conversion function according to the specifications of the memory array, and the interface unit has a plurality of memory types. And a plurality of interface modules that are selectively applied to interface processing between the external device and the memory array unit, and a data bus width in the interface unit is set according to a predetermined memory type The data bus width is set wider than the data bus width.

  Preferably, the converter obtains partition information of the memory array from a mode signal including interface type information, controls access to the memory array, and distinguishes data areas corresponding to different memory types in the memory array. .

  Preferably, the converter has a data width variable function that issues a command and an address of the memory array based on information of access data of the memory array, and outputs a variable or non-variable data width. .

  Preferably, the interface unit interprets a mode indicating the type of the memory from a mode designation signal, identifies at least a burst length and a bit width of data, and uses the identification result as access information of the memory array. As an output to the converter, and the converter issues a command and an address to the memory array based on the mode interpretation of the interpreter and the burst length and bit width information, and the data width is Variable or non-variable output.

  Preferably, the converter performs variable processing of the data width when the external data bus width and the data bus width of the memory array are different.

  Preferably, when the external data bus width is 2 to the Nth power and the converter receives a write command with a data mask, the converter issues the write command continuously, and the corresponding data is controlled by data mask control. Only to the memory array.

  Preferably, the converter issues a read command and a write command and receives an address designation from the memory array when a write command without a data mask is received when the external data bus width is 2 to the Nth power. The data is read out and written together with the read data and the data to be written.

  Preferably, the converter converts the data read from the memory array from parallel data to serial data when receiving a read command when the external data bus width is 2 to the Nth power. Output to the interface module corresponding to the type.

  Preferably, when the external data bus width is not 2 N, the converter replaces the non-N 2 data with the 2 N width when receiving a write command, and An address is issued based on length and bit width information and predetermined count information, and the corresponding data is written into the memory array.

  Preferably, the converter has a case where the external data bus width is not 2 to the Nth power, and when a write command is received, the converter converts the data that is not the 2nd power to the Nth power from parallel to serial for each bit from the input. A plurality of bits corresponding to predetermined data are converted and arranged in order and replaced with 2 N widths. An address is issued based on the burst length and bit width information and predetermined count information, and the corresponding data Are written into the memory array.

  Preferably, the converter has a case where the external data bus width is not 2 to the power of N, and when the read command is received, the read data of the memory array starts from data that is all contained in one block. The predetermined data block is extracted from the read data, converted from serial to parallel, and sequentially expanded. The next data is the first data because the data block for the predetermined data spans two blocks. Are stored together with the second data block, converted from serial to parallel, sequentially expanded and read.

  Preferably, the converter has a case where the external data bus width is not 2 to the power of N, and when a read command is received, the read data of the memory array is divided into two blocks corresponding to the predetermined data. In the case of spanning data, the first data is held, converted from serial to parallel together with the second data block, and sequentially expanded and read.

According to the present invention, it can be used as a memory of various memory types, and can cope with the case where data having a data width less than that of the apparatus is input.
By using a semiconductor memory device, it is possible to improve the efficiency of device manufacturing and design and to stabilize the manufacturing.
For example, in an electronic device equipped with a memory of a certain memory type, when the supply of the memory of that memory type becomes unstable, the memory is replaced with the semiconductor memory device of the present invention, and the same operation as the previous memory is performed. By executing the above, it is possible to continue manufacturing the device without changing the design of the memory control circuit and the peripheral circuit.
In addition, when designing a new electronic device, by adopting the semiconductor memory device of the present invention as a memory chip to be mounted, a highly flexible design and an efficient design are possible, and in the future the memory itself This makes it easy to deal with changes in specifications.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Hereinafter, embodiments of the present invention will be described in the following order.
[1. Outline of Semiconductor Memory Device]
[2. Internal Configuration and Operation of Semiconductor Memory Device]
[3. Mode operation of PLL section]
[4. Selector mode operation]
[5. IO buffer mode operation]
[6. Other Configuration Examples of Semiconductor Memory Device]

[1. Outline of Semiconductor Memory Device]
1A to 1C are explanatory views of a basic schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 1A shows a memory controller (MC) 100 as an external device and the semiconductor memory device 1 of the present embodiment.
The semiconductor memory device 1 is used as a memory IC in a certain electronic device, and is written (written) / readed (read) by a memory controller 100 mounted in the electronic device, and depending on a memory type. Further, it is accessed for erasing.

The memory controller 100 handles the semiconductor memory device 1 as a memory of a specific memory type according to the design specifications.
For example, in a certain electronic device, when the memory controller 100 is designed to perform an access process for DDR, the semiconductor memory device 1 of this example performs input / output similar to DDR to the memory controller 100. Do it. That is, after being mounted on the circuit of the electronic device and electrically connected to the memory controller 100, the semiconductor memory device 1 of this example functions as a DDR.
Further, in another electronic device, when the memory controller 100 is designed to perform access processing for SDR, the semiconductor memory device 1 of this example performs input / output similar to SDR to the memory controller 100. To do. That is, after being mounted on the circuit of the electronic device and electrically connected to the memory controller 100, the semiconductor memory device 1 of this example functions as an SDR.

For this reason, for example, in the case where an electronic device mounted with an SDR has been manufactured so far, even if the SDR supply is stopped at the SDR supplier, the present example is used instead of the SDR thereafter. By mounting the semiconductor memory device 1 and causing the semiconductor memory device 1 to operate as the SDR, it is possible to continue manufacturing the electronic device without changing the memory controller 100 or the like.
Further, if the semiconductor memory device 1 of the present example is adopted in a newly developed electronic device, the degree of freedom in designing the memory controller 100 and peripheral circuits is improved, and further necessity of changing the memory type arises in the future. However, it can be easily handled.

The semiconductor memory device 1 is a memory IC that is monolithically integrated into one package, and an interface (I / F) unit 2 and a memory array unit (RAM array unit) 3 are formed therein.
The memory array section 3 is formed as a DRAM or SRAM structure.
The interface unit 2 includes an input / output buffer for the memory controller 100, a plurality of interface modules corresponding to various memory types, and the like.
That is, in the semiconductor memory device 1 of this example, an interface unit 2 having a plurality of interface modules respectively corresponding to a plurality of memory types and a memory array unit 3 formed as an information storage area are enclosed in a package and integrated. It has become.

FIGS. 1B and 1C show structural examples in the package.
FIG. 1B shows an example in which the memory array section 3 and the interface section 2 are enclosed in a package in a state where they are formed on one silicon die 4.
On the other hand, FIG. 1C shows that the memory array unit 3 and the interface unit 2 are formed on individual silicon dies 4a and 4b, respectively, and the memory array unit 3 and the interface unit 2 are connected. An example enclosed in is shown.

[2. Specific Configuration and Operation of Semiconductor Memory Device]
FIG. 2 is a diagram illustrating a specific circuit configuration example of the semiconductor memory device 1.
As described above, the semiconductor memory device 1 is provided with the interface unit 2 and the memory array unit 3.
As shown in FIG. 2, the interface unit 2 includes an interface module (I / F) module group 21 (21-1, 21-2... 21-4) including a plurality of interface modules, an IO buffer 22, and a selector 23. , A PLL unit 24, and a mode interpretation unit 25.
The memory array unit 3 includes a RAM array 30 and an adaptive converter (ADPCVT) 31.

The RAM array 30 is formed as an information storage area using, for example, DRAM or SRAM. The RAM array 30 can be freely designed according to various circumstances, such as its cell structure.
The adaptive converter 31 performs control signal conversion between the RAM array 30 and each interface module of the interface module group.
The adaptive converter 31 performs signal conversion in accordance with the specifications of the RAM array 30, and is provided for realizing a general interface such as a DRAM or an SRAM.
The adaptive converter 31 according to the present embodiment is configured to be capable of supporting a plurality of data widths, as will be described in detail later, and even when data other than the data width of the semiconductor memory device 1 is input. Data can be efficiently stored in the RAM array 30 and can be read out.
The adaptive converter 31 has a function of issuing a command, an address issuance process, and variable or non-variable data based on the burst length and bit width information of the input data identified by the mode interpreter 25. Have.

In the interface unit 2, the IO buffer 22 performs an electrical interface between the semiconductor memory device 1 and an external device (for example, the memory controller 100).
The IO buffer 22 exchanges a command CMD, input / output data DQ, and data strobe signal DQS with the memory controller 100, for example.
The IO buffer 22 receives the system clock CLK supplied from the memory controller 100, for example, and supplies it to the PLL unit 24.
The IO buffer 22 receives the mode designation signal Md and supplies it to the mode interpretation unit 25.

The mode designation signal Md is a signal for instructing the operation mode of the semiconductor memory device 1 (different memory type to be operated).
The mode designation signal Md may be a signal having a logical value set by a small dip switch (DIP switch) formed on the package of the semiconductor memory device 1, for example.
Alternatively, a predetermined number of pins for mode setting may be formed in the package, and a logical value (for example, a logical value based on H / L / high impedance) according to the connection state of each pin may be used as the mode designation signal Md.
Further, the memory controller 100 may supply the mode specifying signal Md to the semiconductor memory device 1.

  The selector 23 selects one interface module from the interface module group 21 and connects it to the IO buffer 22. Selection by the selector 23 is based on the mode signal Smd from the mode interpretation unit 25.

As the interface module group 21, interface modules of different memory types are provided.
For example, in the example of FIG. 2, an interface module group 21, a DRAM-interface (IF) module group 21-1, an SRAM-IF module 21-2, a DPRAM-IF module 21-3, and a FIFO-IF module 21-4 are provided. It has been.

  FIG. 3 is a block diagram showing a configuration example of the DRAM-IF module group 21-1 according to the present embodiment.

The DRAM-IF module group 21-1 of the present embodiment converts a common part in each state transition of various DRAM-IF modules into a common sequence, and converts a part that performs different processing in each state transition into a dedicated module as an exception process. Configured.
Thereby, simplification of a state transition circuit of a so-called multi-interface RAM (multi-IF RAM) is realized.

  That is, the DRAM-IF module group 21-1 has a common sequence unit 210 and a dedicated module unit 211.

  The common sequence unit 210 detects a command from the memory controller 100 supplied via the I / O buffer 22 and the selector 23, and a common sequence of common parts according to the detection result of the command detection unit 2101 The common state transition unit 2102 that performs processing and causes the dedicated module unit 211 to perform exception processing, and a part that is a unique process in each memory I / F are separated from the common sequence unit and each DRAM-IF module that is configured as a dedicated module. A switch group 2103 for selectively delivering is provided.

  The dedicated module unit 211 is a variety of IF modules in which a part that performs different processing in each state transition in the common sequence unit 210 is made into an exclusive module, and is an SDR-IF module 211-0, a DDR-IF module 211- 1, DDR2-IF module 211-2,..., DDR (n) -IF module 211-n.

  In the DRAM-IF module group 21-1, the common state transition module 2102 which is the common sequence unit 210 is combined with the combination when the IF selector unit of the selector 23 selects the RAM mode according to the system control (system control) setting information Cmd. The IF module of the dedicated module unit 211 is determined and operates.

Each SDR-IF module 211-0, DDR-IF module 211-1, DDR2-IF module 211-2, ..., DDR (n) -IF module 211-n, SRAM-IF module 21-2, DPRAM- The IF module 21-3 and the FIFO-IF module 21-4 perform input / output at a timing required by the memory controller 100 so that the semiconductor memory device 1 operates as a memory of a corresponding memory type.
For example, the SDR-IF module 211-0 performs processing so that the write / read access operation for the RAM array 30 operates as an SDR when viewed from the external memory controller 100. The DDR-IF module 211-1 performs processing so that the write / read access operation for the RAM array 30 operates as DDR when viewed from the external memory controller 100.

  Here, the reason why the DRAM-IF module group 21-1 in the memory IF module group 21 is divided into the common sequence unit 210 and the dedicated module unit 211 as described above will be described with reference to FIGS.

  FIG. 4 is a state transition diagram of the SDRAM. FIG. 5 is a state transition diagram of the DDR-SDRAM. FIG. 6 is a diagram showing a configuration example of a semiconductor memory device provided with an IF module here without being divided into a common sequence section and a dedicated module section. FIG. 7 is a diagram showing state transition of a DRAM-IF module group provided with a common sequence part and a dedicated module part.

The existing memory, for example, SDRAM, has a state transition as shown in FIG. In this case, the state is changed by a combination of input command signals, and data writing (writing), reading (reading), precharging (Precharge), refreshing (Refresh), and the like are performed.
Similarly, in the case of a DDR-SDRAM, there is a state transition as shown in FIG.

As shown in FIG. 6, SDR-IF module 21a, DDR-IF module 21b, DDR2-IF module 21c, DDR3-IF module 21d,... DDR (n) -IF module 21e, SRAM-IF module 21f, DPRAM In the multi-IF RAM having the IF module 21g and the FIFO-IF module 21h in one package, each IF module performs processing by separate state transitions.
Therefore, it is necessary to have state transitions as many as the number of IF modules included in the multi-IF RAM, which may increase the circuit scale.
The semiconductor memory device 1A in FIG. 6 differs from the semiconductor memory device 1 in FIG. 3 only in the configuration of the interface module group 21, and the other configurations and functions have the configurations and functions described above and later.

Therefore, in the present embodiment, in the multi-IF RAM having a plurality of IF modules inside the IC, as shown in FIGS. 3, 4, and 7, common portions in each state transition are made into a common sequence, A part that performs different processing in each state transition is made into a dedicated module as exception processing.
Thereby, simplification of the state transition circuit of the multi-IF RAM is realized.

  An operation example in the common sequence unit and the dedicated module unit in the state transition diagram of FIG. 7 will be described in detail later.

The PLL unit 24, for example, based on the system clock CLK supplied from the memory controller 100, various SDR-IF modules 211-0, DDR-IF modules 211-1, and DDR2-IF modules 211-2 of the interface module group 21. ,... Generate various processing clocks CK to be used by the DDR (n) -IF module 211-n, the SRAM-IF module 21-2, the DPRAM-IF module 21-3, and the FIFO-IF module 21-4. To the interface module group 21.
The clock generation of the PLL unit 24 will be further described later.

The mode interpretation unit 25 interprets a logical value as the input mode designation signal Md and determines a mode required for the operation of the semiconductor memory device 1. A mode signal Smd indicating the mode is supplied to each unit.
The mode interpretation unit 25 identifies the burst length and bit width information of the input data included in the input mode designation signal and supplies the information to the adaptive converter 31 as the mode signal Smd.

In this semiconductor memory device 1, the IO buffer 22, the selector 23, the PLL unit 24, and the interface module group 21 perform necessary operations according to the mode signal Smd output from the mode interpretation unit 25, for example, an external memory controller Seen from 100, it functions as a memory of a specific memory type.
If the memory controller 100 and the semiconductor memory device 1 of this example are mounted on a circuit board of an electronic device as shown in FIG. 1A, the memory controller 100 performs memory control processing for DDR2. Is supposed to be performed.
In this case, a mode designation signal Md indicating a memory type mode called DDR2 is input to the mode interpreter 25 as a dip switch setting or a signal from the memory controller 100.

This case is shown in FIG. The mode interpreter 25 outputs a mode signal Smd indicating the DDR2 mode and syscon setting information Cmd.
As will be described later, the IO buffer 22 switches internal electrical characteristics, for example, power supply voltage and delay characteristics, to a state corresponding to DDR2 in accordance with the mode signal Smd.
The selector 23 is in a state of selecting the DDR2-IF module 211-2 corresponding to DDR2 in accordance with the mode signal Smd and the syscon setting information Cmd.
The PLL unit 24 generates a processing clock group for the DDR2-IF module 211-2 according to the mode signal Smd, and supplies the generated processing clock group to the DDR2-IF module 211-2.
Further, the PLL unit 24 stops supplying the processing clock to the other interface modules (211-0, 211-1, 211-n, 21-2, 21-3, 21-4).

Then, the semiconductor memory device 1 operates as DDR2 when viewed from the memory controller 100. That is, the memory controller 100 outputs the command CMD as control for the DDR2, and handles the input / output data DQ and the data strobe signal DQS at the timing of the DDR2.
In this case, the DDR2-IF module 211-2 performs writing / reading to / from the RAM array 30 in response to the command CM from the memory controller 100. Thus, by performing input / output at the timing of DDR2, an access operation that does not hinder the memory controller 100 is realized.

Next, operation examples of the common sequence unit and the dedicated module unit in the state transition diagram of FIG. 7 will be described with reference to FIGS.
Here, taking SDR-IF as an example, state transition of initialization, state transition of write (WRITE), state transition of write with auto precharge, state transition of read (READ), state transition of read with auto precharge, In addition, the state transition of auto refresh (REF) will be described.

  FIG. 9 is a diagram for explaining the state transition of initialization. FIG. 10 is a diagram for explaining the state transition of writing (WRITE). FIG. 11 is a diagram for explaining the state transition of writing with auto precharge. FIG. 12 is a diagram for explaining state transition of reading (READ). FIG. 13 is a diagram for explaining the state transition of reading with auto precharge. FIG. 14 is a diagram for explaining the state transition of auto refresh (REF).

The various commands shown in FIG. 7 are as follows.
MRS is a mode register setting command, EMRS is an extended mode register setting command, REFS is a self-refresh start command, REFSX is a self-refresh end command, REFA is a (CBR) auto-refresh command, PRE is a precharge command, ACT indicates a bank active, WRITE indicates a write command, WRITE indicates a write command with auto precharge, READ indicates a read command, and READA indicates a read command with auto precharge.
Further, SMd indicates an IF mode switching signal, CKEL indicates that the CKE signal is low, and CKEH indicates that the CKE signal is high.

First, with reference to FIGS. 9A to 9C, the state transition at the time of initialization will be described.
9A shows the power supply voltage Vcc, FIG. 9B shows the system clock CLK, and FIG. 9C shows various commands from the memory controller 100, respectively.

  When initialization is performed in the time chart as shown in FIGS. 9A to 9C, the state transition is as follows.

After the power is turned on, the process proceeds to the process A of the common sequence unit 210. In the process A, the initial sequence of the RAM array 30 is executed.
Each command of PALL → refresh command REF → refresh command REF → mode register setting command MRS is input from the external memory controller 100. When the mode register setting command MRS is detected, the process B is shifted to.
In process B, the burst length (BL), lap type, and CAS latency (CL) mode settings are detected.
In the case of DDR, DDR2, or the like that performs DLL setting, etc., transition is made to exception processing B, but in SDR-IF, after processing B, the state automatically transitions to IDLE (idle) state ST1.

Next, state transitions at the time of writing will be described in association with FIGS.
10A shows the system clock CLK, FIG. 10B shows various commands from the memory controller 100, and FIG. 10C shows write data from the memory controller 100, respectively.

  When writing is performed in the time chart as shown in the upper diagram as shown in FIGS. 10A to 10C, the state transition is as follows.

From the IDLE (idle) state ST1, a transition is made to any of process B, self refresh ST2, process C, power down ST3, and process D according to the command detected by the command detection unit 2101. To do.
When the bank active command ACT is received from the IDLE state ST1, the process D is entered. In the process D, it is determined whether the transition to the ACTIVE (active) state ST4 or the transition to the Active Power Down (active power down) state ST5 is received in response to the IF switching signal SMd. In the SDRAM, the state transits to the ACTIVE state ST4 as it is.

In the ACTIVE state ST4, the state transits to any one of Active Power Down ST5, Process E, Process F, Process G, Process H, and Precharge ST6.
When the write command WRITE is received from the ACTIVE state ST4, the process E is transited to. In process E, a write process to the RAM array 30 is performed.
When the writing process is completed, the state automatically changes to the ACTIVE state ST4. When the write command WRITE is continuously input, this transition is repeated.
When the precharge command PRE is received from the process E, the state transits to the Precharge state ST6 and automatically transits to the IDLE state ST1.
In the process E, the signal CKEL is received as the exception process E and a transition is made to the WRITE SUSPEND (write suspend) state. However, this is only in the case of the SDRAM and does not transit to the exception process E in the other IF modes. When the signal CKEH is received from the exception process E, the state transits to the process E state.

Next, state transition at the time of writing with auto precharge will be described with reference to FIGS.
11A shows the system clock CLK, FIG. 11B shows various commands from the memory controller 100, and FIG. 11C shows write data from the memory controller 100.

  When writing is performed in the time chart as shown in the upper diagram as shown in FIGS. 11A to 11C, the state transition is as follows.

When the bank active command ACT is received from the IDLE state ST1, the process D is entered. In the process D, it is determined whether the transition to the active state ST4 or the active power down state ST5 is received in response to the IF switching signal SMd. In the SDRAM, the state transits to the ACTIVE state ST4 as it is.
In the ACTIVE state ST4, the state transits to any one of Active Power Down ST5, Process E, Process F, Process G, Process H, and Precharge ST6e.
When the write WRITE with auto precharge is received from the ACTIVE state, the process shifts to process G. In process G, a write process to the RAM array 30 is performed. When the writing process is completed, the state automatically transitions to the Precharge state ST6 and further transitions to the IDLE state ST1.
In the process G, the signal CKEL is received as the exception process G and a transition is made to the WRITE SUSPEND (write suspend) state. However, this is only in the case of SDRAM and does not transition to the exception process G in the other IF modes. When the signal CKEH is received from the exception process G, the state transitions to the process G state.

Next, state transition at the time of reading will be described with reference to FIGS.
12A shows the system clock CLK, FIG. 12B shows various commands from the memory controller 100, and FIG. 12C shows read data to the memory controller 100.

  When reading is performed in the time chart as shown in the upper diagram as shown in FIGS. 12A to 12C, the state transition is as follows.

When the bank active command ACT is received from the IDLE state ST1, the process D is entered. In the process D, it is determined whether the transition is made to the active state ST4 or the active power down state ST5 in response to the IF switching signal SMd. In the SDRAM, the state transits to the ACTIVE state ST4 as it is.
In the ACTIVE state ST4, the state transits to any one of Active Power Down ST5, Process E, Process F, Process G, Process H, and Precharge.
When the read command READ is received from the ACTIVE state ST4, the process F is transited. In process F, a read process for the RAM array 30 is performed. When the reading process ends, the state automatically changes to the ACTIVE state ST4. When the read command READ is continuously input, this transition is repeated.
When the precharge command PRE is received from the process F, the state transits to the Precharge state ST6 and automatically transits to the IDLE state ST1.
In the process F, the signal CKEL is received as the exception process F and a transition is made to the READ SUSPEND (read suspend) state. However, this is only in the case of the SDRAM and does not transition to the exception process F in the other IF modes. When the signal CKEH is received from the exception process F, the state transits to the process F state.

Next, state transitions at the time of reading with auto precharge will be described with reference to FIGS.
13A shows the system clock CLK, FIG. 13B shows various commands from the memory controller 100, and FIG. 13C shows read data to the memory controller 100.

  When reading with auto-precharge is performed in the time chart as shown in the upper diagram as shown in FIGS. 13A to 13C, the state transition is as follows.

When the bank active command ACT is received from the IDLE state ST1, the process D is entered. In the process D, it is determined whether the transition to the active state ST4 or the active power down state ST5 is received in response to the IF switching signal SMd. In the SDRAM, the state transits to the ACTIVE state ST4 as it is.
In the ACTIVE state ST4, the state transits to any one of Active Power Down ST5, Process E, Process F, Process G, Process H, and Precharge ST6.
When the read command READA with auto precharge is received from the ACTIVE state ST4, the process shifts to the process H. In process H, a read process for the RAM array 30 is performed. When the reading process is completed, the state automatically transitions to the Precharge state ST6 and further transitions to the IDLE state ST1.
In the process H, the signal CKEL is received as the exception process H and a transition is made to the READ SUSPEND (read suspend) state, but this is only in the case of the SDRAM and does not transit to the exception process H in the other IF modes. When the signal CKEH is received from the exception process H, the state transits to the process H state.

Next, state transitions during auto-refresh will be described with reference to FIGS. 14 (A) and 14 (B).
14A shows the system clock CLK, and FIG. 14B shows various commands from the memory controller 100.

  When auto-refresh is performed using the time chart as shown in the upper diagram as shown in FIGS. 14A and 14B, the following state transition occurs.

  When the auto-refresh command REFA is received from the IDLE state ST1, the process C is shifted to. In process C, auto refresh is performed. When the auto refresh process is completed, the process automatically transitions to the exception process C. However, in the case of SDR-IF, nothing is performed in the exception process C, so the process transitions to the precharge state ST6 and further to the IDLE state ST1. . This transition is repeated when the auto-refresh command REFA is continuously input.

As described above, the DRAM-IF module group 21-1 according to the present embodiment converts common portions in the state transitions of the various DRAM-IF modules into a common sequence, and performs exceptions for portions that perform different processes in the respective state transitions. Since the processing is configured as a dedicated module, the circuit scale can be simplified by sharing the state transition.
In addition, power consumption can be reduced by sharing state transitions.
Also, by dividing the common sequence unit 210 and the dedicated module unit 211, it is possible to flexibly and easily cope with the expansion of the dedicated module.

Next, specific configurations and functions corresponding to a plurality of data widths in the adaptive converter (ADPCVT) 31 provided in the semiconductor memory devices 1 and 1A of FIGS. 2 and 6 will be described with reference to FIGS. This will be explained in association with each other.
Here, processing through the SDR-IF module 211-0 (or 21a in FIG. 6) will be described as an example.

  FIG. 15 is a block diagram illustrating a configuration example of an adaptive converter according to the present embodiment.

As shown in FIG. 15, the adaptive converter 31 includes an address conversion circuit 311, a data conversion circuit 312, and a command control circuit 313.
The address conversion circuit 311 issues an address issued by the interface module (here, the SDR-IF module 211-0 (21a)), and the mode interpreter 25 issues the address ADR of the RAM array 30 according to the mode signal Smd.
The data conversion circuit 312 outputs data from the interface module (here, the SDR-IF module 211-0 (21a)) as data DT of the RAM array 30 in accordance with the mode signal Smd by the mode interpreter 25.
The command control circuit 313 outputs a command from the interface module (here, the SDR-IF module 211-0 (21a)) as a command ACMD of the RAM array 30 in response to the mode signal Smd by the mode interpretation unit 25.

The adaptive converter 31 can arbitrarily vary the data width.
The adaptive converter 31 includes a plurality of control circuits as data width variable function units. Here, the adaptive converter 31 is roughly divided into an external data bus width of the memory controller 100 and a data bus of the RAM array 30. Processing when the width is the same, when the external data bus width of the memory controller 100 is 2 N, and when the external data bus width of the memory controller is not 2 N, will be described.

As a specific example corresponding to these three processes, as described above, if the data bus width of the RAM array 30 is 128 bits, as an example, the adaptive converter 31 converts the data of 128 bits wide, for example. When received, it is supplied to the RAM array 30 as the data width as it is.
As a second example, the adaptive converter 31 receives, for example, 32-bit width data (2 to the Nth power) from the outside, converts the data into 128-bit width data, and supplies it to the RAM array 30.
As a third example, the adaptive converter 31 receives, for example, 10-bit width data (data not 2 to the power of N), converts the data into 16-bit width data, and then converts the data into 128-bit width data. 30.
Hereinafter, the first to third examples will be further described in detail.

<First example>
In the first example, when the adaptive converter 31 receives, for example, data having a 128-bit width, the adaptive converter 31 outputs the same 128-bit data width to the RAM array 30 for writing and reading. Here, the burst length BL (Burst Length) = 4.
FIG. 16 is a diagram for explaining a write operation in the first example of the adaptive converter according to the present embodiment.

[writing]
In this case, the command control circuit 313 issues a write command WRITE to the RAM array 30 based on the burst length BL and bit width information identified by the mode interpretation unit 25.
Similarly, the address conversion circuit 311 issues an address to the RAM array 30 based on the burst length BL and bit width information identified by the mode interpretation unit 25.
The data conversion circuit 312 passes the data from the SDR-IF module 211-0 (21a) to the RAM array 30 as it is.

[reading]
FIG. 17 is a diagram for explaining a read operation in the first example of the adaptive converter according to the present embodiment.

In this case, the command control circuit 313 issues a read command READ to the RAM array 30 based on the burst length BL and bit width information identified by the mode interpretation unit 25.
The address conversion circuit 311 issues an address to the RAM array 30 based on the burst length BL and bit width information identified by the mode interpretation unit 25.
The data conversion circuit 312 passes the read data of the RAM array 30 as it is, the SDR-IF module 211-0 (21a).

<Second example>
In the second example, when the adaptive converter 31 receives, for example, 32-bit width data (2 N power data) from the outside, the adaptive converter 31 converts the data into 128-bit width data, outputs it to the RAM array 30, and writes it. Or it is an example in the case of reading. Also in this case, the burst length BL = 4.

[Write with data mask]
FIG. 18 is a diagram for explaining a write operation in the second example of the adaptive converter according to the present embodiment when there is a data mask.

In this case, the command control circuit 313 issues a write command WRITE to the RAM array 30 based on the burst length BL and bit width information identified by the mode interpretation unit 25. For example, when data mask control is used, write commands WRITE are issued continuously.
The address conversion circuit 311 issues an address to the RAM array 30 based on the burst length and bit width information identified by the mode interpretation unit 25.
The data conversion circuit 312 writes only relevant data into the RAM array 30 by data mask control.

[Write without data mask]
FIG. 19 is a diagram for explaining the write operation in the second example of the adaptive converter according to this embodiment when there is no data mask.

In this case, the command control circuit 313 issues a RAM array 30 read / write command READ / WRITE based on the burst length and bit width information identified by the mode interpretation unit 25.
The address conversion circuit 311 issues an address to the RAM array 30 based on the burst length and bit width information identified by the mode interpretation unit 25.
When data mask control is not performed, the data conversion circuit 312 reads data from the RAM array 30 once, and performs writing together with data to be written this time.

[reading]
FIG. 20 is a diagram for explaining a read operation in the second example of the adaptive converter according to the present embodiment.
In this case, Cas Latency CL = 2 and burst length BL = 4.

In this case, the command control circuit 313 issues a read command READ to the RAM array 30 based on the burst length and bit width information identified by the mode interpretation unit 25.
The address conversion circuit 311 issues an address to the RAM array 30 based on the burst length and bit width information identified by the mode interpretation unit 25.
The data conversion circuit 312 converts the data read from the RAM array 30 from parallel data to serial data, and outputs the data to the SDR-IF module 211-0 (21a).

<Third example>
In the third example, when the adaptive converter 31 receives, for example, 10-bit width data (data not 2 to the power of N), the adaptive converter 31 converts the data into 16-bit width data, and then converts the data into 128-bit width data. This is an example of outputting to the array 30 for writing or reading. Also in this case, the burst length BL = 4.

FIG. 21 is a diagram showing a write / read pattern after conversion in the third example of the adaptive converter according to the present embodiment.
FIG. 22 is a diagram illustrating an example of an address conversion table in the third example of the adaptive converter according to the present embodiment.
FIG. 23 is a diagram illustrating addresses to be read in the third example of the adaptive converter according to the present embodiment.

In order to efficiently store 10-bit width data in the 128-bit width RAM array 30, first, 10 bits are replaced with 16 bits, and the 16 bits are stored in the 128-bit width RAM array.
In this case, since there are five patterns as shown in FIG. 21 as storage patterns, writing and reading to the RAM array are controlled in consideration of these patterns.
In the example of FIG. 21, the first pattern PTN1 includes all of the data <1> and a part of the data <2>.
Second pattern PTN2 includes the remainder of data <2>, all of data <3>, and part of data <4>.
Third pattern PTN3 includes the remainder of data <4> and a portion of data <5>.
The fourth pattern PTN4 includes the rest of the data <5>, all of the data <6>, and a part of the data <7>.
The fifth pattern PTN5 includes the remainder of the data <7> and a part of the data <8>.

[Address control]
In the case of SDRAM with a burst length of 4 (BL = 4), two addresses from the SDR-IF module 221-0 (21a) are handled as one data block, and these data blocks are written and read in the pattern of FIG. The
First, in order to detect which pattern in FIG. 21 the address from the SDR-IF module 211-0 (21a) corresponds to, as shown in the address conversion table in FIG. Extract the bit.
In the case of a write address, the address conversion circuit 311 issues an address to the RAM array 30 according to the timing of the right table and the count En.
In the case of a read address, the address conversion circuit 311 issues an address according to the address conversion table of FIG.

[Address translation table]
In the address conversion table of FIG. 22, a case where the address width of the SDR-IF module is N is shown as an example.
The contents of the address conversion table of FIG. 22 are as follows.

When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN1 is “000”, the address of the RAM array 30 is the address “N-1: 4] * 5.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN2 is “001”, the address of the RAM array 30 is the address “N-1: 4] * 5 and the address“ N-1: 4] * 5 + 1.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN3 is “010”, the address of the RAM array 30 is the address “N−1: 4] * 5 + 1.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN4 is “011”, the address of the RAM array 30 is the address “N−1: 4] * 5 + 1 and the address“ N− 1: 4] * 5 + 2.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN5 is “100”, the address of the RAM array 30 is the address “N-1: 4] * 5 + 2 and the address“ N− 1: 4] * 5 + 3.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN6 is “101”, the address of the RAM array 30 is the address “N−1: 4] * 5 + 3.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN7 is “110”, the address of the RAM array 30 is the address “N-1: 4] * 5 + 3, and the address“ N− 1: 4] * 5 + 4.
When the address [3: 1] of the SDR-IF module 211-0 corresponding to the pattern PTN8 is “111”, the address of the RAM array 30 is the address “N-1: 4] * 5 + 4.

[writing]
FIG. 24 is a diagram for explaining a write operation in the third example of the adaptive converter according to the present embodiment.

The conversion from 10 bits to 16 bits is performed by converting each input bit from parallel to serial, and arranging two bits for 8 data in pairs.
The command control circuit 313 issues a write command WRITE to the RAM array 30 based on the burst length and bit width mode signal identified by the mode interpreter 25 and the information of the count En.
The address conversion circuit 311 issues an address to the RAM array 30 based on the burst length and bit width information identified by the mode interpretation unit 25 and the count En information.
The data conversion circuit 312 performs data mask control and writes the corresponding data.

[Reading] CL = 2, BL = 4
In the case of continuous address reading FIG. 25 is a diagram for explaining the continuous address reading operation in the third example of the adaptive converter according to the present embodiment.

In this case, based on the burst length, bit width (data width) identified by the mode interpretation unit 25, and the address from the SDR-IF module 211-0 (21a), the address of the RAM array 30 is designated and data is read out. .
When the read data of the RAM array 30 includes all the data of one pattern, when starting from <1>, <3>, <6>, <8>, a block corresponding to 8 data is extracted from the read data, Convert to parallel and expand sequentially.
For the next data, since the data block for 8 data spans two blocks, the first data is held, serial / parallel converted together with the second data block, and sequentially expanded Thus, it is possible to read efficiently.

In the case of single address read FIG. 26 is a diagram for explaining the single address read operation in the third example of the adaptive converter according to the present embodiment.

In this case, the address of the RAM array 30 is designated based on the burst length, bit width (data width), burst length, data width, and address from the SDR-IF module 211-0 (21a) identified by the mode interpreter 25. And read the data.
When the read data of the RAM array 30 starts from <2>, <4>, <5>, <7>, the data block for 8 data spans two blocks, so the first data is retained. Together with the second data block, serial / parallel conversion is performed and the data blocks are sequentially expanded.

  As described above, the adaptive converter 31 according to the present embodiment is roughly divided into data width variable function units. When the external data bus width of the memory controller 100 and the data bus width of the RAM array 30 are the same, the memory controller When the external data bus width of 100 is 2 to the Nth power, the data width can be adaptively processed without changing the external data bus width of the memory controller. Even when data other than the data width of the semiconductor memory device 1 is input, the data can be efficiently stored in the RAM array 30 and can be read out.

In this embodiment, the I / O width (data bus width) between each interface module side and the adaptive converter 31 (IF unit 3) is a bus width of a normal SDRAM, DDR, SRAM, or the like. A width wider than a certain 32 bits or 20 bits, for example, a width of 64 bits (or 128 bits) is set.
In this embodiment, the bus width between the adaptive converter 31 and the RAM array 30 is fixed to 128 bits.

If the I / O width of the semiconductor memory devices 1 and 1A is 32 bits, for example, as shown in FIG. 27A, a control device 100 having an I / O width of 64 bits and an SDRAM having an I / O width of 32 bits. Are connected.
In contrast, in the present embodiment, as shown in FIG. 27B, the I / O width is formed as a 64-bit multi-IF, so only one memory device is required. That is, the number of M memories can be reduced.

For example, when data stored in the SDRAM is converted by the control device 100B and stored in the SRAM, as shown in FIG. 28A, two memory devices, SDRAM and SRAM, are connected to the control device 100B. The
On the other hand, in the present embodiment, as described above, the adaptive converter 31 can switch the bus width in accordance with the mode signal. Therefore, by controlling the switching of the mode signal, FIG. As shown in FIG. 29B, the interface (IF) between the SDRAM and the SRAM can be used, and the storage area can be divided and used as shown in FIGS.
In the example of FIG. 30, the division information of the memory area is obtained from the mode signal Smd, the adaptive converter 31 controls the write (write) and read (read) addresses of the RAM array 30, and the SDRAM data area and the SRAM data area To distinguish.

Further, when the contents of the memory devices connected to the control devices having different interfaces (IF) are exchanged between the control devices, each memory device is required as shown in FIG.
On the other hand, in the present embodiment, as described above, by controlling the switching of the mode signal, the SDRAM (DDR) interface (IF) can be shared. For example, it can be used as a dual-port RAM with different interfaces (IF).

As described above, the multi-IF memory device having a wide I / O width can reduce the number of memories on the substrate by connecting as described above.
Further, when the contents stored in the memory are exchanged with different IFs, it can be performed by one memory device.

  As described above, each interface module implements input / output at the operation timing of the corresponding memory type to the memory controller 100. Here, the SDR-IF module 211-0 corresponding to the SDR is used. The operation of the DDR-IF module 211-1 corresponding to DDR will be described as an example.

  First, the timing of SDR and DDR read / write processing will be described with reference to FIGS. 32 and 33.

  FIGS. 32A and 32B show an example of read cycle timing and write cycle timing of a normal SDR-SDRAM. In particular, this shows a timing example of the system clock CLK, the command CMD, and the data input / output DQ when Cas Latency CL = 2 and Burst Length BL = 4.

  The SDRAM latches each command (control signal) CMD at the rising edge of the input clock CLK, and inputs / outputs data in synchronization with the clock CLK. The timing of the rising edge of the clock CLK is indicated by T1, T2,.

  As the read cycle timing in FIG. 32A, a read command READ supplied from the host side (for example, a memory control device corresponding to the memory controller 100) is latched at timing T1, for example. When the CAS latency CL = 2, the data Q0, Q1, Q2, and Q3 read in response to the read command READ are output to the host side after the timing T3 after two clocks.

  Also, as the write cycle timing of FIG. 32B, the write command WRITE supplied from the host side is latched at timing T1, for example. Further, the data Q0, Q1, Q2, and Q3 supplied from the host side are latched after the timing T1, and the writing process is performed.

On the other hand, FIGS. 33A and 33B show examples of the read cycle timing and the write cycle timing of the DDR-SDRAM. In this case as well, the case of CAS latency CL = 2 and burst length BL = 4 is shown, and timing examples of system clocks CLK1, CLK2, command CMD, data input / output DQ, and data strobe signal DQS are shown. The clock CLK2 is a phase inversion clock of the clock CLK1.
The DDR-SDRAM is controlled by inputting a command at the rising edge of the input clock CLK, similarly to the SDR-SDRAM, but the data input / output timing is different from that of the SDR-SDRAM.
The DDR-SDRAM uses two clocks CLK1 and CLK2 whose phases are inverted and a data strobe signal DQS in order to realize high-speed data transfer. The data strobe signal DQS is synchronized with the clock CLK1, and the data input / output DQ is synchronized with both rising and falling edges of the data strobe signal DQS.

  In the read cycle timing of FIG. 33A, for example, command processing is performed in synchronization with the rise of the clock CLK1 as timing T1. When CAS latency CL = 2, read data is output from timing T3 after two clocks. In this case, data Q0, Q1, Q2, and Q3 are output in synchronization with both edges of the data strobe signal DQS.

  In the write cycle timing of FIG. 33B, the write command supplied from the host side is latched at timing T1, for example. In addition, data Q0, Q1, Q2, and Q3 are written in synchronization with both edges of the data strobe signal DQS.

  DDR2, DDR3,... Are basically the same operation as DDR, and have a different operating frequency from the selectable cast latency CL.

For example, there are differences in processing timing due to differences in memory types such as SDR and DDR.
In the semiconductor memory device 1 of this example, each IF module of the interface module group 21 functions so as to absorb such a difference and operate as various memory types.

  FIG. 34 is a diagram showing input / output operation timing when the SDR-IF module 211-0 functions, and FIG. 35 is a diagram showing input / output operation timing when the DDR-IF module 211-1 functions.

  34 and 35 illustrate a case where the RAM array 30 has a performance of an access time tAC = 3 nsec from the address input to the data read and output. Moreover, the case where the cast latency CL = 2 is obtained is shown.

  FIG. 34 shows the timing when, for example, the memory controller 100 issues a read request by regarding the semiconductor memory device 1 as an SDR. That is, the semiconductor memory device 1 is set to the SDR mode and the SDR-IF module 211-0 functions.

FIG. 34A shows the basic clock BF, and the frequency of the basic clock BF is set to 100 MHz, for example. The basic clock BF is a clock having the same phase and the same frequency as that of the system clock CLK supplied from the memory controller 100 to the semiconductor memory device 1.
The clock 2BF in FIG. 34B is a clock having a frequency twice that of the basic clock BF, and the clock 2BF + π in FIG. 34C is an inverted clock obtained by shifting the clock 2BF by 180 °.
These clocks BF, 2BF, and 2BF + π are generated by the PLL unit 24 based on the input system clock CLK, and supplied to the SDR-IF module 211-0 as a processing clock group.

FIG. 34D shows input / output to / from the memory controller 100 performed by the SDR-IF module 211-0 via the IO buffer 22.
FIG. 34E shows the timing at which the SDR-IF module 211-0 issues an address to the RAM array 30 (adaptive converter 31).
FIG. 34F shows the timing at which read data from the RAM array 30 is transferred to the SDR-IF module 211-0.
FIG. 34G shows the timing when the SDR-IF module 211-0 expands the read data and delivers it to the IO buffer 22.

For example, assume that a read command is fetched from the memory controller 100 at timing T1. In this case, the SDR-IF module 211-0 performs command interpretation and read address recognition processing, and issues an address to the RAM array 30 at timing T2 after 5 nsec.
Since the RAM array 30 has an access time tAC = 3 nsec, read data is transferred to the SDR-IF module 21a after 3 nsec. Then, the SDR-IF module 211-0 expands and outputs the read data Q0, Q1, Q2, Q3.
In this case, the read data Q0, Q1, Q2, and Q3 are expanded at the rising timing of the reference clock BF after the timing T3 after 4.5 nsec, and output to the memory controller 100 via the IO buffer 22.

With such an operation, the semiconductor memory device 1 realizes a read operation equivalent to that of the SDR-SDRAM with the CAS latency CL = 2.
In other words, the memory controller 100 may issue a command by regarding the semiconductor memory device 1 as an SDR. On the other hand, the semiconductor memory device 1 performs an SDR as an SDR according to a command by processing of the SDR-IF module 211-0. Perform the operation with the required cast latency.

FIG. 34 shows an example in which the access time tAC of the RAM array 30 is set to 3 nsec. However, when the access time tAC is late, the processing in the SDR-IF module 211-0 is speeded up.
For example, if the access time tAC = 5 nsec and the CAS latency CL = 2 is required, the SDR-IF module 211-0 performs the output of the read data after 2.5 nsec, so that the timing T3 The read data Q0, Q1, Q2, and Q3 can be output.
Further, for example, if the access time tAC = 8 nsec and the CAS latency CL = 2 is required, the SDR-IF module 211-0 reads the RAM array 30 after 2.5 nsec from the read command latch at the timing T 1. An address is issued for this. Then, the expanded output of the read data transferred after 8 nsec may be executed from the timing T3 after 2 nsec.

  Next, FIG. 35 shows the timing when the memory controller 100 issues a read request with the semiconductor memory device 1 regarded as a DDR. That is, FIG. 35 shows a case where the semiconductor memory device 1 is set to the DDR mode and the DDR-IF module 211-1 functions.

The basic clock BF in FIG. 35A is a clock having the same phase and the same frequency as the system clock CLK supplied to the semiconductor memory device 1 by the memory controller 100, and the frequency is set to 133 MHz, for example.
The clock 2BF in FIG. 35B is a clock having a frequency twice that of the basic clock BF, and the clock 2BF + π in FIG. 35C is an inverted clock obtained by shifting the clock 2BF by 180 °.
These clocks BF, 2BF, and 2BF + π are generated by the PLL unit 24 based on the input system clock CLK, and are supplied as a processing clock group to the DDR-IF module 211-1.

FIG. 35D shows input / output with respect to the memory controller 100 performed by the DDR-IF module 211-1 via the IO buffer 22.
FIG. 35E shows the address processing timing of the DDR-IF module 211-1.
FIG. 35F shows the timing at which the DDR-IF module 211-1 issues an address to the RAM array 30 (adaptive converter 31).
FIG. 35G shows the timing at which read data from the RAM array 30 is transferred to the DDR-IF module 211-1.
FIG. 35H shows the timing of the read data expansion processing by the DDR-IF module 211-1.
FIG. 35I shows the timing when the DDR-IF module 211-1 delivers the expanded read data to the IO buffer 22.

For example, it is assumed that a read command from the memory controller 100 is input at timing T1. The DDR-IF module 211-1 performs address processing for 3.76 nsec and issues an address to the RAM array 30.
Since the RAM array 30 has an access time tAC = 3 nsec, read data is transferred to the DDR-IF module 211-1 after 3 nsec. Then, the DDR-IF module 211-1 develops the read data Q0, Q1, Q2, and Q3 after 0.76 nsec, and after the timing T3 after 5.6 nsec, both rising and falling edges of the reference clock BF The read data Q0, Q1, Q2, and Q3 are output to the memory controller 100 via the IO buffer 22 at the timing shown in FIG.

With such an operation, the semiconductor memory device 1 realizes a read operation equivalent to that of the DDR-SDRAM with the CAS latency CL = 2.
In other words, the memory controller 100 may issue a command by regarding the semiconductor memory device 1 as a DDR. On the other hand, the semiconductor memory device 1 performs processing as the DDR according to the command by the processing of the DDR-IF module 211-1. Perform the operation with the required cast latency.

  FIG. 35 shows an example in which the access time tAC of the RAM array 30 is 3 nsec. Also in this case, if the access time tAC is slow, the processing in the DDR-IF module 21b can be handled at high speed. Good.

In the above, the read operation timing when the SDR-IF module 211-0 and the DDR-IF module 211-1 function is shown, but when other interface modules such as the DDR2-IF module 211-2 function, An operation corresponding to the corresponding memory type may be realized.
In the case of the configuration of FIG. 2, the semiconductor memory device 1 can be configured to function as SDR, DDR, DDR2-DDR ( n) Can operate as any one of SRAM, DPRAM, and FIFO.

[3. Mode operation of PLL section]
By the way, when the semiconductor memory device 1 operates as various memory types, each unit performs processing according to the mode in accordance with the mode signal Smd from the mode interpretation unit 25 as described above.
In particular, the PLL unit 24, the selector 23, and the IO buffer 22 perform operations corresponding to the mode signal Smd. Hereinafter, this mode operation will be described.

  First, the mode operation of the PLL unit 24 will be described here.

  FIG. 36 shows a specific configuration example of the PLL unit 24. For simplification of illustration and description, here, as a clock output system, a portion corresponding to three interface modules of the SDR-IF module 211-0, the DDR-IF module 211-1, and the DDR2-IF module 211-2. Only the mode operation of the PLL unit 24 will be described. In FIG. 36, the common sequence unit 210 is omitted for easy understanding.

The system clock CLK supplied from the memory controller 100 is supplied to the clock generation PLL circuit 242 via the buffer amplifier 241. The clock generation PLL circuit 242 is formed as a PLL (Phase Locked Loop) circuit including a phase comparator, a loop filter, a VCO (voltage controlled oscillator), and a doubler, for example.
The clock generation PLL circuit 242 outputs a clock 2BF having a double frequency synchronized with the system clock CLK while performing a phase comparison between the system clock CLK and the output of the 1/2 frequency divider 243. This clock 2BF is supplied to the switching circuit 245.
The clock 2BF is frequency-divided by a 1/2 frequency divider 243 to have the same frequency as the system clock CLK, and then fed back to the clock generation PLL circuit 242 as a phase comparison clock. The clock divided by the / 2 frequency divider 243 is supplied to the switching circuit 247 as the reference clock BF having the same phase and the same frequency as the system clock CLK.
Further, the clock 2BF output from the clock generation PLL circuit 242 is phase-shifted by the phase shifter 244 to generate a phase-inverted clock 2BF + π. This clock 2BF + π is supplied to the switching circuit 246.

The switching circuits 245, 246, and 247 have S, D1, and D2 terminals as output terminals, respectively.
The S terminal is a terminal connected to the SDR-IF module 211-0 (21a).
The D1 terminal is a terminal connected to the DDR-IF module 211-1 (21b).
The D2 terminal is a terminal connected to the DDR2-IF module 211-1 (21c).
In addition, the switching circuits 245, 36, and 37 are each provided with a fixed voltage terminal F to which an H level voltage Hi is supplied. The fixed voltage terminal F may be an L level voltage. Or you may be in a high impedance state.

  As described above, in FIG. 36, only the clock output system for the three interface modules (211-0, 211-1, 211-2) is shown, so that the switching circuits 245, 246, 247 have three output terminals. In reality, however, the switching circuits 245, 246 and 247 are also provided with output terminals for the other interface modules (211-3 to 211-n, 21-2, 21-3, 21-4). It can be selected.

  For such a PLL unit 24, the mode signal Smd from the mode interpretation unit 25 is supplied to the switching circuits 245, 246 and 247. The switching circuits 245, 246 and 247 switch the connection state according to the mode signal Smd.

For example, when the mode signal Smd is a signal indicating the SDR mode, the switching circuits 245, 246, and 247 select the S terminals as output terminals, respectively. Output terminals not selected in the mode (D1 terminal, D2 terminal and other output terminals not shown) are connected to the fixed voltage terminal F.
This state is shown in FIG. 36, whereby the clocks 2BF, 2BF + π, and BF are supplied to the SDR-IF module 211-0 from each S terminal as a processing clock group for the SDR-IF module 211-0, respectively. Will be.
For example, when the 100 MHz system clock CLK is supplied from the memory controller 100, the 100 MHz reference clock BF shown in FIG. 34A and the double frequency clocks 2BF and 2BF + π are supplied to the SDR-IF module 211-0. The
The SDR-IF module 211-0 functions by supplying the processing clock group.
On the other hand, the DDR-IF module 211-1, the DDR2-IF module 211-2 (and other interface modules 211-3 to 211-n, 21-2, 21-3, 21-4 not shown) have processing clocks. It is not supplied and the operation function is turned off.

Further, for example, when the mode signal Smd is a signal indicating the DDR mode, the switching circuits 245, 246 and 247 select the D1 terminal as the output terminal, respectively, and other output terminals (S terminal, D2 terminal and other not shown) Output terminal) is connected to the fixed voltage terminal F. As a result, the clocks 2BF, 2BF + π, and BF are supplied to the DDR-IF module 211-1 from each D1 terminal as a processing clock group for the DDR-IF module 211-1.
For example, when the 133 MHz system clock CLK is supplied from the memory controller 100, the 133 MHz reference clock BF shown in FIG. 35A and the double frequency clocks 2BF and 2BF + π are supplied to the DDR-IF module 211-1. The
By supplying the processing clock group, the DDR-IF module 211-1 functions, while the SDR-IF module 211-0 and the DDR2-IF module 211-2 (and other interface modules 211-3 not shown). ˜ 211-n, 21-2, 21-3, 21-4), the processing clock is not supplied and the operation function is turned off.

  For example, as described above, the PLL unit 24 supplies the interface modules 211-0 to 211-n, 21-2, 21-3, and 21-4 with a clock according to the mode signal Smd. One necessary interface module functions, and the other interface module is turned off.

[4. Selector mode operation]
The mode operation of the selector 23 will be described with reference to FIG.
In FIG. 37, as in the case of FIG. 36, only the portions corresponding to the three interface modules of the SDR-IF module 211-0, the DDR-IF module 211-1, and the DDR2-IF module 211-2 are used as interface modules. Is shown. In FIG. 37, the common sequence unit 210 is omitted for easy understanding.

As described above, the command CMD, the input / output data DQ, and the data strobe signal DQS are input / output between the memory controller 100 and the IO buffer 22, and the transfer of these signals in the selector 23 includes command CMD, data input. DQin, data output DQout, strobe signal input DQSin, and strobe signal output DQSout are transferred.
That is, the selector 23 transfers the command CMD input from the memory controller 100 to the IO buffer 22 to the interface module group 21.
When the command CMD is a write command, write data is input from the memory controller 100 to the IO buffer 22. The selector 23 transfers this write data to the interface module group 21 as the data input DQin.
If the command CMD is a read command, data is read from the RAM array 30 by the interface module group 21, but the selector 23 transfers this read data to the IO buffer 22 as a data output DQout.
When the mode is DDR to DDR (n), the data strobe signal DQS is used. The selector 23 transfers the input and output of the data strobe signal DQS as the strobe signal input DQSin and the strobe signal output DQSout.

The selector 23 is provided with selection switch circuits 23a to 23e according to these signals.
The selection switch circuit 23a corresponds to the command CMD, and an S terminal, a D1 terminal, and a D2 terminal are formed as output terminals for the interface module group 21.
The selection switch circuit 23b corresponds to the data input DQin, and an S terminal, a D1 terminal, and a D2 terminal are formed as output terminals for the interface module group 21.
The selection switch circuit 23c corresponds to the data output DQout, and an S terminal, a D1 terminal, and a D2 terminal are formed as input terminals from the interface module group 21.
The selection switch circuit 23d corresponds to the strobe signal input DQSin, and has a D1 terminal and a D2 terminal as output terminals for the interface module group 21.
The selection switch circuit 23e corresponds to the strobe signal output DQSout, and has a D1 terminal and a D2 terminal as input terminals from the interface module group 21.

  In FIG. 37, only the input / output system for the three interface modules (211-0, 211-1, 211-2) is shown, and therefore the selection switch circuits 23a to 23e include other interface modules (211). -3 to 211-n, 21-2, 21-3, and 21-4) are not shown, but actually, other interface modules (211-3 to 211-n, 21-2, Output terminals or input terminals for 21-3, 21-4) are also formed and selectable.

Each selection switch circuit 23 a to 23 e of the selector 23 selects an output terminal or an input terminal according to the mode signal Smd from the mode interpretation unit 25.
For example, when the mode signal Smd is a signal indicating the SDR mode, the selection switch circuits 23a, 23b, and 23c each select the S terminal. Since the data strobe signal DQS is not used in SDR, the selection switch circuits 23d and 23e may be disconnected.
Thereby, transfer of the command CMD, the data input DQin, and the data output DQout is realized between the IO buffer 22 and the SDR-IF module 211-0.

For example, when the mode signal Smd is a signal indicating the DDR mode, the selection switch circuits 23a to 23e select the D1 terminal, respectively.
FIG. 37 shows this state. In this state, the command CMD, the data input DQin, the data output DQout, the strobe signal input DQSin, and the strobe signal output DQSout are between the IO buffer 22 and the DDR-IF module 211-1. Is realized.

  For example, as described above, the selection switch circuits 23a to 23e of the selector 23 perform connection selection according to the mode signal Smd, so that signal transfer between one functioning interface module and the IO buffer 22 is performed. Thus, signal input / output between the one functioning interface module and the memory controller 100 is executed.

[5. IO buffer mode operation]
As the mode operation of the IO buffer 22, switching of the buffer power supply voltage characteristic and the delay characteristic according to the mode (memory type to be executed) is performed.
The buffer power supply voltage varies depending on the memory type. For example, 3.3V or 2.5V for SDR, 2.5V for DDR, 1.8V for DDR2, 1.5V for DDR3, and the like. Therefore, in the case of the semiconductor memory device 1 of this example, the IO buffer 22 needs to be switched in the operating power supply voltage depending on the mode.

38 to 42 show configuration examples of the IO buffer 22 for switching the power supply voltage and the delay characteristics, respectively. In each figure, an operation of switching two power supply voltages as type A and type B will be described. For example, a buffer amplifier with “A” in the figure is a type A buffer with a power supply voltage of 3.3 V and a delay characteristic of τ1, and a buffer amplifier with “B” in the figure has a power supply voltage of 2.5 V. Suppose that the type B buffer has a delay characteristic of 2.
Here, switching of electrical characteristics as type A and type B will be described, but in actuality, switching of electrical characteristics of the required number of types is possible depending on the number and types of memory types that the semiconductor memory device 1 can handle. It goes without saying that the configuration is performed.
In each figure, three signal paths are shown as an input system, an output system, and a bidirectional system. However, specific signal paths may be considered to correspond to any of these. For example, it can be considered that the signal paths of the command CMD and the data input DQin each have the input system configuration shown in the figure.
The internal logic 40 in FIGS. 38 to 42 is a block that comprehensively shows the selector 23, the PLL unit 24, and the interface module group 21.

First, an example of FIG. 38 will be described.
The IO buffer 22 is provided with a type A buffer 44, a type B buffer 48, and switches 41 and 53 as input systems.
The IO buffer 22 is provided with a type A buffer 45, a type B buffer 49, and switches 42 and 54 as an output system.
The IO buffer 22 is provided with a type A buffer 46, a type A / 3-state buffer 47, a type B buffer 50, a type B / 3-state buffer 51, and switches 43, 55, and 56 as bidirectional systems.
The mode instruction signal Md is supplied to the mode interpretation unit 25 via the buffer amplifier 52.

As power lines introduced from the outside of the semiconductor memory device 1, a type A buffer power line 70, a type B buffer power line 71, an internal logic power line 72, and a mode buffer power line 73 are provided. Is formed.
For example, the type A buffer power line 70 is a 3.3 V power line, and the type A buffer power line 70 includes type A buffers 44, 45, 46, type A 3-state buffer 47, switch 41, Power is supplied to 42 and 43.
The type B buffer power supply line 71 is, for example, a 2.5 V power supply line. The type B buffer power supply line 71 supplies power to the type B buffers 48, 49, 50 and the type B 3 state buffer 51. I do.
The internal logic power supply line 72 supplies an operation power supply voltage to each circuit unit (the interface module group 21 and the PLL unit 24) and the mode interpretation unit 25 in the internal logic 40, and switches the switches 53, 54, 55, and 56. Supply operation power supply voltage for operation.
The mode buffer power supply line 73 supplies an operation power supply voltage to the buffer amplifier 52.

  In this example, the operation power supply voltage is supplied to the switches 41, 42, and 43 through the type A buffer power supply line 70, which is supplied with the power supply voltage that enables the switching operations of the switches 41, 42, and 43. The operation power supply voltage of the switches 41, 42, and 43 may be supplied from another power supply line.

Each of the switches 41, 42, 43, 53, 54, 55, and 56 is configured to be able to switch between an a terminal corresponding to type A and a b terminal corresponding to type B.
Each switch 41, 42, 43, 53, 54, 55, 56 switches the connection terminal according to the mode signal Smd from the mode interpretation unit 25.

  For example, when a memory type corresponding to type A is indicated by the mode signal Smd, each switch 41, 42, 43, 53, 54, 55, 56 selects the a terminal. As a result, in the IO buffer 22, the type A buffers 44, 45, and 46 and the type A 3 state buffer 47 function to input / output various signals, that is, according to the memory type corresponding to the type A. Input / output buffer operation is realized.

  When the mode signal Smd indicates a memory type corresponding to type B, each of the switches 41, 42, 43, 53, 54, 55, and 56 selects the b terminal. As a result, in the IO buffer 22, the type B buffers 48, 49, 50 and the type B 3 state buffer 51 function to input / output various signals, that is, according to the memory type corresponding to the type B. Input / output buffer operation is realized.

Here, as a type A and a type B, a description has been given of a model of switching between two electrical characteristic types. It is assumed that the number of types will be larger.
For example, many types such as type C, type D,... Are required as electrical characteristic types having different power supply voltages and delay characteristics. In that case, a buffer amplifier corresponding to each type may be mounted in the same manner as the above types A and B, and the switches 41, 42, 43, 53, 54, 55, and 56 may be selected.
In the following, other configurations will be described with reference to FIGS. 39 to 42, and it is the same that the configuration should be considered in an expanded manner so as to correspond to a larger number of electrical characteristic types.

Next, another configuration example of the IO buffer 22 will be described with reference to FIG. Note that the same parts as those in FIG.
In the example of FIG. 39, three power supply lines are introduced into the semiconductor memory device 1 from the outside. That is, the buffer power line 74, the mode buffer power line 73, and the internal logic power line 72.

The buffer power line 74 is a power line to the switches 41, 42, and 43, and the connection destination is switched between the A type system and the B type system by the power line switch 57.
The mode signal Smd is supplied to each switch 41, 42, 43, 53, 54, 55, 56 and the power line switch 57.
When the semiconductor memory device 1 is mounted on the circuit board of the electronic device, a predetermined power supply voltage is supplied to the buffer power line 74 according to the memory type used for the semiconductor memory device 1. Is done.
For example, in the electronic device, when the semiconductor memory device 1 is handled as SDR, the buffer power supply line 74 is fixedly connected to the 3.3V power supply line by circuit board wiring. On the other hand, for example, in the electronic device, when the semiconductor memory device 1 is handled as DDR, the buffer power line 74 is fixedly connected to the 2.5 V power line by circuit board wiring.

For example, when the memory type corresponding to type A is indicated by the mode signal Smd, each switch 41, 42, 43, 53, 54, 55, 56 selects the a terminal, and the power line switch 57 is also the a terminal. Select.
In this case, since the buffer power supply line 74 is a 3.3V power supply line, a 3.3V power supply voltage is supplied to the type A buffers 44, 45, 46 and the type A / 3 state buffer 47. Accordingly, in the IO buffer 22, the type A buffers 44, 45 and 46 and the type A / 3-state buffer 47 function to input / output various signals, and an input / output buffer corresponding to the memory type corresponding to the type A Operation is realized.

When the memory type corresponding to type B is indicated by the mode signal Smd, each switch 41, 42, 43, 53, 54, 55, 56 selects the b terminal, and the power line switch 57 also selects the b terminal. To do.
In this case, since the buffer power supply line 74 is a 2.5 V power supply line, a 2.5 V power supply voltage is supplied to the type B buffers 48, 49, 50 and the type B 3-state buffer 51. Accordingly, in the IO buffer 22, the type B buffers 48, 49, 50 and the type B 3 state buffer 51 function to input / output various signals, and an input / output buffer corresponding to the memory type corresponding to the type B is provided. Operation is realized.

Subsequently, an example of FIG. 40 will be described.
In the example of FIG. 40, the power supply line introduced from the outside into the semiconductor memory device 1 is only the common power supply line 76. A DC / DC converter (DDC) 58 is provided in the IO buffer 22.
The DC / DC converter 58 performs voltage conversion on the power supply voltage from the common power supply line 76 and supplies a predetermined voltage to each power supply line.
That is, the DC / DC converter 58 supplies the power supply voltage to the switches 41, 42, and 43 through the switch power supply line 75.
The DC / DC converter 58 supplies a 3.3 V power supply voltage to the type A buffers 44, 45, 46 and the type A 3 state buffer 47 through the type A buffer power line 70.
The DC / DC converter 58 supplies a power supply voltage of 2.5 V to the type B buffers 48, 49, 50 and the type B 3 state buffer 51 through the type B buffer power supply line 71.
The DC / DC converter 58 supplies the power supply voltage to the buffer amplifier 52 through the mode buffer power supply line 73.
The DC / DC converter 58 supplies a power supply voltage to the internal logic 40, the switches 53, 54, 55, and 56 and the mode interpretation unit 25 through the internal logic power supply line 72.

  The mode signal Smd from the mode interpreter 25 is supplied to the switches 41, 42, 43, 53, 54, 55, 56 and the DC / DC converter 58. The DC / DC converter 58 selectively executes power supply voltage output to the type A buffer power supply line 70 and power supply voltage output to the type B buffer power supply line 71 in accordance with the mode signal Smd.

For example, when the memory type corresponding to type A is indicated by the mode signal Smd, each switch 41, 42, 43, 53, 54, 55, 56 selects the a terminal, and the DC / DC converter 58 The operation power supply voltage is supplied to the switch power supply line 75, the mode buffer power supply line 73, and the internal logic power supply line 72, and the 3.3 A power supply voltage is supplied to the type A buffer power supply line 70. .
Accordingly, in the IO buffer 22, the type A buffers 44, 45 and 46 and the type A / 3-state buffer 47 function to input / output various signals, and an input / output buffer corresponding to the memory type corresponding to the type A Operation is realized.

When the memory type corresponding to type B is indicated by the mode signal Smd, each switch 41, 42, 43, 53, 54, 55, 56 selects the b terminal, and the DC / DC converter 58 The operation power supply voltage is supplied to the power supply line 75, the mode buffer power supply line 73, and the internal logic power supply line 72, and the 2.5V power supply voltage is supplied to the type B buffer power supply line 71.
Accordingly, in the IO buffer 22, the type B buffers 48, 49, 50 and the type B 3 state buffer 51 function to input / output various signals, and an input / output buffer corresponding to the memory type corresponding to the type B is provided. Operation is realized.

Next, an example of FIG. 41 will be described. However, the example of FIG. 41 is a configuration example in which the IO buffer 22 is not internally switched by the mode signal Smd.
In this case, the IO buffer 22 is provided with a common buffer 81 as an input system. A common buffer 82 is provided as an output system. As a bidirectional system, a common buffer 83 and a common 3-state buffer 84 are provided.
The common buffers 81, 82, and 83 and the common three-state buffer 84 are buffer amplifiers that can allow a voltage range and a delay with an applied voltage.

The power supply lines introduced into the semiconductor memory device 1 from the outside are the three power supply lines, ie, the buffer power supply line 74, the mode buffer power supply line 73, and the internal logic power supply line 72.
The buffer power supply line 74 is formed as a power supply line for supplying power to the common buffers 81, 82, 83 and the common three-state buffer 84.
The internal logic power supply line 72 is formed as a power supply line for supplying power to each part in the internal logic 40 and the mode interpretation unit 25.
The mode buffer power supply line 73 is formed as a power supply line for supplying power to the buffer amplifier 52.

When the semiconductor memory device 1 is mounted on the circuit board of the electronic device, a predetermined power supply voltage is supplied to the buffer power line 74 according to the memory type used for the semiconductor memory device 1. Is done.
For example, in the electronic device, when the semiconductor memory device 1 is handled as SDR, the buffer power supply line 74 is fixedly connected to the 3.3V power supply line by circuit board wiring.
On the other hand, for example, in the electronic device, when the semiconductor memory device 1 is handled as DDR, the buffer power line 74 is fixedly connected to the 2.5 V power line by circuit board wiring.

In the case of this configuration, the IO buffer 22 does not need to perform a switching operation based on the mode signal Smd from the mode interpretation unit 25. The switching operation by the mode signal Smd is performed in the selector 23 and the PLL unit 24 in the internal logic 40.
For example, when the semiconductor memory device 1 is handled as SDR, the buffer power supply line 74 is a 3.3V power supply line, and the common buffers 81, 82, and 83 and the common three-state buffer 84 operate with a power supply voltage of 3.3V.
Further, for example, when the semiconductor memory device 1 is handled as DDR, the buffer power supply line 74 is a 2.5V power supply line, and the common buffers 81, 82, 83 and the common 3-state buffer 84 operate with a power supply voltage of 2.5V. To do.

Next, the example of FIG. 42 will be described.
This example includes common buffers 81, 82, 83 and a common three-state buffer 84 as in FIG. 41. However, the power supply line introduced from the outside into the semiconductor memory device 1 is only the common power supply line 76. . A DC / DC converter 85 is provided in the IO buffer 22.
The DC / DC converter 85 performs voltage conversion on the power supply voltage from the common power supply line 76 and supplies power of a predetermined voltage to each power supply line.
That is, the DC / DC converter 85 supplies the power supply voltage to the common buffers 81, 82, 83 and the common three-state buffer 84 through the buffer power supply line 74.
The DC / DC converter 85 supplies a power supply voltage to the buffer amplifier 52 through the mode buffer power supply line 73.
The DC / DC converter 85 supplies a power supply voltage to the internal logic 40 and the mode interpretation unit 25 through the internal logic power supply line 72.

  The mode signal Smd from the mode interpretation unit 25 is supplied to the DC / DC converter 85 in the IO buffer 22. The DC / DC converter 85 switches the power supply voltage supplied to the buffer power supply line 74 in accordance with the mode signal Smd.

For example, when the SDR mode is instructed by the mode signal Smd, the DC / DC converter 85 supplies each operation power supply voltage to the mode buffer power supply line 73 and the internal logic power supply line 72 and also supplies the buffer power supply line. The power supply voltage applied to 74 is set to 3.3V.
As a result, the common buffers 81, 82, 83 and the common three-state buffer 84 perform an input / output buffer operation according to the SDR.

For example, when the DDR mode is instructed by the mode signal Smd, the DC / DC converter 85 supplies each operation power supply voltage to the mode buffer power supply line 73 and the internal logic power supply line 72 and also supplies the buffer power supply. The power supply voltage applied to the line 74 is set to 2.5V.
As a result, the common buffers 81, 82, 83 and the common three-state buffer 84 perform input / output buffer operations according to DDR.

  As described above, by adopting the configuration as shown in FIGS. 38 to 42 as the IO buffer 22, an input / output buffer operation corresponding to each mode (memory type) can be executed.

[6. Other Configuration Examples of Semiconductor Memory Device]
Although the configuration of the semiconductor memory device 1 according to the present embodiment is shown in FIG. 2, other configuration examples are conceivable as the semiconductor memory device 1. FIG. 43 illustrates another configuration example. The same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

The configuration example of FIG. 43 is an example in which a dedicated IO buffer is provided so as to correspond to each of the interface modules 211-0 to 211-n, 21-2, 21-3, and 21-4.
That is, the IO buffer 22a for the SDR-IF module 211-0, the IO buffer 22b for the DDR-IF module 211-1, the IO buffer 22c for the DDR2-IF module 211-2, and the DDR (n) -IF module 211- An n-type IO buffer 22d, an SRAM-IF module 21-2 IO buffer 22e, a DPRAM-IF module 21-3 IO buffer 22f, and a FIFO-IF module 21-4 IO buffer 22g are provided.
An input buffer 22h corresponding to the system clock CLK is provided, and the system clock CLK is supplied to the PLL unit 24 via the input buffer 22h.
An input buffer 22i corresponding to the mode instruction signal Md is provided, and the mode instruction signal Md is supplied to the mode interpretation unit 25 through the input buffer 22i.

In this case, the IO buffers 22a to 22g are dedicated input / output signal systems, buffer amplifiers, and connection terminals corresponding to the corresponding interface modules 211-0 to 211-n, 21-2, 21-3, and 21-4, respectively. Have
For example, the IO buffer 22a corresponding to the SDR-IF module 211-0 has an input terminal and an input buffer for the command CMD, an input terminal and an input buffer for the data input DQin, and an output terminal and an output buffer for the data output DQout. . Of course, each buffer in the IO buffer 22a has electrical characteristics corresponding to the SDR.
Further, for example, the IO buffer 22b corresponding to the DDR-IF module 211-1 includes an input terminal and an input buffer for the command CMD, an input terminal and an input buffer for the data input DQin, and an output terminal and an output buffer for the data output DQout. Have an input / output terminal and an input / output buffer for data strobe signal DQS. Of course, each buffer in the IO buffer 22b has electrical characteristics according to DDR.

In the case of such a configuration, when mounting the semiconductor memory device 1 on a circuit board of an electronic device, depending on which memory type the semiconductor memory device 1 is used, an IO buffer connected to the memory controller 100 is provided as an IO buffer. One of the buffers 22a to 22g is selected.
For example, when the semiconductor memory device 1 is used as the DDR in the electronic device, the substrate wiring is designed so that the terminal of the IO buffer 22b is connected to the memory controller 100, for example. In this case, as shown in FIG. 44, various signals are input / output between the memory controller 100a and the DDR-IF module 211-1 via the IO buffer 22b. At this time, the other IO buffers 22a and 22c to 22g are not used.
Naturally, the mode instruction signal Md is a signal indicating the DDR mode, and the mode interpretation unit 25 supplies the PLL unit 24 with the mode signal Smd as the DDR mode. As a result, the PLL unit 24 gives a processing clock group to the DDR-IF module 211-1, causing the DDR-IF module 211-1 to function, and other interface modules 211-0, 211-n, 21-2-21- For 4, the clock supply is stopped and the operation is turned off.
Thereby, the semiconductor memory device 1 functions as a DDR.
In the case of this configuration, the selector 23 shown in FIG. 2 is not necessary.

  Depending on the power supply configuration of the IO buffers 22a to 22g, for example, 2.5 V buffer operation power is supplied to the IO buffer 22b by the mode signal Smd. Alternatively, when a common power supply line is formed in the IO buffers 22a to 22g, the power supply line may be connected to a 2.5V power supply line depending on the board design.

  43 and 44 are other configuration examples corresponding to the configuration of FIG. 2, but the configuration shown in FIGS. 45 and 46 is the same as another configuration example corresponding to the configuration of FIG. Needless to say, it is possible. Since the basic concept is the same as in the case of FIGS. 43 and 44, detailed description thereof is omitted.

As described above, the embodiment has been described. By using the semiconductor memory device 1 according to the embodiment, the circuit scale can be simplified and the increase in power consumption can be suppressed, and the memory can be used as various types of memory. In addition, it is possible to cope with the case where data less than the data width of this apparatus is input, and it is possible to realize the efficiency of device manufacturing and design and the stabilization of manufacturing. And since it is configured as a multi-IF memory device with a wide I / O width, the number of memories on the substrate can be reduced.
Further, when the contents stored in the memory are exchanged with different IFs, it can be performed by one memory device.
For example, in an electronic device equipped with a memory type memory, when the supply of the memory type memory becomes unstable, the memory is replaced with the semiconductor memory device 1 and the same operation as the previous memory is executed. By doing so, it is possible to continue device manufacturing without changing the design of the memory control circuit and the peripheral circuit.
In addition, when designing a new electronic device, by adopting the semiconductor memory device 1 as a memory chip to be mounted, a highly flexible design and an efficient design are possible, and the specification of the memory itself will be changed in the future. Even when it is desired to change the memory type, it can be easily handled.

The semiconductor memory device of the present invention is not limited to the configuration of the embodiment, and various modifications can be considered.
There are at least two interface modules to be mounted, and it may be configured to function as at least two types of memory types.

It is explanatory drawing about the basic schematic structure of the semiconductor memory device which concerns on embodiment of this invention. It is a figure which shows the specific circuit structural example of the semiconductor memory device which concerns on this Embodiment. It is a block diagram which shows the structural example of the DRAM-IF module group which concerns on this Embodiment. 4 is a state transition diagram of the SDRAM. It is a state transition diagram of DDR-SDRAM. It is a figure which shows the structural example of the semiconductor memory device which provided the IF module here without dividing into a common sequence part and an exclusive module part. It is a figure which shows the state transition of the DRAM-IF module group which provided the common sequence part and the exclusive module part. FIG. 10 is an explanatory diagram illustrating an example of an operation state of the semiconductor memory device according to the embodiment; It is a figure for demonstrating the state transition of initialization. It is a figure for demonstrating the write state transition. It is a figure for demonstrating the state transition of the write with auto precharge. It is a figure for demonstrating the state transition of reading. It is a figure for demonstrating the state transition of the read with an auto precharge. It is a figure for demonstrating the state transition of an auto refresh. It is a block diagram which shows the structural example of the adaptive converter (Adaptive Converter) which concerns on this embodiment. It is a figure for demonstrating the write-in operation | movement in the 1st example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the read-out operation | movement in the 1st example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the write-in operation | movement in case the data mask exists in the 2nd example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the write-in operation | movement in the case of no data mask in the 2nd example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the read-out operation | movement in the 2nd example of the adaptive converter which concerns on this embodiment. It is a figure which shows the write-in and read-out pattern after conversion in the 3rd example of the adaptive converter which concerns on this embodiment. It is a figure which shows an example of the address conversion table in the 3rd example of the adaptive converter which concerns on this embodiment. It is a figure shown about the address read in the 3rd example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the write-in operation | movement in the 3rd example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the continuous address read-out operation | movement in the 3rd example of the adaptive converter which concerns on this embodiment. It is a figure for demonstrating the single address read-out operation | movement in the 3rd example of the adaptive converter based on this embodiment. It is a figure for demonstrating the 1st example of the semiconductor memory device (multi-IF memory device) which reduces a memory number. It is a figure for demonstrating the 2nd example of the semiconductor memory device (multi-IF memory device) which reduces a memory number. It is a figure which shows the relationship between the adaptive converter corresponding to a 2nd example, and a RAM array. It is a figure which shows an example of the timing chart of a 2nd example. It is a figure for demonstrating the 3rd example of the semiconductor memory device (multi-IF memory device) which reduces a memory number. It is explanatory drawing of the read / write cycle timing of SDR. FIG. 6 is an explanatory diagram of DDR read / write cycle timing. It is explanatory drawing of the operation | movement at the time of the SDR-IF module function of embodiment. It is explanatory drawing of the operation | movement at the time of the DDR-IF module function of embodiment. It is explanatory drawing of the mode operation | movement of the PLL part of embodiment. It is explanatory drawing of the mode operation | movement of the selector of embodiment. It is explanatory drawing of the mode operation | movement of IO buffer of embodiment. It is explanatory drawing of the mode operation | movement of IO buffer of embodiment. It is explanatory drawing of the mode operation | movement of IO buffer of embodiment. It is explanatory drawing of the mode operation | movement of IO buffer of embodiment. It is explanatory drawing of the mode operation | movement of IO buffer of embodiment. It is a block diagram of the other structural example of the semiconductor memory device of an embodiment. It is explanatory drawing of the operation state of the other structural example of the semiconductor memory device of embodiment. It is a block diagram of the further another structural example of the semiconductor memory device of the embodiment. It is explanatory drawing of the operation state of the further another structural example of the semiconductor memory device of embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1A ... Semiconductor memory device, 2 ... Interface part, 3 ... Memory array part, 21 ... Interface module group, 21-1 ... DRAM-interface (IF) module group, 210 ..Common sequence unit, 2101 ... command detection unit, 2102 ... common state transition unit, 2103 ... switch group, 211 ... dedicated module unit, 211-0, 21a ... SDR-IF module , 211-1, 21b ... DDR-IF module, 211-2, 21c ... DDR2-IF module, 211-n, 21e ... DDR (n) -IF module, 21-2, 21f ... · SRAM-IF module, 21-3, 21g ... DPRAM-IF module, 21-4, 21h ... FIFO-IF Joule, 22 ... IO buffer, 23 ... selectors, 24 ... PLL unit, 25 ... mode interpretation unit, 30 ... RAM array, 31 ... adaptive converter (Adaptive Converter).

Claims (12)

A memory array part in which a memory array to be accessed with a predetermined data bus width is formed;
An interface unit for performing an interface between the external device and the memory array unit;
A converter having a function of converting data and control signals between the interface unit and the memory array, and a converter having a conversion function according to the specifications of the memory array;
The interface part is
A plurality of interface modules respectively corresponding to a plurality of memory types and selectively applied to interface processing between the external device and the memory array unit;
A semiconductor memory device, wherein a data bus width in the interface unit is set to a data bus width wider than a data bus width set according to a predetermined memory type. The converter is
The semiconductor memory device according to claim 1, wherein division information of the memory array is obtained from a mode signal including interface type information to control access to the memory array, and data areas corresponding to different memory types in the memory array are distinguished. The converter is
The semiconductor memory device according to claim 1, further comprising a data width variable function for issuing a command and an address of the memory array based on information on access data of the memory array, and outputting the data width in a variable or non-variable manner. The interface part is
Interpreter that interprets the mode indicating the type of memory from the mode designation signal, identifies at least the burst length and bit width of the data, and outputs the identification result to the converter as access information of the memory array Have
The converter is
2. The semiconductor memory device according to claim 1, wherein a command and an address are issued to the memory array based on mode interpretation of the interpreter and burst length and bit width information, and the data width is variable or non-variable. 3. The converter is
5. The semiconductor memory device according to claim 4, wherein when the external data bus width is different from the data bus width of the memory array, the data width variable processing is performed. The converter is
When the external data bus width is 2 to the Nth power and a write command with a data mask is received, the write command is issued continuously, and only the corresponding data is written into the memory array by data mask control. 6. The semiconductor memory device according to 5. The converter is
When the external data bus width is the Nth power of 2 and when a write command without a data mask is received, a read command and a write command are issued, addressed data is read from the memory array, and the read data and 6. The semiconductor memory device according to claim 5, wherein writing is performed together with data to be written. The converter is
When the external data bus width is 2 to the Nth power and a read command is received, the data read from the memory array is converted from parallel data to serial data and output to the interface module corresponding to the memory type The semiconductor memory device according to claim 5. The converter is
When the external data bus width is not 2 to the Nth power and a write command is received, the data that is not the second power of N is replaced with a width of the second power of N, the burst length and bit width information, and the predetermined data The semiconductor memory device according to claim 5, wherein an address is issued based on the count information and the corresponding data is written to the memory array. The converter is
When the external data bus width is not 2 to the N-th power and a write command is received, the non-N-th power of 2 is converted from parallel to serial for each bit from the input, and a plurality of bits corresponding to predetermined data And sequentially replacing each of them in pairs and replacing them with the N-th power width, issuing an address based on the burst length and bit width information, and predetermined count information, and writing the corresponding data into the memory array. The semiconductor memory device described. The converter is
When the external data bus width is not 2 to the power of N and when a read command is received, if the read data of the memory array starts with data that is all contained in one block, the predetermined data is read from the read data. Are extracted, converted from serial to parallel, and expanded sequentially.
As the next data, the data block for the predetermined data spans two blocks, so the first data is held, converted from serial to parallel together with the second data block, and sequentially expanded The semiconductor memory device according to claim 10. The converter is
If the external data bus width is not 2 to the Nth power and a read command is received, the read data of the memory array is the first when the data block for the predetermined data spans two blocks. The semiconductor memory device according to claim 10, wherein the data is stored, converted together with the second data block from serial to parallel, sequentially expanded and read.

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