JP2009180854A - Wiring pattern, substrate device, method for forming slit in wiring pattern, method for designing slit in wiring pattern, apparatus and program therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring pattern in which a slit is formed with a larger opening area while suppressing increase in resistance. <P>SOLUTION: Slits S that transmit UV rays to a photosetting sealing member constituting a sealing section are formed along electric lines of force 48 perpendicular to equipotential lines 47 of a wiring pattern body LP1 formed on a glass substrate of a liquid crystal cell. Thus, slits S having an increased opening area are formed while suppressing increase in resistance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring pattern having a slit for transmitting light, a substrate device, a wiring pattern slit forming method, a substrate device, a wiring pattern slit designing method, a device therefor, and a program therefor.

  Liquid crystal display devices have various features such as thinness, light weight, and low power consumption, and are applied to various uses such as OA equipment, information terminals, watches, and televisions. In particular, a liquid crystal display element having a thin film transistor is used as a monitor for displaying a large amount of information such as a portable television or a computer because of its high responsiveness.

  In such a liquid crystal display device, a pair of glass substrates are arranged to face each other, a liquid crystal layer is interposed between the glass substrates, and the vicinity of the outer peripheral edge of the glass substrate is bonded to each other by an adhesive portion (seal portion) made of an adhesive. Thus, the liquid crystal layer is sealed between the glass substrates.

  In recent years, in the liquid crystal dropping method that has been frequently applied to mass production, a photo-curing adhesive, that is, an ultraviolet curable adhesive (hereinafter referred to as a UV seal) is in contact with a liquid crystal material in an uncured state. A large amount of components may be eluted in the liquid crystal layer, and when these impurities and constituent components are eluted in the liquid crystal, a decrease in voltage holding ratio, alignment failure, etc. are induced, and the display quality is remarkably deteriorated.

  In order to reduce the elution of such impurities, materials and UV irradiation apparatuses that cause a sufficient photocuring reaction have been studied. However, in the current liquid crystal display element, a wiring pattern is formed under the UV seal. There is. Since such a wiring pattern may have a width of about 200 to 300 μm, when such a wiring pattern crosses the UV seal, the UV seal becomes uncured by being shielded by the wiring pattern. There is a possibility that elution of the UV seal into the liquid crystal layer may occur.

  On the other hand, although there is a case where light is irradiated from the counter substrate side provided with the color filter layer, a frame-shaped light shielding pattern for preventing light leakage is often formed at a corresponding place on the counter substrate side. However, there is a problem that sufficient exposure for curing is not easy.

Therefore, a configuration is known in which a slit for transmitting light is provided in a wiring pattern or the like crossing the UV seal (see, for example, Patent Document 1).
JP 2001-2222017 A

  The slit provided in the wiring pattern is desired to have an opening area as large as possible in order to efficiently irradiate the UV seal with light. However, when the opening area of the slit is increased, the resistance value of the wiring pattern is increased.

  The present invention has been made in view of the above points, and is capable of forming a slit having a large opening area while suppressing an increase in resistance value, a wiring board device, a wiring pattern slit forming method, a wiring board device, and a wiring pattern. An object of the present invention is to provide a slit design method, an apparatus therefor, and a program therefor.

  The present invention relates to a wiring pattern formed of a conductor on a substrate, which is formed along a wiring pattern main body and a current stream line orthogonal to an equipotential line of the wiring pattern main body and allows light to pass therethrough. It is equipped with.

  In addition, the present invention is a wiring pattern slit forming method including a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate, which is orthogonal to the equipotential lines of the wiring pattern body. A slit forming step of forming the slit along a current flow line is provided.

  Furthermore, the present invention is a wiring pattern slit design method comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate, and the virtual wiring pattern simulating the wiring pattern body A virtual slit forming step of forming a virtual slit for simulating the slit along a virtual stream line of a current orthogonal to a virtual equipotential line of the main body is provided.

  Then, a slit is formed along the current stream line orthogonal to the equipotential line of the wiring pattern body formed of the conductor on the substrate.

  Furthermore, the present invention is a wiring pattern slit designing apparatus comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate, and a virtual wiring pattern simulating the wiring pattern body Virtual slit forming means for forming a virtual slit for simulating the slit along a virtual stream line of a current orthogonal to a virtual equipotential line of the main body is provided.

  The present invention is also a slit design program for a wiring pattern having a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate, the virtual wiring pattern simulating the wiring pattern body A virtual slit forming step of forming a virtual slit for simulating the slit along a virtual streamline of a current orthogonal to the virtual equipotential line.

  Then, a virtual slit that simulates the slit is formed along the virtual streamline of the current that is orthogonal to the virtual equipotential line of the virtual wiring pattern body that simulates the wiring pattern body.

  According to the present invention, it is possible to form a slit having a large opening area while suppressing an increase in resistance value.

  The configuration of the first embodiment of the present invention will be described below with reference to the drawings.

  3 and 4, reference numeral 11 denotes a liquid crystal panel which is a liquid crystal display device as a display device. The liquid crystal panel 11 is a liquid crystal display which is a display element as a substantially rectangular plate-like substrate device used for, for example, a cellular phone. It is a transmissive type comprising an element, that is, a liquid crystal cell 12 that is an LCD (Liquid Crystal Display) cell and a backlight 13 that is a planar light source device that irradiates the back surface of the liquid crystal cell 12 with planar light. .

  The liquid crystal cell 12 is, for example, an active matrix type capable of color display. An array substrate 16 as a substrate and a counter substrate 17 as a substrate are arranged to face each other, and a light modulation layer is interposed between the substrates 16 and 17. The polarizing plate (not shown) is attached to each of the substrates 16 and 17, and the substrates 16 and 17 are bonded to each other by a seal portion 19 as an adhesive portion, and are fixedly bonded. A rectangular display region 20 in which pixels P for displaying an image are formed in a matrix is formed in a substantially central portion.

  The array substrate 16 includes, for example, a glass substrate 25 that is a light-transmitting substrate body. On the main surface of the glass substrate 25 on the liquid crystal layer 18 side, a thin film is formed by a conductor such as a metal member. The scanning lines (gate wirings) 31 and the signal lines (source wirings) 32, which are a plurality of wirings (metal wirings), are arranged in a lattice shape so as to be substantially orthogonal to each other to form a wiring pattern LP. A thin film transistor (TFT) 33, which is a switching element, is provided at each crossing position of the signal line 32 and the signal line 32, and an alignment film (not shown) for aligning liquid crystal molecules of the liquid crystal layer 18 is formed so as to cover them.

  The thin film transistor 33 has a gate electrode connected to the scanning line 31, a source electrode connected to the signal line 32, a drain electrode connected to a pixel electrode (not shown), and a gate driver 36 that is a scanning line driving circuit. Is applied to the gate electrode via the scanning line 31, and the switching is controlled, and a voltage is applied to the pixel electrode corresponding to the signal input from the source driver 37 which is a signal line driving circuit via the signal line 32. By applying the voltage, each pixel P is turned on / off independently.

  The counter substrate 17 includes a glass substrate 45 that is a light-transmitting substrate body, and a color filter layer, a counter electrode, an alignment film, and the like (not shown) are sequentially stacked on the glass substrate 45.

  The color filter layer is formed in a thin film shape for each pixel P by a synthetic resin or the like corresponding to the three primary colors of RGB, for example, and has, for example, a stripe shape in plan view.

  The counter electrode is formed by a sputtering method or the like with a transparent conductive material such as ITO at a position corresponding to the pixel electrode in the display region 20.

  The liquid crystal layer 18 is a light modulation layer formed of a predetermined liquid crystal material.

  Further, the seal portion 19 is formed by a seal member (UV seal) which is, for example, an ultraviolet (UV) curable resin as a photocurable resin, and is formed in a frame shape (frame shape) surrounding the display region 20. In addition, a part of the wiring pattern LP overlaps the seal portion 19.

  In the present embodiment, the liquid crystal layer 18 is disposed between the substrates 16 and 17 by a liquid crystal dropping method. That is, the seal portion 19 is a state in which an uncured seal member is applied in a frame shape on the glass substrate 25, and the liquid crystal material dropped on the region surrounded by the seal member is sandwiched between the glass substrates 25 and 45. It is formed by irradiating UV light to the uncured seal member and curing.

  Here, as shown in FIG. 1, a plurality of wiring patterns LP are formed in a wiring pattern main body LP1 formed of a conductor and a portion overlapping this seal portion 19 of the wiring pattern main body LP1, and a sealing portion 19 (FIG. 2). And a slit S that transmits light for curing (UV light).

  The slit S is formed in a rectangular shape in plan view, and is longitudinal along an electric force line 48 that is a current stream line orthogonal to the equipotential line 47 between the resistance calculation electrodes E and E of the wiring pattern body LP1. Respectively.

  The slits S of the wiring pattern LP are designed by a computer system that is a control unit including CAD software that is pattern layout software as design means used for pattern design of the substrates 16 and 17 of the liquid crystal cell 12 and the like. The computer includes a hard disk as storage means, a memory as temporary storage means, and CAD software, and wiring pattern forming means for forming a virtual wiring pattern LPa (virtual wiring pattern main body LP1a) simulated on the CAD software And a virtual pattern that simulates the pattern formed on the substrates 16 and 17 having the function of the virtual slit forming means for forming the virtual slit Sa simulating the slit S on the CAD software on the CAD software. A virtual equipotential line 47a (virtual electric force line 48a which is a virtual stream line) on the virtual wiring pattern main body LP1a based on the virtual pattern creating means to be formed and the shape, material or length of the virtual wiring pattern main body LP1a CPU having a function of virtual equipotential line calculation means (virtual electric field line calculation means) etc. Control means, respectively.

  Next, the slit design method and creation method of the wiring pattern of the first embodiment will be described. In the present embodiment, the wiring pattern LP is created on the array substrate 16 side, but the same can be applied to the case where it is created on the counter substrate 17 side.

  First, a simulated pattern that simulates the pattern of the glass substrate 25 including the wiring pattern LP is designed on CAD software (pattern design process).

  In this pattern design process, as shown in FIG. 2, the virtual wiring pattern main body LP1a simulating the wiring pattern main body LP1 arranges virtual electrodes Ea for measuring a resistance value or the like between desired positions. The virtual equipotential lines 47a between the electrodes Ea and the virtual electric force lines 48a orthogonal to these virtual equipotential lines 47a are simulated, and elongated rectangular virtual slits Sa are sequentially arranged along the virtual electric force lines 48a. (Virtual slit forming process).

  As a result, the wiring pattern LP having the slits S is designed on the computer.

  Then, a photomask is created on the basis of the virtual wiring pattern LPa having the virtual slit Sa designed on the computer, and sputtering or etching is appropriately repeated using this photomask to actually form the wiring pattern LP having the slit S. Then, it is formed on the main surface of the glass substrate 25 (slit forming step).

  As described above, according to the first embodiment, the wiring pattern body LP1 formed of the conductor on the glass substrate 25 is moved along the electric force lines 48 perpendicular to the equipotential lines 47 of the wiring pattern LP. The slit S is formed. Specifically, a virtual slit Sa for simulating the slit S is formed along a virtual electric force line 48a orthogonal to the virtual equipotential line 47a of the virtual wiring pattern body LP1a simulating the wiring pattern body LP1 by the slit design means. Then, the wiring pattern LP having the slit S designed in this way is formed on the glass substrate 25.

  As a result, it is possible to form the slit S having a large opening area while suppressing an increase in the resistance value of the wiring pattern LP.

  Further, by providing such a slit S in a portion overlapping the seal portion 19 of the wiring pattern body LP1, it overlaps with the wiring pattern LP of the sealing member when the uncured sealing member is irradiated with UV light and cured. The UV light is irradiated to the sealing member through the slit S even in the part where the sealing member 19 is surely cured and the sealing portion 19 is formed, so that the liquid crystal material is dropped on the region surrounded by the uncured sealing member. Even when the liquid crystal cell 12 is manufactured using the liquid crystal dropping method for curing the seal member, the seal member constituting the seal portion 19 is not sufficiently cured and does not elute into the liquid crystal layer 18, Such elution can also prevent the display quality of the liquid crystal cell 12 from deteriorating.

  Next, a second embodiment will be described with reference to FIGS. In addition, about the structure and effect | action similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the second embodiment, the opening area of the slit S is set corresponding to the current density on the wiring pattern LP in the first embodiment.

  That is, the slit S has a relatively small opening area at a position where the current density of the wiring pattern body LP1 is large, and has a relatively large opening area at a position where the current density of the wiring pattern body LP1 is small. The total sum of the opening areas of all the slits S is preferably constant.

  In FIG. 5, between the electrodes E and E, the opening area of the slit S along the electric field lines 48 on the upper side and the lower side in the figure is relatively large, and the electric field lines 48 in the upper and lower centers in the figure. The opening area is set so as to decrease sequentially along the slits S along. In addition, each slit S is set so that the longitudinal dimension is substantially equal, and the opening area varies depending on the width dimension.

  When creating the wiring pattern LP having such a slit S, as shown in FIG. 6, in the virtual slit forming step, a virtual current density on the virtual wiring pattern body LP1a is calculated, and this current density is calculated. The width dimension of the virtual slit Sa is set corresponding to the above, and the wiring pattern in which the slit S is formed on the glass substrate 25 in the slit forming process corresponding to the virtual wiring pattern LPa in which the virtual slit Sa is thus formed. LP is formed.

  As a result, it is possible to form the slit S having a large opening area while further suppressing an increase in the resistance value of the wiring pattern LP, and the same effects as those in the first embodiment can be obtained.

  In each of the above embodiments, the shape of the slit S (virtual slit Sa) is an arbitrary shape such as a curved shape along the electric force line 48 (virtual electric force line 48a). Is possible.

  Further, the substrate device is not limited to the liquid crystal cell 12, but may be any device as long as it has a wiring pattern formed of a member that is cured by light and bonds a pair of substrates and a conductor. it can.

  Furthermore, each of the pattern forming process and the virtual slit forming process of the above design method may be a wiring pattern slit design program that is programmed as each step operable by a computer. It is also possible to record on a disk or other medium so as to be readable by a computer, and automatically operate the computer.

  FIG. 7 shows Example 1 corresponding to the first embodiment, Example 2 corresponding to the second embodiment, and a comparative example corresponding to the conventional example.

  In the comparative example shown in FIG. 7 (c), the straight line portions LPb and LPb connected to the electrodes E and E are continuously bent to the side (right side in the drawing) at a substantially right angle, that is, each straight line portion. With respect to the substantially vertically symmetrical wiring pattern body LP1 provided with a bent portion LPc inclined at a predetermined angle, for example, approximately 45 °, with respect to LPb and LPb, it has a longitudinal direction in a certain direction, here the vertical direction in the figure. An elongated rectangular slit S0 is formed.

  In Example 1 shown in FIG. 7A, the slits S having the same opening area as the slits S0 are arranged along the lines of electric force of the wiring pattern body LP1, that is, the straight portions LPb and LPb are the same as in the comparative example. In the bent portion LPc, the bent portion LPc is arranged along the bent shape of the bent portion LPc. In the second embodiment shown in FIG. The opening area of S is variably set corresponding to the current density of the wiring pattern main body LP1, for example, the slit S located in the bent portion LPc from the left side (inside the bent shape of the bent portion LPc) to the right side (of the bent portion LPc). The opening area is set so as to gradually increase toward the outer side of the bent shape. The opening area of Example 2 is equal to the opening area of Example 1.

  And when the resistance value between the both ends of a wiring pattern was measured about the said Example 1, Example 2, and a comparative example, when resistance value was set to 100% in a comparative example, the resistance value of Example 1 was 96.37%, The resistance value of Example 2 was 95.64%, and each resistance value could be reduced.

It is an explanatory top view showing the slit formation method of the wiring pattern of a 1st embodiment of the present invention. It is explanatory drawing which shows the slit design method of a wiring pattern same as the above. It is a longitudinal cross-sectional view which shows the board | substrate apparatus which formed the slit with the slit formation method of a wiring pattern same as the above. It is a circuit diagram which shows a board | substrate apparatus same as the above. It is explanatory drawing which shows the slit formation method of the wiring pattern of the 2nd Embodiment of this invention. It is explanatory drawing which shows the slit design method of a wiring pattern same as the above. (a) is an explanatory plan view showing Example 1 of the slit forming method of the wiring pattern, (b) is an explanatory plan view showing Example 2 of the slit forming method of the wiring pattern, and (c) corresponds to the conventional example. It is an explanatory plan view showing a comparative example.

Explanation of symbols

12 Liquid crystal cell as a substrate device
Array substrate which is 16 substrate
17 Substrate that is the substrate
47 equipotential lines
47a Virtual equipotential lines
48 Electric field lines that are streamlines
48a Virtual electric lines of force that are virtual streamlines
LP wiring pattern
LPa virtual wiring pattern
LP1 wiring pattern body
LP1a Virtual wiring pattern body S Slit
Sa virtual slit

Claims (11)

A wiring pattern formed of a conductor on a substrate,
A wiring pattern body;
A wiring pattern comprising: a slit formed along a current flow line orthogonal to an equipotential line of the wiring pattern main body and capable of transmitting light. An opening area of the slit is set corresponding to a current density on the wiring pattern body. A pair of substrates disposed opposite each other;
Formed of a member that is cured by light, and an adhesive portion that bonds the pair of substrates by curing of the member;
3. A substrate device comprising: the wiring pattern according to claim 1 or 2 formed on at least one of the pair of substrates. A wiring pattern slit forming method comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate,
A slit forming method for forming a wiring pattern, comprising: a slit forming step of forming the slit along a current flow line orthogonal to an equipotential line of the wiring pattern main body. The wiring pattern slit forming method according to claim 4, wherein, in the slit forming step, an opening area of the slit is set corresponding to a current density on the wiring pattern main body. A wiring pattern slit design method comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate,
A virtual slit forming step of simulating the slit along a virtual streamline of a current orthogonal to a virtual equipotential line of the virtual wiring pattern body simulating the wiring pattern body; Wiring pattern slit design method. The wiring pattern slit designing method according to claim 6, wherein, in the virtual slit forming step, an opening area of the virtual slit is set corresponding to a virtual current density on the virtual wiring pattern body. A wiring pattern slit designing device comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate,
Virtual slit forming means for simulating the slit along the virtual streamline of the current orthogonal to the virtual equipotential line of the virtual wiring pattern body simulating the wiring pattern body. Wiring pattern slit design device. 9. The wiring pattern slit designing apparatus according to claim 8, wherein the virtual slit forming means sets an opening area of the virtual slit corresponding to a virtual current density on the virtual wiring pattern body. A wiring pattern slit design program comprising a slit for transmitting light to a wiring pattern body formed of a conductor on a substrate,
A virtual slit forming step of forming a virtual slit for simulating the slit along a virtual streamline of a current orthogonal to a virtual equipotential line of a virtual wiring pattern simulating the wiring pattern body; Slit design program for wiring patterns. The wiring pattern slit design program according to claim 10, wherein, in the virtual slit forming step, an opening area of the virtual slit is set corresponding to a virtual current density on the virtual wiring pattern body.

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