JP2009177303A - Video signal processor, and video signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal processor which can enhance stability of clock recovery. <P>SOLUTION: A receive buffer 1 stores received TS packets. A GAP restore section 2 restores time interval between time points when the TS packets stored in a receive buffer means are transferred. A control section 3 calculates the interval between time points when the TS packets stored in the receive buffer 1 are transferred, from a PCR value included in the TS packet and the number of TS packets included between the PCRs, and controls transfer of TS packets at the GAP restore section 2. Consequently, transfer rate of TS packets can be made constant substantially, and stability of clock recovery can be enhanced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for processing a video signal by receiving a transport stream (TS), and more particularly, processes a video signal by improving the stability of clock recovery by PCR (Program Clock Reference). The present invention relates to a video signal processing apparatus and a video signal processing method.

  In recent years, systems for transmitting and receiving video signals via the Internet network have become widespread. In a set top box (STB) used in such a system, a communication protocol using MPEG (Moving Picture Experts Group) 2-TS (Transport Stream) is often used for transmission and reception of video signals.

  FIG. 5 is a diagram showing a packet structure of MPEG2-TS. MPEG2-TS is composed of a plurality of transport packets (hereinafter also referred to as TS packets). Each TS packet has a size of 188 bytes or 204 bytes and includes an adaptation field control and an adaptation field.

  The adaptation field control is information indicating whether or not the TS packet includes an adaptation field. Therefore, depending on the information of the adaptation field control, some TS packets do not include the adaptation field.

  In the adaptation field, additional information of the corresponding TS packet is stored. This adaptation field includes a PCR flag and an optional field. This PCR flag is information indicating whether or not PCR is included in the optional field.

  When the PCR flag is “1”, it indicates that the optional field includes PCR. When the PCR flag is “0”, it indicates that the optional field does not include PCR. Therefore, depending on the value of the PCR flag, there is an adaptation field that does not include PCR in the optional field.

  The PCR is time information for recovering the system clock of the encoding device that has generated the transport stream by the decoding device that receives the transport stream. The PCR is also a clock adjustment value for matching the frequency of the system clock of the encoding device that generated the transport stream with the frequency of the system clock generated by the decoding device that receives the transport stream.

  That is, the frequency of the system clock of the encoding device that generated the transport stream does not exactly match the system clock of the decoding device that receives the transport stream. Therefore, in order for the decoding device to decode the same number of frames as the number of frames generated by the encoding device, it is necessary for the decoding device to recover and match the system clock of the encoding device.

  When transmitting a transport stream, the encoding device adds a counter value counted by the system clock of the encoding device as a PCR to a TS packet at a predetermined time interval among a plurality of TS packets included in the transport stream to be transmitted. . On the decoding device side, the system clock of the encoding device is recovered using this PCR.

  In the MPEG2 standard, a method of calculating the clock rate on the encoding device side from the arrival time of the PCR on the decoding device side and the number of bits of the transport stream received between the PCRs is used. Specifically, the time stamp value generated using the system clock of the decoding device is compared with the PCR value received from the encoding device, and the system clock on the decoding device side is controlled so that the difference becomes zero. . As technologies related to this, there are inventions disclosed in the following Patent Documents 1 to 3.

  In the delay fluctuation absorbing method disclosed in Patent Document 1, time-series packets supplied from a receiving apparatus are sequentially stored in a buffer and simultaneously supplied to a reference time information detector, and also input to an input byte counter in units of 1 byte. Is added. The reference time information detector reads the byte value a, detects reference time information b from the packet data, and stores them in the reference time / position memory. The output timing controller supplies the buffer packets to the decoder at intervals determined by the byte value a, the reference time information b, the output byte counter byte value Bn, the transmission time Cn, and the packet length of the packet.

  The invention disclosed in Patent Document 2 is a jitter suppression device that reduces jitter of time information included in an input digital signal, and includes a time information extraction unit that extracts time information from the input digital signal, and a time information extraction unit. Time information storage means for storing the extracted time information, data storage means for storing the input digital signal, clock generation means, clock measurement means for measuring the clock from the clock generation means, multiplexed to the input digital signal Data generating means, multiplexing means for multiplexing the input digital signal stored in the data storage means and the data generated by the data generating means, and correcting time information contained in the multiplexed data multiplexed by the multiplexing means Time information correction means, time information storage means, data storage means, multiplexing means and time And control means for controlling the information correction means.

In the clock recovery circuit disclosed in Patent Document 3, based on the relationship between the absolute value of the sum Σe of error signals output during a predetermined period Ta and the jitter width J, is the input signal and the recovery clock synchronized? If it is in the synchronized state, the gain is changed with the stable gain Ga for the jitter width J as a target value, and if not, the gain is changed with the allowable gain Gb for the jitter width J as the target value. To do.
JP 2002-152273 A JP 2005-277816 A JP 2001-028537 A

  When TS packets are distributed using IP packets, the reception time of TS packets on the decoding device side varies greatly due to storage of multiple transport streams in the IP packet and variations in the IP packet transmission rate on the encoding device side. Become.

  Therefore, in the method of comparing the time stamp value generated using the system clock of the decoding device described above and the PCR value received from the coding device to recover the clock on the coding device side, the arrival time variation (jitter) The larger the is, the higher the control pull-in range, that is, the wider the range in which the clock changes must be followed. Therefore, the stability of the recovered clock is low, and the fluctuation of the video synchronization signal generated from the recovered clock increases.

  In order to increase the stability of the recovered clock using PCR, a method of temporarily storing the received TS packet in a buffer and sending it to the decoder at the original interval may be used. For example, the time stamp at the time of transmission is separately stored in the TS packet on the encoding device side, the time stamp is referred to on the decoding device side, and the TS packet is extracted at that timing.

  When such a method is used, a mechanism for adding a time stamp separately on the encoding device side, extracting the time stamp added on the decoding device side, and controlling the timing for extracting the TS packet is required. It is desirable to increase the stability of the recovered clock without adding such a time stamp separately. However, even if the inventions disclosed in Patent Documents 1 to 3 described above are used, it is difficult to realize this.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a video signal processing apparatus and a video signal processing method capable of improving the stability of clock recovery.

  According to an aspect of the present invention, the video signal processing device includes a reception buffer unit that accumulates received transport packets, and a restoration unit that restores a time interval at the time of transfer of the transport packets accumulated in the reception buffer unit. The control means for controlling the transfer of transport packets in the restoration means by calculating the time interval of transport packet transfer accumulated in the reception buffer means, and the video signal is decoded based on the transport packets transferred from the restoration means Decoding means.

  The control means calculates the transport packet transfer time interval accumulated in the reception buffer means and controls the transport packet transfer in the restoration means, so that the transfer rate of the transport packet can be made substantially constant, It is possible to improve the stability of clock recovery.

  Preferably, the control means determines the time interval of transport packet transfer from the program time base reference value included in the transport packet and the number of transport packets arranged between the transport packets having the program time base reference value. Calculate and control transport packet transfer in the restoration means.

  Therefore, the time interval for transport packet transfer can be easily calculated.

  More preferably, the restoring means sets a time interval calculated by the control means and counts according to the clock signal, and one unit output from the reception buffer means according to the value of the counting means. Gate means for transferring the transport packet to the decoding means, and the control means controls the frequency of the clock signal so that the difference value between the transport packet accumulation amount in the reception buffer means and the predetermined value becomes zero. Output to the counting means.

  Therefore, the transfer rate of the transport packet can be stabilized, and the stability of clock recovery can be improved.

  More preferably, the restoring means sets a time interval calculated by the control means and counts according to the clock signal, and one unit output from the reception buffer means according to the value of the counting means. Gate means for transferring the transport packet to the decoding means, and the control means counts by increasing / decreasing the time interval so that the difference value between the storage amount of the transport packets in the reception buffer means and the predetermined value becomes zero. Output to the means.

  Therefore, the transfer rate of the transport packet can be stabilized, and the stability of clock recovery can be improved.

  According to another aspect of the present invention, a video signal processing method includes a step of storing a received transport packet, a step of calculating a time interval at the time of transfer of the stored transport packet, and a calculated time interval. And transferring the transport packet, and decoding the video signal based on the transferred transport packet.

  Since the transport packet is transferred at the calculated time interval, the transfer rate of the transport packet can be made substantially constant, and the stability of clock recovery can be improved.

  According to an aspect of the present invention, the control means calculates the transport packet transfer time interval accumulated in the reception buffer means and controls the transport packet transfer in the restoration means. Can be made substantially constant, and the stability of clock recovery can be improved.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a video signal processing apparatus according to the first embodiment of the present invention. The video signal processing device includes a reception buffer 1, a GAP restoration unit 2, a control unit 3, a decoder 4, a PCR clock recovery unit 5, and a video signal control unit 6.

  The reception buffer 1 sequentially stores TS packets received via a network such as the Internet, and outputs the packet accumulation amount to the control unit 3 as a buffer level value. In addition, the reception buffer 1 extracts the PCR included in the TS packet and outputs it to the control unit 3, calculates the number N of TS packets included between the PCRs, and outputs it to the control unit 3. In addition, the reception buffer 1 sequentially transfers the TS packets stored in response to the request from the GAP restoration unit 2 to the decoder 4 via the GAP restoration unit 2.

  The GAP restoration unit 2 receives the packets gap value and the clock signal output from the control unit 3 and controls the transfer timing of the TS packets accumulated in the reception buffer 1. Details of the GAP restoration unit 2 will be described later.

  The control unit 3 calculates a packets gap value from the PCR value received from the reception buffer 1 and the number of TS packets included between the PCRs, and outputs the packet gap value to the GAP restoration unit 2. The packet gap value is a PCR counter value for one TS packet, that is, a value indicating how many clocks of the clock generated by the control unit 3 correspond to each TS packet. Calculated.

packets gap value = (1st PCR value−2nd PCR value) / N (1)
In addition, the control unit 3 refers to the buffer level value received from the reception buffer 1, controls the clock signal, and outputs it to the GAP restoration unit 2. Details of the control unit 3 will be described later.

  The decoder 4 decodes the video signal and the audio signal included in the TS packet in synchronization with the system clock output from the PCR clock recovery unit 5 and outputs the decoded video signal and audio signal to the video signal control unit 6.

  The PCR clock recovery unit 5 compares the time stamp value generated using the system clock with the PCR value received from the GAP restoration unit 2, and controls the system clock so that the difference becomes 0, and the decoder 4 and the video signal control unit 6.

  The video signal control unit 6 receives the video signal decoded by the decoder 4, and synchronizes with the system clock output from the PCR clock recovery unit 5 in the horizontal sync (Hsync) signal of the CVBS (Composite Video Base Band Signal), the vertical It generates and outputs various control signals for synchronization (Vsync) signal, video (S_video) signal, and HDMI (High-Definition Multimedia Interface).

  FIG. 2 is a diagram illustrating an example of an internal configuration of the GAP restoration unit 2 illustrated in FIG. The GAP restoration unit 2 includes a decrement counter 21 and a gate 22. The decrement counter 21 loads a packets gap value given from the control unit 3 at the time of initial setting, and starts decrementing in synchronization with the clock signal from the control unit 3. At this time, the gate 22 is closed.

  When the value of the decrement counter 21 becomes “0”, the gate 22 is opened to transfer one TS packet to the decoder 4 and the decrement counter 21 is loaded with the packets gap value again to start decrementing. . The above process is repeated, and N TS packets are sequentially transferred to the decoder 4 in a cycle corresponding to the packets gap value.

  FIG. 3 is a diagram illustrating an example of an internal configuration of the control unit 3 illustrated in FIG. 1. The controller 3 includes an adder 31, a DAC (Digital Analog Converter) 32, an LPF (Low Pass Filter) 33, and a VCO (Voltage Control Oscillator) 34. The adder 31 calculates a difference value by adding the buffer level value and (−INIT_buf_level value). The INIT_buf_level value is a predetermined value, for example, a value that is half the capacity of the reception buffer 1 is set.

  Control is performed so that TS packets are always accumulated in the reception buffer 1 by the value of the INIT_buf_level value. That is, the frequency of the clock signal is controlled so that the difference value calculated by the adder 31 becomes “0”.

  The DAC 32 generates an analog signal having a voltage value corresponding to the difference value output from the adder 31 and outputs the analog signal to the LPF 33. For example, when the difference value output from the adder 31 is “0”, the DAC 32 outputs a voltage of 1V. When the difference value output from the adder 31 is a positive value, the DAC 32 outputs a voltage larger than 1 V according to the value. When the difference value output from the adder 31 is a negative value, the DAC 32 outputs a voltage smaller than 1 V according to the value.

  The LPF 33 removes the high frequency component of the analog signal output from the DAC 32 and outputs only the low frequency component of the analog signal output from the DAC 32.

  The VCO 34 generates and outputs a clock signal having a frequency corresponding to the voltage value of the analog signal output from the LPF 33. As described above, when the difference value output from the adder 31 is “0”, if a voltage of 1 V is output from the DAC 32, then the VCO 34 generates and outputs a clock signal of a predetermined frequency. When a voltage having a value larger than 1V is output from the DAC 32, a clock signal having a frequency higher than a predetermined frequency is generated and output according to the value. Further, when a voltage having a value smaller than 1V is output from the DAC 32, a clock signal having a frequency smaller than a predetermined frequency is generated and output according to the value.

  In this way, when the accumulation amount of the reception buffer 1 becomes larger than the predetermined value, the frequency of the clock signal is increased so that the transfer of the TS packet becomes faster, and when the accumulation amount of the reception buffer 1 becomes smaller than the predetermined value, Control is performed so that the frequency of the clock signal is lowered so that the transfer of the TS packet becomes slow, and the transfer rate of the TS packet becomes almost constant.

  As described above, according to the video signal processing apparatus in the present embodiment, the control unit 3 calculates the packet gap value according to the PCR value included in the TS packet, and provides the packet gap value to the GAP restoration unit 2 to receive the reception buffer. Since the clock signal is generated and output to the GAP restoration unit 2 so that the accumulated amount of TS packets in 1 is constant, the variation (jitter) in the arrival time of TS packets can be suppressed, and the PCR clock The stability of clock recovery in the recovery unit 5 can be improved.

(Second Embodiment)
The schematic configuration of the video signal processing apparatus and the internal configuration of the GAP restoration unit in the second embodiment of the present invention are the schematic configuration of the video signal processing apparatus and the GAP restoration in the first embodiment shown in FIGS. The internal configuration of the unit 2 is the same. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  In the first embodiment of the present invention, the stability of the clock recovery in the PCR clock recovery unit 5 is improved by keeping the packets gap value constant and changing the frequency of the clock signal. In the second embodiment of the present invention, the stability of clock recovery in the PCR clock recovery unit 5 is improved by making the frequency of the clock signal constant and changing the packets gap value.

  FIG. 4 is a diagram illustrating an example of an internal configuration of the control unit 3 according to the second embodiment of the present invention. The control unit 3 includes an adder 31 and an up / down counter 35. The adder 31 calculates a difference value by adding the INIT_buf_level value and (−buffer level value). The INIT_buf_level value is a predetermined value, for example, a value that is half the capacity of the reception buffer 1 is set.

  Control is performed so that TS packets are always accumulated in the reception buffer 1 by the value of the INIT_buf_level value. That is, the value of the up / down counter 35 is increased or decreased so that the difference value calculated by the adder 31 becomes “0”.

  The up / down counter 35 sets a packets gap value shown in Expression (1) at the time of initial setting. Then, the value of the up / down counter 35 is updated at a predetermined cycle as follows. When the difference value output from the adder 31 is a positive value, the up / down counter 35 increments the held value. When the difference value output from the adder 31 is a negative value, the up / down counter 35 decrements the held value.

  In this way, when the accumulation amount of the reception buffer 1 becomes larger than the predetermined value, the packets gap value is decreased so that the transfer of the TS packet becomes faster, and when the accumulation amount of the reception buffer 1 becomes smaller than the predetermined value, the TS The packet gap value is increased so that packet transfer is delayed, and control is performed so that the transfer rate of TS packets is substantially constant.

  As described above, according to the video signal processing device of the present embodiment, the control unit 3 increases or decreases the packets gap value so that the accumulated amount of TS packets in the reception buffer 1 is constant, and the GAP restoration unit 2 As a result of the output, the variation (jitter) in the arrival time of TS packets can be suppressed, and the stability of clock recovery in the PCR clock recovery unit 5 can be improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows schematic structure of the video signal processing apparatus in the 1st Embodiment of this invention. It is a figure which shows an example of an internal structure of the GAP decompression | restoration part 2 shown in FIG. It is a figure which shows an example of the internal structure of the control part 3 shown in FIG. It is a figure which shows an example of the internal structure of the control part 3 in the 2nd Embodiment of this invention. It is a figure which shows the packet structure of MPEG2-TS.

Explanation of symbols

  1 reception buffer, 2 GAP restoration unit, 3 control unit, 4 decoder, 5 PCR clock recovery unit, 6 video signal control unit, 21 decrement counter, 22 gate, 31 adder, 32 DAC, 33 LPF, 34 VCO, 35 up Down counter.

Claims (5)

Receiving buffer means for storing received transport packets;
Restoring means for restoring a time interval at the time of transfer of transport packets stored in the reception buffer means;
Control means for calculating a time interval of transport packet transfer accumulated in the reception buffer means and controlling transport packet transfer in the restoration means;
A video signal processing apparatus including decoding means for decoding the video signal based on the transport packet transferred from the restoration means;   The control means calculates a transport packet transfer time interval from a program time base reference value included in the transport packet and the number of transport packets arranged between transport packets having the program time base reference value. The video signal processing apparatus according to claim 1, wherein transfer of transport packets in said restoration means is controlled. The restoration means has a time interval calculated by the control means, and count means for counting according to a clock signal;
Gate means for transferring one transport packet output from the reception buffer means to the decoding means in accordance with the value of the counting means,
3. The control means according to claim 2, wherein the control means controls the frequency of the clock signal so that a difference value between a storage amount of transport packets in the reception buffer means and a predetermined value becomes 0 and outputs the clock signal to the counting means. Video signal processing device. The restoration means includes a counting means for setting a time interval calculated by the control means and counting according to a clock signal;
Gate means for transferring one transport packet output from the reception buffer means to the decoding means in accordance with the value of the counting means,
3. The video signal according to claim 2, wherein the control means outputs the video signal to the counting means by increasing or decreasing the time interval so that a difference value between an accumulation amount of transport packets in the reception buffer means and a predetermined value becomes 0. 4. Processing equipment. Accumulating received transport packets;
Calculating a time interval during transfer of the accumulated transport packet;
Transferring transport packets at the calculated time interval;
Decoding a video signal based on the transferred transport packet.

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