JP2009177197A5 - - Google Patents
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- Publication number
- JP2009177197A5 JP2009177197A5 JP2009081042A JP2009081042A JP2009177197A5 JP 2009177197 A5 JP2009177197 A5 JP 2009177197A5 JP 2009081042 A JP2009081042 A JP 2009081042A JP 2009081042 A JP2009081042 A JP 2009081042A JP 2009177197 A5 JP2009177197 A5 JP 2009177197A5
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- JP
- Japan
- Prior art keywords
- main surface
- mounting portion
- back surface
- lead
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 18
- 238000007789 sealing Methods 0.000 claims 9
- 239000000725 suspension Substances 0.000 claims 8
- 230000000875 corresponding Effects 0.000 claims 3
- 240000004282 Grewia occidentalis Species 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Claims (5)
前記半導体チップの主面が同一方向を向くように前記半導体チップが搭載された主面と、前記主面とは反対側にある裏面と、を有するチップ搭載部と、
主面と、前記主面とは反対側にある裏面とを有し、前記チップ搭載部に連結された複数の吊りリードと、
主面と、前記主面とは反対側にある裏面とを有し、前記チップ搭載部の周囲に配置され、その両端が前記吊りリードと連結された共通リードと、
主面と、前記主面とは反対側にある裏面とを有し、前記共通リードの周囲に配置された複数のリードと、
前記複数の電極のうち、前記複数のリードに対応した電極と前記複数のリードの主面とをそれぞれ電気的に接続する第１ワイヤと、
前記複数の電極のうち、前記共通リードに対応した電極と前記共通リードの主面とをそれぞれ電気的に接続する第２ワイヤと、
前記半導体チップの主面よりも上にある主面と、前記主面とは反対側にある裏面と、を有する封止体と、を備えた半導体装置であって、
前記封止体は、前記半導体チップ、前記第１ワイヤ、及び前記第２ワイヤを樹脂封止し、
前記吊りリードは、前記チップ搭載部と前記共通リードに挟まれた第１部分と、前記第１部分を除く第２部分と、を有し、
前記リードの裏面、前記チップ搭載部の裏面、前記共通リードの裏面、及び前記吊りリードの前記第１部分の裏面は前記封止体の裏面から露出し、前記吊りリードの前記第２部分の裏面は前記封止体内に配置されており、
前記封止体の一部は前記半導体チップの裏面と密着していることを特徴とする半導体装置。 A semiconductor chip having a main surface on which a semiconductor element and a plurality of electrodes are formed, and a back surface opposite to the main surface;
A chip mounting portion having a main surface on which the semiconductor chip is mounted such that the main surface of the semiconductor chip faces in the same direction, and a back surface on the opposite side of the main surface;
A plurality of suspension leads having a main surface and a back surface opposite to the main surface and connected to the chip mounting portion;
A common lead having a main surface and a back surface opposite to the main surface , disposed around the chip mounting portion , and both ends thereof connected to the suspension lead ;
A plurality of leads having a main surface and a back surface opposite to the main surface, and disposed around the common lead;
Of the plurality of electrodes, a first wire that electrically connects electrodes corresponding to the plurality of leads and main surfaces of the plurality of leads,
A second wire that electrically connects the electrode corresponding to the common lead and the main surface of the common lead among the plurality of electrodes;
A semiconductor device comprising: a sealing body having a main surface above the main surface of the semiconductor chip; and a back surface opposite to the main surface;
The sealing body, the semiconductor chip, before Symbol first wire, and the second wire by resin sealing,
The suspension lead has a first portion sandwiched between the chip mounting portion and the common lead, and a second portion excluding the first portion,
The rear surface of the front Symbol leads, the back surface of the chip mounting portion, the back surface of the common lead, and the rear surface of the first portion of the suspension lead is exposed from the back surface of the sealing body, of the second portion of the suspension lead backside is disposed within the sealing body,
A part of the sealing body is in close contact with the back surface of the semiconductor chip.
前記チップ搭載部の外形寸法は、前記半導体チップの外形寸法よりも小さいことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an outer dimension of the chip mounting portion is smaller than an outer dimension of the semiconductor chip.
前記チップ搭載部は前記主面と前記裏面との間に側面を有し、
前記半導体チップは前記主面と前記裏面との間に側面を有し、
前記チップ搭載部の側面及び前記半導体チップの側面は、前記封止体の一部と密着していることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The chip mounting portion has a side surface between the main surface and the back surface,
The semiconductor chip has a side surface between the main surface and the back surface;
The semiconductor device according to claim 1 , wherein a side surface of the chip mounting portion and a side surface of the semiconductor chip are in close contact with a part of the sealing body.
前記封止体は四角形状であって、前記封止体の４つの角部に対応した箇所に前記チップ搭載部と連結する前記吊りリードが配置され、前記共通リードは前記吊りリードに連結されていることにより、前記共通リードは、前記吊りリードの一部を介して前記チップ搭載部と連結されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The sealing body is a rectangular shape, the suspension leads connecting to the chip mounting portion is disposed at a position corresponding to the four corners of the sealing body, the common lead is connected to the suspension lead Therefore, the common lead is connected to the chip mounting portion through a part of the suspension lead.
前記共通リードは、グランド電位が印加されるリードであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the common lead is a lead to which a ground potential is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009081042A JP4839387B2 (en) | 2009-03-30 | 2009-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009081042A JP4839387B2 (en) | 2009-03-30 | 2009-03-30 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003431915A Division JP2005191342A (en) | 2003-12-26 | 2003-12-26 | Semiconductor device and manufacturing method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009177197A JP2009177197A (en) | 2009-08-06 |
| JP2009177197A5 true JP2009177197A5 (en) | 2009-09-17 |
| JP4839387B2 JP4839387B2 (en) | 2011-12-21 |
Family
ID=41031889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009081042A Expired - Fee Related JP4839387B2 (en) | 2009-03-30 | 2009-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4839387B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11168169A (en) * | 1997-12-04 | 1999-06-22 | Hitachi Ltd | Lead frame, semiconductor device using lead frame and manufacture thereof |
| JP3285815B2 (en) * | 1998-03-12 | 2002-05-27 | 松下電器産業株式会社 | Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same |
| JP2001077278A (en) * | 1999-10-15 | 2001-03-23 | Amkor Technology Korea Inc | Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof |
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
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2009
- 2009-03-30 JP JP2009081042A patent/JP4839387B2/en not_active Expired - Fee Related