JP2009175959A - Divider, division method, and image encoding device using divider - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quicken division arithmetic processing for quantization processing. <P>SOLUTION: Whether or not a divisor is the number of the power of 2 is judged, and the shift quantity of a dividend when the divisor is the number of the power of 2 is determined, and a shift arithmetic operation of the dividend is performed according to the shift quantity, and when the divisor is the number of the power of 2, the quotient is calculated on the basis of the shift arithmetic result to be output from the shift arithmetic means. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a divider, and more particularly to a divider capable of efficiently performing a division operation for quantization processing executed in an image encoding device.

  In compression coding of image data by JPEG (Joint Photographic Expert Group) or MPEG (Moving Picture Experts Group) which are compression coding methods of image data, DCT coefficients obtained by two-dimensional discrete cosine transform (two-dimensional DCT) are used. Then, by dividing by the quantization threshold, a quantization process for obtaining a quantization coefficient as the quotient is executed. Therefore, an image encoding device that performs compression encoding of image data includes a divider that performs a division operation as a circuit that performs quantization processing.

  Here, there is a problem that a divider that performs a division operation generally has a low processing speed. FIG. 6 is an explanatory diagram showing a basic algorithm for division operation.

  First, the value of each bit of the [N + 1] -bit reduced number Md is set to “0”, and the value of the index i is set to [M−1] (step S1010). Here, M indicates the number of bits of the dividend Dd, and N indicates the number of bits of the divisor Ds.

  Then, the value of the bit Dd [i] corresponding to the index i is added to the divisor Md (step S1020).

  Next, when the divisor Md is equal to or greater than the divisor Ds (step S1030: YES), the divisor Ds is subtracted from the divisor Md (step S1040), and the bit quotient Q [i] corresponding to the index i is set to “1”. (Step S1050). On the other hand, when the divisor Md is smaller than the divisor Ds (step S1030: NO), the quotient Q [i] is set to “0” (step S1060).

  If the index i is “0” (step S1070: YES), the division operation is terminated. On the other hand, if the index i is not “0” (step S1070: NO), the index i is decremented by “1” (step S1080), the subordinate Md is shifted left by 1 bit, and the value of the most significant bit is discarded. After setting the value as a new divisor Md (step S1090), the process returns to step S1020 to execute the processes of steps S1020 to S1060. That is, the processes in steps S1020 to S1090 are repeated until the index i becomes “0”.

  As described above, the basic algorithm of the division operation repeatedly executes the processing in steps S1020 to S1090 in order from the most significant bit (i = [M−1]) to the least significant bit (i = 0) of the dividend. By doing so, the division result is obtained.

  FIG. 7 shows a configuration in which processing for each bit of the dividend Dd in the arithmetic algorithm is performed as a divider according to the basic algorithm of division operation, during one clock of the reference clock. FIG.

  The divider 1000 includes a dividend register 101 that stores an M-bit dividend Dd, a divisor register 102 that stores an N-bit divisor Ds, and a quotient register 103 that stores an M-bit quotient Q. The divider 1000 also selects and outputs a 1-bit dividend Dd [i] from the M-bit dividend Dd [M−1: 0], and outputs a 1-bit dividend Dd [i] to the divisor Md. [N + 1] -bit reduced register 105 that stores the least significant bit. Further, the divider 1000 subtracts the N-bit divisor Ds from the [N + 1] -bit divisor Md, and outputs the N-bit subtraction result (remainder). The subtractor Md is equal to or greater than the divisor Ds. A comparator 107 that compares whether or not there is, and outputs a 1-bit comparison result; a left shift circuit 108 that shifts the [N + 1] -bit divisor Md by 1 bit to the left and outputs an N-bit divisor Md; and subtraction The selector 109 that selects and outputs either the output of the comparator 106 or the output of the left shift circuit 108, and which bit of the M-bit quotient register 103 the 1-bit output of the comparator 107 is written to are determined. The selector 110 and the control circuit 111 that controls the operation of the selector 104 and the selector 110 are provided. Note that the output of the comparator 107 is also input to the selector 109 as a control signal of the selector 109.

  The selector 104 and the dividend register 105 execute the processing of step S1020 in FIG. 6, that is, the processing of adding the value of the dividend Dd [i] of the bit corresponding to the index i to the dividend Md.

  By the subtractor 106, the comparator 107, and the selector 110, the processing of steps S1030 to S1060, that is, when the dividend Md is equal to or larger than the divisor Ds, the divisor Ds is subtracted from the dividend Md, and the bit corresponding to the index i When the quotient Q [i] is set to “1” and the divisor Md is smaller than the divisor Ds, the quotient Q [i] is set to “0”.

  By the control circuit 111, the left shift circuit 108, and the selector 109, the processing of steps S1070 to S1090, that is, the index i is decremented by “1”, the subtracted Md is shifted left by 1 bit, and the value of the most significant bit is discarded. A process is performed in which the calculated value is used as a new value of the upper N bits of the subtracted Md.

  In the case of the configuration as shown in FIG. 7, a time corresponding to the number of clocks equal to the number of bits M of the dividend Dd is required for the division calculation process. For example, a DCT coefficient as a dividend is represented by 11 bits (sign pear), and a quantization coefficient as a divisor is represented by 8 bits. However, when 1-bit processing is performed with 1 reference clock, The time for 11 clocks is required for the division calculation process.

  FIG. 8 shows a case where the processing for each bit of the dividend Dd in the arithmetic algorithm is performed as a divider according to the basic algorithm of the division operation, and the processing of 3 bits is performed during one clock of the reference clock. It is a block diagram which shows the structure of these.

  The divider 1000A replaces the subtractor 106, the comparator 107, the left shift circuit 108, and the selector 109 of the divider 1000 in FIG. 7 in order to execute 3-bit processing during one clock of the reference clock. Thus, subtracters 106a to 106c for three bits, comparators 107a to 107c, left shift circuits 108a to 108c, and selectors 109a to 109c are provided in three stages. In order to correspond to this configuration, instead of the selector 104 and the selector 110 of the divider 1000, the M-bit dividend Dd [M-1: 0] to the 3-bit dividends Dd [i] and Dd [i-1 ], Dd [i-2], the selector 104A that outputs as the least significant bit of the [N + 1] -bit divisor Md that is input to the subtractors 106a, 106b, and 106c, and the outputs of the comparators 107a to 107c. And a selector 110A that determines which of the 3 bits of the M-bit quotient register 103 is to be written. Further, instead of the control circuit 111, a control circuit 111A for controlling the operation of the selector 104A and the selector 110A is provided.

  In the case of the configuration shown in FIG. 8, the time required for the division calculation process is shorter than that in the configuration of FIG. For example, when an 11-bit DCT coefficient is used as a dividend and an 8-bit quantization coefficient is used as a divisor, the division calculation process is executed in a time corresponding to 4 clocks of the reference clock. However, since the number of bits that can be processed at one time depends on the operation speed of the circuit, the type of semiconductor process that constitutes the circuit, and the like, the number of bits that can be executed collectively is limited. Further, as the number of bits to be executed collectively increases, the circuit scale increases proportionally.

  In addition, it is possible to improve the throughput of the divider by pipelining a series of processing, but in this case as well, the number of processing circuits for the number of pipeline stages is increased, and in addition, pipeline processing Since a register is also required, the circuit scale increases.

  As a divider using a division calculation method for solving the above problems, for example, examples described in Patent Documents 1 and 2 have been proposed. These division calculation methods compare a DCT coefficient as a dividend and a quantization threshold as a divisor. If the quantization threshold is larger than the DCT coefficient, the quotient as the quantization coefficient is set to “0” without performing the division operation process executed by repeating the process of subtracting the divisor from the divisor. By setting, the actual division calculation process is omitted and the calculation process time as a whole is increased.

  However, in the divider using the above division operation method, when the DCT coefficient as the dividend is larger than the quantization threshold as the divisor, the most significant bit to the least significant bit is eventually obtained for each bit of the DCT coefficient as the dividend. Processing such as step S1020 to step S1090 is repeated in order up to the bit, so that the division operation processing time cannot be shortened, and the speed of the operation processing time as a whole is insufficient.

JP-A-10-191334 Japanese Patent Laid-Open No. 3-85871

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a technique capable of increasing the speed of division operation processing for quantization processing.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A divider for obtaining a quotient obtained by dividing a dividend by a divisor,
Determining whether the divisor is a power of 2 and determining a power of 2 for determining a shift amount of the dividend when the divisor is a power of 2;
Shift computing means for computing the dividend according to the shift amount;
Control means for obtaining the quotient based on a shift calculation result output from the shift calculation means when the divisor is a power of 2;
A divider comprising:

  In the divider described in Application Example 1, when the divisor is a power of 2, the quotient is obtained based on the shift calculation result output from the shift calculation means, and the dividend is actually divided by the divisor Therefore, the time required for the division calculation process can be shortened, and the division calculation process can be speeded up.

[Application Example 2]
A divider according to application example 1,
Furthermore, a comparison means for comparing and determining whether or not the dividend is smaller than the divisor,
The divider obtains the quotient by setting the quotient of each bit to zero when the dividend is smaller than the divisor.

  In the divider described in Application Example 2, when the dividend is smaller than the divisor, the quotient obtained by dividing the dividend by the divisor is obtained by setting the quotient of each bit to zero, and actually dividing the dividend by the divisor Therefore, it is possible to shorten the time required for the division calculation process and increase the speed of the division calculation process.

[Application Example 3]
A divider according to application example 1 or application example 2,
The dividend is a DCT coefficient obtained by discrete cosine transform of image data, and the divisor is a predetermined quantization threshold.
A divider characterized by that.

  In the divider described in Application Example 3, the time required for quantization processing as division operation processing for dividing a DCT coefficient as a dividend by a quantization threshold value as a divisor and obtaining a quantization coefficient as a quotient is shortened. It is possible to speed up the quantization process.

[Application Example 4]
Provided with a divider as described in Application Example 3,
The quotient obtained by dividing the DCT coefficient by the quantization threshold is obtained as the quantization coefficient by inputting the DCT coefficient as the dividend and inputting the quantization threshold as the divisor to the divider. An image encoding apparatus characterized by that.

  The image coding apparatus described in Application Example 4 can achieve the same effects as Application Example 3.

[Application Example 5]
A division method for obtaining a quotient obtained by dividing a dividend by a divisor,
Determining whether the divisor is a power of 2 and determining a shift amount of the dividend when the divisor is a power of 2;
Shifting the dividend according to the shift amount,
When the divisor is a power of 2, the quotient is obtained based on a shift calculation result output from the shift calculation means.
A division method characterized by that.

  According to the division method described in Application Example 5, the same effects as in Application Example 1 can be obtained.

A. Configuration of image encoding device:
B. Divider configuration:
B1. Division algorithm:
B2. Specific examples of dividers:
C. Variations:

A. Configuration of image encoding device:
FIG. 1 is a block diagram showing a configuration of an image encoding apparatus in which a divider according to the present invention is applied to a quantization unit. FIG. 2 is an explanatory diagram illustrating quantization processing executed by the image encoding device.

  The image encoding device 10 includes a DCT unit 20, a quantization unit 30, a quantization table 40, a Huffman encoding unit 50, and a Huffman table 60.

  The DCT unit 20 performs a two-dimensional discrete cosine transform on each image divided into blocks of [8 × 8] pixels as shown in FIG. 2 (A) to obtain DCT coefficients as shown in FIG. 2 (B). Is a functional block to obtain

  The quantization unit 30 divides the DCT coefficient of each block by the quantization threshold value stored in the quantization table 40 as shown in FIG. 2 (C), as shown in FIG. 2 (D). It is a functional block for obtaining a quantized coefficient as a quotient.

  The obtained quantized coefficients are taken out in the scanning order of the quantized coefficients represented by the numbers Q1 to Q64 and input to the Huffman encoder 50 as shown in FIG.

  The Huffman encoder 50 is a functional block that encodes the input quantization coefficient according to the Huffman table 60.

  As described above, the image encoding device 10 converts image data representing an image into DCT coefficients by the DCT unit 20, and divides the obtained DCT coefficients by the quantization threshold in the quantization unit 30 using a divider. It is an apparatus that generates code data obtained by encoding an image represented by image data by performing quantization by processing and encoding the obtained quantized coefficient by a Huffman encoding unit 50.

B. Divider configuration:
Below, the divider | division as one Example used for the quantization part 30 of the image coding apparatus 10 is demonstrated.

B1. Division algorithm:
In the case of JPEG image compression encoding processing, as a quantization processing, a division operation represented by [DCT coefficient (code no 11 bits) ÷ quantization threshold (code no 8 bits)] is executed, and the quotient The quantized coefficient (sign pear 11 bits) is in the range of [0x000] to [0x7FF].

  Here, when an actual natural image, for example, a 5M pixel photograph taken with a digital camera, is examined for a quantization coefficient when image compression encoding processing by the JPEG method is executed in the high quality mode, the following characteristics are obtained. I found out.

[A] Since a natural image does not contain much high-frequency components, even if the DCT coefficients of high-frequency components are removed from DCT coefficients obtained by DCT conversion of image data, it is considered that there is little deterioration in image quality. It is done. Therefore, in the division operation as the quantization process, for the purpose of compressing the image data by removing the high frequency component, the division threshold is calculated by dividing the quantization threshold corresponding to the high frequency component out of the quantization threshold as the dividend. A large numerical value such that the quotient quantization coefficient is zero is used. For example, in the actual natural image, the quantization coefficient of 65 to 80% is [0x000].

[B] The low-frequency component of the natural image has a great influence on the deterioration of the image quality. Therefore, in the quantization processing by division operation, a relatively small numerical value ([0x01] to [0x20]) is used for the quantization threshold of the portion corresponding to the low frequency component for the purpose of preventing the deterioration of the image quality and compressing the image data. Used. Such a relatively small numerical value has a high ratio that is a power of 2 in the first place. For example, out of 32 numerical values in the range of [0x01] to [0x20], the powers of 2 are [0x01], [0x02], [0x04], [0x08], [0x10], [0x20]. There are six, accounting for about 18%. Also, in the field of digital processing, the arithmetic processing of the number of powers of 2 can increase the speed. Therefore, the data to be processed tends to be the number of powers of 2, and the quantization threshold is also a power of 2. The frequency is relatively high. For example, in the actual natural image, the quantization threshold as a divisor of 10 to 50% is a power of 2 in a portion (35 to 15% of the whole) where the quantization coefficient as a quotient is not [0x000]. It has become a number.

  Therefore, focusing on the above points, it is considered possible to increase the speed of the division calculation process as described below.

[1] A quantization coefficient of [0x000] indicates that the DCT coefficient (dividend) is smaller than the quantization threshold (divisor). Therefore, as described in the conventional example, the DCT coefficient is compared with the quantization threshold, and when DCT coefficient <quantization threshold, the quantization coefficient as the quotient of the division operation is set to [0x000] and the conventional algorithm is used. The subtraction process (see the processes in steps S1020 to S1090 in FIG. 6) executed for each bit of the DCT coefficient (dividend) described in the above is omitted. Accordingly, for example, among the division calculation processing as the actual natural image quantization processing, the processing time in the division calculation processing of 65 to 80% can be shortened, so that the division calculation processing is accelerated as a whole. Can be achieved.

[2] When the quantization threshold as the divisor is a power of 2, the DCT coefficient as the dividend is shifted to obtain the quantization coefficient as the quotient of the division operation, and the DCT described in the conventional algorithm The subtraction process (see steps S1020 to S1090 in FIG. 6) executed for each bit of the coefficient (dividend) is omitted. Thereby, for example, in the division calculation process as the quantization process of the actual natural image, the division calculation of 10 to 50% in the part (35 to 15% of the whole) where the quantization coefficient is not [0x000]. The processing time in the processing can be shortened, and the division operation processing can be accelerated as a whole.

  FIG. 3 is an explanatory diagram showing an algorithm of division operation as an embodiment of the present invention.

  First, it is determined whether or not the M-bit dividend Dd is equal to or greater than the N-bit divisor Ds (step S101). When the dividend Dd is smaller than the divisor Ds (step S101: NO), the quotients Q [M−1] to Q [0] of each bit of the M-bit quotient Q are set to “0” (step S102). Terminates the division operation. On the other hand, if the dividend Dd is equal to or greater than the divisor Ds (step S101: YES), it is further determined whether the divisor Ds is a power of 2 (step S103), and the next processing is performed according to the result. Execute.

  When the divisor Ds is a power of 2 (step S103: YES), the bit quotient Q [M−1] ˜ of the M-bit quotient Q is shifted by performing a shift operation on the dividend Dd according to the divisor Ds. Q [0] is obtained (step S104).

  On the other hand, when the divisor Ds is not a power of 2 (step S103: NO), the processing of step S105 to step S113 is executed, and the quotient Q [M−1] to Q of each bit of the quotient Q of M bits. [0] is obtained. Note that steps S105 to S113 are the same as the normal division calculation processing in steps S1010 to S1090 in FIG. 6, and thus the description thereof is omitted here.

  As described above, in the algorithm of the present embodiment, first, when the dividend Dd is equal to or greater than the divisor Ds, the quotients Q [M−1] to Q [0] of each bit of the M-bit quotient Q are calculated. A division result is obtained by setting “0”. Second, when the divisor Ds is a power of two, the dividend Dd is shifted to obtain the quotients Q [M−1] to Q [0] of each bit of the M-bit quotient Q. A division result is obtained. Third, when neither the first case nor the second case is performed, a division operation similar to the conventional one is executed, and the quotients Q [M−1] to Q [0] of each bit of the quotient Q of M bits. To obtain the division result. Therefore, when the dividend Dd is smaller than the divisor Ds and when the divisor Ds is a power of 2, the processing of steps S105 to S113, which is a division operation processing similar to the conventional one, can be omitted.

  For example, as described above, in the case of image compression encoding processing of a single natural image by the JPEG method, the quantization coefficient that is the quotient of the division operation as quantization processing is [0x000], that is, M The case where the 11-bit DCT coefficient as the bit dividend Dd is smaller than the 8-bit quantization threshold as the N-bit divisor Ds is 65 to 80%. Therefore, in this case, it is possible to shorten the processing time in the division calculation process of 65 to 80% of the division calculation process as the quantization process of the natural image, and the speed of the division calculation process as a whole is increased. Can be achieved. Further, when the quantization threshold as the divisor Ds is a power of 2, it is 10 to 50% in the portion (35 to 15% of the whole) where the quantization coefficient is not [0x000]. Therefore, in this case, among the division calculation processing as the natural image quantization processing, the processing time in the division calculation processing of 1.5 to 17.5% can be shortened. It is possible to increase the processing speed.

B2. Specific examples of dividers:
FIG. 4 shows a case where the processing for each bit of the dividend Dd is executed as 1-bit processing during one clock of the reference clock as a divider according to the algorithm of division operation as an embodiment of the present invention. It is a block diagram which shows a structure.

  This divider 100 includes a comparator 112, a power-of-two decision circuit 3, a shift calculator 114, in addition to the configuration of the conventional divider 1000 according to the basic division algorithm shown in FIG. . A selector 115 is provided between the selector 110 and the quotient register 103. Further, a control circuit 116 is provided instead of the control circuit 111.

  The comparator 112 is a functional block that compares the M-bit dividend Dd with the N-bit divisor Ds and outputs the comparison result to the control circuit 116.

  The power-of-two determination circuit 113 determines whether or not the divisor Ds is a power of 2, determines the shift amount of the dividend Dd when the divisor Ds is a power of 2, and determines the determination result. This is a functional block that outputs to the control circuit 116 and outputs the shift amount to the shift computing unit 114. The determination as to whether the number is a power of 2 and the shift amount can be easily configured by a logic circuit that detects that only one bit of each bit of the divisor Ds is “1”.

  The shift calculator 114 is a functional block that shifts the dividend Dd with the shift amount input from the power-of-two determination circuit 113 and outputs the obtained result to the selector 115 as a quotient Q.

  The selector 115 writes the output of the selector 110 into the quotient register 103, writes the output of the shift calculator 114 into the quotient register 103, or writes “0” into the quotient register 103 according to the control signal of the control circuit 116. Function block to be selected.

  The control circuit 116 is a functional block that controls the operations of the selector 104, the selector 110, and the selector 115 according to the comparison result of the comparator 112 and the determination result of the power-of-two determination circuit 113.

  The comparator 112, the selector 115, and the control circuit 116 determine whether the M-bit dividend Dd is smaller than the N-bit divisor Ds in steps S101 and S102 of FIG. When the divisor is smaller than the divisor Ds, a process of setting the quotients Q [M−1] to Q [0] of each bit of the M-bit quotient Q to “0” is executed.

  The power-of-two determining circuit 113, the shift computing unit 14, the selector 115, and the control circuit 116 determine whether the divisor Ds is a process of steps S103 and S104, that is, whether the divisor Ds is a power of two. When the number is a power of two, a process of obtaining each bit quotient Q [M−1] to Q [0] of the M-bit quotient Q by performing a shift operation on the dividend Dd according to the divisor Ds is executed. Is done.

  The processing of steps S105 to S110 is performed by the selector 104, the attenuator register 105, the subtractor 106, the comparator 107, the left shift circuit 108, the selector 109, and the selector 110, which are the same components as those of the conventional divider 1000. That is, the same processing as the normal division operation processing in steps S1010 to S1090 in the conventional basic division operation algorithm shown in FIG. 6 is executed, and the quotient Q [M−1 of each bit of the M-bit quotient Q is executed. ] To Q [0] are executed.

  In the configuration of the divider 100, a division operation according to the algorithm of the division operation shown in FIG. 3 can be executed, and the processing time of the division operation as the quantization processing in the image compression encoding device is shortened. Therefore, it is possible to speed up the division calculation process for the quantization process.

  Further, in the configuration of the divider 100, basically, a comparator 112, a power decision circuit 113, a shift calculator 114, and a selector 115 are added to the conventional divider 1000 (see FIG. 7). Therefore, the efficiency is higher than that of a divider having a complicated and large circuit scale such as a divider provided in a general-purpose processor.

  Further, when the dividend Dd is equal to or greater than the divisor Ds or when the divisor Ds is not a power of two, the same division operation processing is executed, so that at least the same operation as the conventional divider 1000 is performed. Can do.

  FIG. 5 shows a case where the processing for each bit of the dividend Dd is performed as a divider according to the division operation algorithm as an embodiment of the present invention, and the processing of 3 bits is performed during one clock of the reference clock. It is a block diagram which shows a structure.

  In addition to the configuration of the conventional divider 1000A in accordance with the basic division operation algorithm shown in FIG. 8, this divider 100A is similar to the divider 100 shown in FIG. Power decision circuit 3 and shift calculator 114. A selector 115 is provided between the selector 110 and the quotient register 103. Further, a control circuit 116A is provided instead of the control circuit 111A.

  The control circuit 116A is a functional block that controls the operations of the selector 104A, the selector 110A, and the selector 115 in accordance with the comparison result of the comparator 112 and the determination result of the power-of-two determination circuit 113.

  In the configuration of the divider 100A, similarly to the divider 100 shown in FIG. 4, the division operation according to the algorithm of the division operation shown in FIG. 3 can be executed, and the quantization process in the image compression encoding apparatus is performed. As a result, it is possible to shorten the processing time of the division operation as described above, so that it is possible to increase the speed of the division operation processing for the quantization processing.

  Further, in the configuration of the divider 100A, the divider 100 shown in FIG. 4 can execute 1-bit processing during one clock of the reference clock, but can execute 3-bit processing. Therefore, compared with the divider 100, the processing time repeatedly executed in steps S105 to S113 in FIG. 3 can be further shortened, so that the division operation processing for the quantization processing can be speeded up. Is possible.

  The configuration of the divider 100A also basically includes a comparator 112, a power determination circuit 113 of 2 and a shift calculator 114, and a selector 115 in addition to the conventional divider 1000A (see FIG. 8). Therefore, the efficiency is higher than that of a divider having a complicated and large circuit scale such as a divider provided in a general-purpose processor.

  Further, when the dividend Dd is equal to or greater than the divisor Ds, or when the divisor Ds is not a power of two, the same division operation processing is executed, so that at least the same operation as the conventional divider 1000A is performed. Can do.

  In the dividers 100 and 100A, the comparator 112 corresponds to the whole dividend comparison means of the present invention.

C. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the scope of the invention.

  In the above-described embodiment, as a specific example of the divider, an example of a configuration in which 1-bit processing is executed during one clock and an example of a configuration in which 3-bit processing is executed during one clock. Although shown, the present invention is not limited to this, and a multi-bit processing is performed during one clock, such as a configuration in which 2-bit processing is performed during one clock or a 4-bit processing is performed. Applicable to configurations for execution.

  In the above-described embodiment, as an example, a DCT coefficient obtained by performing two-dimensional discrete cosine transform on image data of a natural image is a dividend, a quantization threshold is a divisor, and a quantization coefficient is obtained as a quotient of a division operation. Although described, the present invention is not limited to this, and can be applied to various cases. This is particularly effective when the divisor includes a large number of powers of 2.

It is a block diagram which shows the structure of the image coding apparatus which applied the divider of this invention to the quantization part. It is explanatory drawing shown about the quantization process performed with an image coding apparatus. It is explanatory drawing which shows the algorithm of the division operation as an Example of this invention. It is a block diagram which shows the structure in the case of performing the process about each bit of the dividend Dd as a divider according to the algorithm of the division operation as an Example of this invention between 1 clocks of a reference clock. . It is a block diagram which shows the structure in the case of performing the process about each bit of the dividend Dd as a divider according to the algorithm of the division operation as an Example of this invention, during a 1-clock reference clock process. . It is explanatory drawing which shows the algorithm of a basic division operation. It is a block diagram which shows the structure in the case of performing the process about each bit of the dividend Dd in an arithmetic algorithm as 1 time of a reference clock as a divider according to the basic algorithm of a division operation. It is a block diagram which shows the structure in the case of performing the process about each bit of the dividend Dd in an arithmetic algorithm as a divider according to the basic algorithm of a division operation in 1 clock of reference clocks.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Image coding apparatus 20 ... DCT part 30 ... Quantization part 40 ... Quantization table 50 ... Huffman coding part 60 ... Huffman table 100 ... Divider 100A ... Divider 101 ... Dividend register 102 ... Divide register 103 ... Quotient register DESCRIPTION OF SYMBOLS 105 ... Subtracted register 104 ... Selector 104A ... Selector 106 ... Subtractor 107 ... Comparator 108 ... Left shift circuit 109 ... Selector 106a-106c ... Subtractor 107a-107c ... Comparator 108a-108c ... Left shift circuit 109a-109c ... Selector DESCRIPTION OF SYMBOLS 110 ... Selector 110A ... Selector 111 ... Control circuit 111A ... Control circuit 112 ... Comparator 113 ... Power-of-two judgment circuit 114 ... Shift calculator 114
115: Selector 116 ... Control circuit 116A ... Control circuit

Claims (5)

A divider for obtaining a quotient obtained by dividing a dividend by a divisor,
Determining whether the divisor is a power of 2 and determining a power of 2 for determining a shift amount of the dividend when the divisor is a power of 2;
Shift computing means for computing the dividend according to the shift amount;
Control means for obtaining the quotient based on a shift calculation result output from the shift calculation means when the divisor is a power of 2;
A divider comprising: The divider according to claim 1, wherein
Furthermore, a comparison means for comparing and determining whether or not the dividend is smaller than the divisor,
The divider obtains the quotient by setting the quotient of each bit to zero when the dividend is smaller than the divisor. A divider according to claim 1 or claim 2, wherein
The dividend is a DCT coefficient obtained by discrete cosine transform of image data, and the divisor is a predetermined quantization threshold.
A divider characterized by that. A divider according to claim 3,
The quotient obtained by dividing the DCT coefficient by the quantization threshold is obtained as the quantization coefficient by inputting the DCT coefficient as the dividend and inputting the quantization threshold as the divisor to the divider. An image encoding apparatus characterized by that. A division method for obtaining a quotient obtained by dividing a dividend by a divisor,
Determining whether the divisor is a power of 2 and determining a shift amount of the dividend when the divisor is a power of 2;
Shifting the dividend according to the shift amount,
When the divisor is a power of 2, the quotient is obtained based on a shift calculation result output from the shift calculation means.
A division method characterized by that.

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