JP2009171390A - Differential signal receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make not only skew correction between differential signals inputted into individual differential signal receivers but also the skew correction between image data signals outputted from respective differential signal receivers. <P>SOLUTION: A differential interface is constituted of differential signal drivers 11a-11c and skew correction differential signal receivers 13a-13b. Waveform adjustment circuits 18a, 18b for correcting skew (gap of rise time and falling time duration) between differential signals inputted into a differential signal receiving circuit 17 are provided in the anterior stages of respective differential signal receivers 13a-13b. A delay circuit 19 for correcting skew (gap of delay times) between data signals outputted from the differential signal receiving circuit 17 is provided in the posterior stage of respective differential signal receivers 13a-13c. According to this method, the skew between differential signals inputted into respective differential signal receiving circuits 17 and the skew between image data signals outputted from respective delay circuits 19 can be corrected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a differential signal receiving apparatus including a plurality of differential signal receiving circuits that receive differential signals respectively output from a plurality of differential signal output circuits.

  2. Description of the Related Art Digital cameras that convert a captured image captured using an image sensor such as a CCD image sensor into digital image data and record it on a recording medium such as a memory card have become popular. A digital camera uses a differential interface as an interface for transmitting an image data signal of a captured image captured by an image sensor to an image processing circuit or the like at high speed (see, for example, Patent Document 1). The differential interface includes a differential signal driver and a differential signal receiver, which are connected via a pair of differential signal transmission paths.

  The differential signal driver converts the image data signal output from the image sensor into a positive (+) differential signal and a negative (−) differential signal, and performs differential operation via both differential signal transmission paths. Output to the signal receiver. If the difference between the positive differential signal output from the differential signal driver and the negative differential signal is positive, the differential signal receiver determines that the level is H (High), and if the difference between the two is negative. It discriminate | determines as L (Low) level, and converts the received differential signal into an image data signal.

  By the way, in the data transmission method using the differential interface, a skew is generated between the differential signals input to the differential signal receiver due to a difference in line length between the two differential signal transmission paths, a difference in wiring capacitance, or the like. To do. The skew is a delay of the rise time and fall time of the signal waveform of the differential signal (see FIG. 4), a delay of the signal waveform (see FIG. 7), and the like, and causes common mode noise. The common mode noise is a noise current that flows in the same direction through each differential signal transmission path when a noise source exists between the signal line (operation signal transmission path) and the ground. In order to suppress the occurrence of such common mode noise, various countermeasures for suppressing the occurrence of skew between differential signals have been proposed.

For example, a method of correcting a skew between differential signals transmitted through both differential signal transmission lines by providing a delay element in the differential signal driver has been proposed (see, for example, Patent Document 2). Further, the differential signal output from the differential signal driver is compared with the data signal of the previous stage of the differential signal driver, and the magnitude of the delay of the image data signal with respect to the differential signal is detected. A method of correcting skew between differential signals by changing the drive capability of the differential signal driver and the capacity of the differential signal transmission path has been proposed (for example, see Patent Document 3).
JP 2006-107292 A JP 2004-327797 A JP 2004-320471 A

  By the way, when transmitting an image data signal, many output lines are required. For this reason, the differential interface is provided with a plurality of pairs of differential signal drivers and differential signal receivers. At this time, in the methods described in Patent Documents 2 and 3, skew correction between differential signals input to individual differential signal receivers is possible, but image data output from each differential signal receiver. There is a problem that skew correction between signals cannot be performed.

  The present invention has been made to solve the above-described problem, and in addition to correcting skew between differential signals respectively input from a plurality of differential signal drivers to each differential signal receiver, An object of the present invention is to provide a differential signal receiving apparatus capable of correcting a skew between output data signals.

  In order to solve the above problem, a differential signal receiving apparatus of the present invention is connected to a plurality of differential signal output circuits that output differential signals via a pair of differential signal transmission lines, respectively, and the differential signal output A plurality of differential signal receiving circuits that receive the differential signals output from the circuits and convert them into data signals, and are provided in a preceding stage of each of the differential signal receiving circuits, via the pair of differential signal transmission paths A plurality of first skew correction circuits for correcting skew between the differential signals input to the differential signal receiving circuit; and each differential signal receiving circuit provided at a subsequent stage of each differential signal receiving circuit. And a plurality of second skew correction circuits that correct skew between the data signals output from the data signal.

  A drive circuit that receives a clock signal and a serial signal from the outside and drives the plurality of first and second skew correction circuits collectively based on a parallel signal obtained by parallelizing the serial signal in synchronization with the clock signal It is preferable to provide. Accordingly, it is not necessary to provide a plurality of drive circuits, so that the cost of the device can be reduced.

  The first skew correction circuit includes a plurality of capacitors having different capacities, and a first selection circuit capable of individually selecting connection and disconnection between the capacitors and the pair of differential signal transmission lines, The drive circuit drives the first selection circuit and selects the capacitors connected to the pair of differential signal transmission lines, whereby the differential signals input to the differential signal reception circuits, respectively. It is preferable to correct the skew between the differential signals by adjusting the rise time and fall time of the signal.

  The second skew correction circuit includes a plurality of delay gates having different delay times for delaying the data signal, and a second selection circuit capable of selecting any one of the delay gates, and the driving The circuit adjusts the delay time of the data signal output from each differential signal receiving circuit by driving the second selection circuit and selecting the delay gate for delaying the data signal. Thus, it is preferable to correct the skew between the data signals.

  In the differential signal receiving apparatus according to the present invention, the first skew correction circuit and the second skew correction circuit are provided at the front stage and the rear stage of each differential signal reception circuit, respectively. In addition to skew correction between differential signals, skew correction between image data signals output from each differential signal receiving circuit can be performed. This can reduce the occurrence of skew between signals and the occurrence of common mode noise due to the occurrence of skew.

  A differential interface 10 shown in FIG. 1 is provided in, for example, a digital camera (not shown), and transmits an image data signal of a captured image taken by an imaging device (not shown) to an image processing circuit or the like at high speed. Interface. The differential interface 10 converts image data signals output from the image sensor through a plurality of output lines into differential signals and transmits the differential signals.

  The differential interface 10 is roughly divided into differential signal drivers 11a to 11c and a pair of differential signal transmission paths (hereinafter simply referred to as transmission paths) 12 connected to the differential signal drivers 11a to 11c. A plurality of skew-corrected differential signal receivers (hereinafter simply referred to as differential signal receivers) 13a to 13c, which are paired with the differential signal drivers 11a to 11c, respectively, and a differential signal receiver drive circuit (hereinafter simply referred to as drive circuit) 14 It consists of and. In the present embodiment, only three pairs of differential signal drivers and differential signal receivers are provided. However, the present invention is not limited to this, and four or more pairs may be provided. .

  Each differential signal driver 11a to 11c corresponds to a differential signal output circuit of the present invention. Each of the differential signal drivers 11a to 11c converts the image data signal input to the input terminal DIN into a positive and negative differential signal and outputs it from the output terminals OUT + and OUT−, respectively. Since a method for converting an image data signal into a differential signal is well known, description thereof is omitted here.

  The differential signals output from both output terminals OUT + and OUT− are input to the differential signal receivers 13 a to 13 c via the transmission line 12. The transmission line 12 includes a first transmission line 12a that connects the output terminals OUT + of the differential signal drivers 11a to 11c and the input terminals IN + of the differential signal receivers 13a to 13c, an output terminal OUT−, and an input terminal IN−. The second transmission path 12b connecting the two. The ends of the transmission lines 12a and 12b on the differential signal receivers 13a to 13c side are connected by a current-voltage conversion resistor 15. The current-voltage conversion resistor 15 converts the differential signal output as a current from each of the differential signal drivers 11a to 11c into a voltage.

  Each of the differential signal receivers 13a to 13c corresponds to the differential signal receiver of the present invention. Each of the differential signal receivers 13a to 13c converts the operation signal input from each of the differential signal drivers 11a to 11c via the transmission path 12 into an image data signal, and outputs the converted image data signal from the output terminal DOUT. . At this time, each of the differential signal receivers 13a to 13c performs skew correction between the differential signals and skew correction between the image data signals. The drive circuit 14 drives a skew correction circuit provided in each of the differential signal receivers 13a to 13c.

  As shown in FIG. 2, each of the differential signal receivers 13a to 13c is roughly divided into a differential signal reception circuit 17, waveform adjustment circuits 18a and 18b (first skew correction circuit), and a delay circuit 19 (second skew correction). Circuit). The differential signal receiving circuit 17 converts the differential signals respectively input to the input terminals IN + and IN− into image data signals. Since a method for converting a differential signal into an image data signal is well known, the description thereof is omitted here. The image data signal output from the differential signal receiving circuit 17 is input to the delay circuit 19.

  The waveform adjustment circuits 18a and 18b are provided in front of each differential signal receiving circuit 17, and rise time and fall time (hereinafter simply referred to as “differential signal”) input to each differential signal receiving circuit 17, respectively. The deviation (skew) of the change time (called time constant) is corrected. As described above, this shift in the change time occurs due to the line length difference or the wiring capacity difference between the first and second transmission paths 12a and 12b. The delay circuit 19 is provided in the subsequent stage of each differential signal receiving circuit 17 and corrects a shift (skew) in the delay time of the image data signal output from each differential signal receiving circuit 17. This shift in the delay time is caused by variations in the performance of the differential signal receiving circuits 17 and differences in line lengths and wiring capacities of the connection lines 20c connecting the differential signal receiving circuits 17 and the delay circuits 19. appear.

  The waveform adjustment circuit 18a has a connection terminal PS connected to a connection line 20a that connects the input terminal IN + and the differential signal receiving circuit 17, and adjusts the shift in the change time of the positive differential signal. Further, the waveform adjusting circuit 18b is connected at its connection terminal MS to the connection line 20b that connects the input terminal IN- and the differential signal receiving circuit 17, and adjusts the shift of the change time of the negative differential signal. .

  As shown in FIG. 3, the waveform adjustment circuits 18 a and 18 b have the same configuration, and include a capacitor parallel circuit 22 and a first selection circuit 23. The capacitor parallel circuit 22 is connected in parallel via the branch line 25 branched into three from the connection terminal PS (MS), the branch line 27 branched into three from the ground 26, and both branch lines 25, 27. First to third capacitors 28a to 28c and n-type first to third MOS (Metal Oxide Semiconductor) transistor switches (hereinafter simply referred to as first to third switches) SW1 to SW1 provided to the branch lines 25, respectively. SW3. The switches are not limited to n-type MOS transistor switches, and various switches may be used.

  The first to third capacitors 28a to 28c have different capacities. In the present embodiment, the capacity of the first capacitor 28a is the lowest and the capacity of the third capacitor 28c is the highest. When the first switch SW1 is turned ON / OFF, the first capacitor 28a and the connection lines 20a and 20b (see FIG. 2) are connected or disconnected, respectively. Similarly, when the second or third switch SW2, SW3 is turned ON / OFF, the second or third capacitor 28b, 28c and the connection line 20a, 20b are connected or disconnected, respectively. When all the switches SW1 to SW3 are turned off, none of the capacitors 28a to 28c is connected to the connection lines 20a and 20b.

  When a capacitor is connected to the connection lines 20a and 20b, the change time of the differential signal transmitted through the connection lines 20a and 20b becomes long. The change time becomes longer as the capacitance of the capacitor connected to each connection line 20a, 20b increases.

  In FIG. 4, waveforms of positive (+) and negative (−) differential signals when the first to third capacitors 28 a to 28 c are not connected to the connection lines 20 a and 20 b are represented by W0 (solid line). Waveforms of both differential signals when the first to third capacitors 28a to 28c are connected to the connection lines 20a and 20b are represented by W1 (dotted line), W2 (one-dot chain line), and W3 (two-dot chain line), respectively. Comparing the waveforms W1 to W3, the change time when the first capacitor 28a is connected is the shortest, and the change time when the third capacitor 28c is connected is the longest.

  Thus, in this embodiment, the change time of each differential signal input to each differential signal receiving circuit 17 is selected by selecting the first to third capacitors 28a to 28c connected to the connection lines 20a and 20b. It can be adjusted (longer) in three stages. When correcting the skew (change time shift) of each differential signal input to each differential signal receiving circuit 17, the change of other differential signals is based on the differential signal having the longest change time. Increase time.

  The change time of each differential signal input to each differential signal receiving circuit 17 is obtained using, for example, a waveform detection device 30 (see FIG. 2) such as an oscilloscope capable of detecting a voltage waveform. The waveform detection device 30 detects the waveform of the differential signal transmitted through the connection lines 20a and 20b before the waveform adjustment circuits 18a and 18b. Then, the change time of the differential signal input to the differential signal receiving circuit 17 is obtained from the waveform detection result.

  When the change time of each differential signal input to each differential signal receiving circuit 17 is obtained, the differential signal having the longest change time is determined as a reference. Next, a connection for transmitting other differential signals so that a difference between a change time of a reference differential signal and a change time of another differential signal (hereinafter simply referred to as a change time difference) is minimized. The capacitor parallel circuit 22 connected to the lines 20a and 20b is driven. Specifically, the first to third switches 29a to 29c are set to ON / OFF.

  For example, when the first to third capacitors 28a to 28c are not connected to the connection lines 20a and 20b, and the shift of the change time is minimized, the first to third switches SW1 to SW3 are all turned off. In addition, when the first to third capacitors 28a to 28c are connected to the connection lines 20a and 20b, respectively, the first to third switches SW1 to SW3 are turned ON if the change in the change time is minimized.

  In order to determine the switch setting of each of the switches SW1 to SW3 that minimizes the deviation of the change time, for example, when the capacitors 28a to 28c are connected to the connection lines 20a and 20b, respectively, τ = CR (τ: time constant ( (Change time), C: wiring capacitance, R: wiring resistance, and how long the change time of the differential signal is measured in advance. Based on the shift, it is possible to determine the switch setting that minimizes the shift time of the change time, and the switch setting is determined for each capacitor parallel circuit 22 by a drive circuit (not shown) of the digital camera, for example. .

  Returning to FIG. 3, ON / OFF of the switches SW <b> 1 to SW <b> 3 of the capacitor parallel circuit 22 is selected by the first selection circuit 23. The first selection circuit 23 has basically the same configuration as a well-known decoder circuit, and switches SW1 to SW3 based on input values of control signals to two input terminals PS (MS) 0 and PS (MS) 1. A selection signal for selecting one of these is output.

  The first selection circuit 23 includes first to third AND circuits 32a to 32c of 2-input 1-output type. The output units of the AND circuits 32a to 32c are connected to the first to third switches SW1 to SW3 via the connection line 33, respectively. Each of the switches SW1 to SW3 is turned on when the selection signal is at a high level, and is turned off when the selection signal is at a low level.

  The input parts of the AND circuits 32a to 32c are connected to the input terminal PS (MS) 0 via a branch line 34 branched into two and input terminal PS via a branch line 35 branched into two. (MS) 1 is connected. A NOT circuit 36 is connected to one of the branch lines 34 and 35. In the present embodiment, the input part of the first AND circuit 32a is connected to the input terminals PS (MS) 0 and PS (MS) 1 via the NOT circuit 36, respectively. The input part of the second AND circuit 32 b is directly connected to the input terminal PS (MS) 0 and is connected to the input terminal PS (MS) 1 via the NOT circuit 36. The input section of the third AND circuit 32c is connected to the input terminal PS (MS) 0 via the NOT circuit 36 and directly connected to the input terminal PS (MS) 1.

  By configuring the first selection circuit 23 in this way, as shown in FIG. 5, the switches SW1 to SW1 are switched according to the input values of the control signals to the input terminals PS (MS) 0 and PS (MS) 1, respectively. SW3 ON / OFF can be selected. Note that “1” in the PS (MS) 0 and PS (MS) 1 columns in FIG. 5 indicates that a high level control signal is input to each input terminal, and “0” indicates a low level. It shows that a control signal is input. Further, “1” and “0” in the SW1 to SW3 columns indicate the level of the selection signal, “1” indicates that the switch is ON, and “0” indicates that the switch is OFF.

  When the control signals of both input terminals PS (MS) 0 and PS (MS) 1 are both “0”, only the first switch SW 1 is turned on. When the control signal of only the input terminal PS (MS) 0 or the input terminal PS (MS) 1 is “1”, only the second switch SW2 and the third switch SW3 are turned on. When both control signals of the input terminals PS (MS) 0 and PS (MS) 1 are “1”, all the switches SW1 to SW3 are turned off.

  When the drive circuit of the digital camera determines the switch setting that minimizes the shift in the change time by the above-described method, the input of the control signal to each input terminal PS (MS) 0, PS (MS) 1 is appropriately set. Then, the switches SW1 to SW3 are turned ON / OFF according to the determined switch settings. As a result, correction is performed such that the skew (shift in change time) between the differential signals respectively input to the differential signal receiving circuits 17 of the differential signal receivers 13a to 13c is minimized.

  As shown in FIG. 6, the delay circuit 19 includes a first branch line 38 that is branched into three from an input terminal IN to which an image data signal is input, and two lines L <b> 1 and L <b> 2 of the branch line 38. The delay gate 39, the second delay gate 40, and the second selection circuit 41 are included. In addition, the code | symbol L3 in a figure is the remaining one line of the branch line 38 in which the delay gate is not provided. The image data signal input to the input terminal IN passes through one of the lines L1 to L3 selected by the second selection circuit 41.

  The first delay gate 39 is obtained by connecting one delay element A, and the second delay gate 40 is obtained by connecting two delay elements A in series. The delay element A delays the data signal output from the differential signal receiving circuit 17. The delay element is not limited to a gate delay circuit, for example, and is not particularly limited as long as the delay time of the data signal can be adjusted.

  In FIG. 7, the waveform when the image data signal passes through the line L3 is indicated by WA (solid line), the waveform when the image data signal passes through the first delay gate 39 of the line L1 is indicated by WB (dotted line), and the waveform of the line L2 The waveform when passing through the second delay gate 40 is indicated by WC (one-dot chain line). Comparing the waveforms WB and WC, since the second delay gate 40 has more delay elements than the first delay gate 39, the image data signal passing through the second delay gate 40 has a first delay. The delay time is longer than that of the image data signal passing through the gate 39.

  Therefore, by selecting which of the lines L1 to L3 the image data signal input to the input terminal IN is allowed to pass through, the delay time of the image data signal can be increased in two stages. When correcting the shift of the delay time of each image data signal, as described in the waveform adjustment circuits 18a and 18b, the image data signal having the longest delay time is used as a reference, and the other image data signals are corrected. Increase the delay time.

  For the image data signal with the longest delay time (which is the reference), the waveform of the image data signal output from each differential signal receiving circuit 17 is detected using the waveform detection device 30 (see FIG. 2). Can be determined. Further, from the detection result by the waveform detection device 30, a deviation in delay time between the reference image data signal and another image data signal (hereinafter simply referred to as a delay time deviation) is obtained. Therefore, one of the lines L1 to L3 is selected in the delay circuit 19 to which another image data signal is input so that the delay time is minimized.

  In order to determine the selection of the lines L1 to L3 that minimize the delay of the delay time, the delay time when the image data signal passes through each of the delay gates 39 and 40 as described in the correction of the shift time of the change time. It is measured in advance how long it becomes. By referring to this gate performance measurement result, it is possible to determine the setting of the line with the smallest delay time deviation based on the delay time deviation. The line setting is determined for each delay circuit 19 by a digital camera drive circuit (not shown), for example.

  Returning to FIG. 6, the second selection circuit 41 is a multiplexer circuit, and selects one of the lines L1 to L3 according to the input values of the control signals to the two input terminals D0 and D1. The image data signal can be passed.

  The second selection circuit 41 includes first to fourth NAND circuits 46a to 46d of three input and one output type. The output part of the first NAND circuit 46 a is connected to the output terminal OUT of the delay circuit 19 through the connection line 47. The output terminal OUT is connected to the output terminals DOUT of the differential signal receivers 13a to 13c. The input part of the first NAND circuit 46 a is connected to the output parts of the second to fourth NAND circuits 46 b to 46 c via the connection line 48.

  One of the input parts of the second to fourth NAND circuits 46b to 46d is connected to the line L3, the line L1 (first delay gate 39), and the line L2 (second delay gate 40). The remaining two input parts of the second to fourth NAND circuits 46b to 46d are connected to the input terminal D0 through the branch line 49 and to the input terminal D1 through the branch line 50. Yes. A NOT circuit 36 is connected to one of the branch lines 49 and 50.

  In the present embodiment, the two input portions of the second NAND circuit 46b are connected to the input terminals D0 and D1 via the NOT circuit 36, respectively. One of the two input parts of the third NAND circuit 46c is directly connected to the input terminal D0, and the other is connected to the input terminal D1 via the NOT circuit 36. Of the two input sections of the fourth NAND circuit 46d, one is connected to the input terminal D0 via the NOT circuit 36, and the other is directly connected to the input terminal D1.

  By configuring the second selection circuit 41 in this way, as shown in FIG. 8, by selecting the input value of the control signal to each of the input terminals D0 and D1, lines L1 to L3 that allow the image data signal to pass therethrough. Can be selected. When the input values of the control signals to the input terminals D0 and D1 are both “0”, at least the control signal “0” is input to the input portions of the third and fourth NAND circuits 46c and 46d. The output signals from the third and fourth NAND circuits 46c and 46d are fixed at “1”. As a result, the lines L1 and L2 (first and second delay gates 39 and 40) are substantially disabled.

  On the other hand, since only the control signal “1” is input to the second NAND circuit 46b, the output signal of the second NAND circuit 46b changes according to the image data signal passing through the line L3. If the input image data signals are “1” and “0”, the output signals of the second NAND circuit 46b are “0” and “1”, respectively. When the output signal of the second NAND circuit 46b is “0”, “0”, “1”, and “1” are input to the input portion of the first NAND circuit 46a from the second to fourth NAND circuits 46b to 46d, respectively. Entered. As a result, the output signal of the first NAND circuit 46a is “1”. Similarly, when the output signal of the second NAND circuit 46b is “1”, “1”, “1”, and “1” are input to the input portion of the first NAND circuit 46a. 0 ". Therefore, when the control signal input to each of the input terminals D0 and D1 is both “0”, only the line L1 is selected.

  When the control signal input to the input terminal D0 is “0” and the control signal input to the input terminal D1 is “1”, the output signals from the second and third NAND circuits 46b and 46c are “1”. On the other hand, the output signal from the fourth NAND circuit 46d changes according to the image data signal passing through the line L2 (second delay gate 40). That is, only the line L2 is selected.

  When the control signal input to the input terminal D0 is “1” and the control signal input to the input terminal D1 is “0”, the output signals from the second and fourth NAND circuits 46b and 46d are “1”. On the other hand, the output signal from the third NAND circuit 46c changes according to the image data signal passing through the line L1 (first delay gate 39). That is, the line L1 is selected.

  Further, when both of the control signal inputs to the input terminals D0 and D1 are “1”, the output signals from the second to fourth NAND circuits 46b to 46d are fixed at “1”, respectively. All of L1 to L3 are substantially invalidated. For this reason, it is prohibited to simultaneously input the control signal “1” to the input terminals D0 and D1.

  When the driving circuit of the digital camera determines the line setting that minimizes the deviation of the delay time by the above-described method, the input line of the control signal to each of the input terminals D0 and D1 is appropriately set so that the line is set according to the determined line setting. Select (Delay Gate). As a result, correction is performed so that the skew (delay in delay time) of each image data signal output from the differential signal receiving circuit 17 of each of the differential signal receivers 13a to 13c is minimized.

  As described above, by driving the waveform adjustment circuits 18a and 18b and the delay circuit 19 of the differential signal receivers 13a to 13c, they are input to the differential signal reception circuit 17 of the differential signal receivers 13a to 13c, respectively. It is possible to correct the skew of each differential signal (shift in change time) and the skew (delay in delay time) of the data signal respectively output from the differential signal receiving circuit 17. The circuits 18a, 18b, and 19 of the differential signal receivers 13a to 13c are collectively driven by the drive circuit 14. Hereinafter, the drive circuit 14 will be described with reference to FIGS.

  The drive circuit 14 is a so-called 18-bit shift register composed of 18 D-type flip-flop circuits 53 connected in cascade (see FIG. 10). For example, a clock signal and a receiver control signal in a serial signal format synchronized with the clock signal are input to the drive circuit 14 from a drive circuit of a digital camera. The receiver control signal is shifted in the drive circuit 14 by the clock signal and output (converted) as an 18-bit parallel signal. Then, the drive circuit 14 outputs a parallel signal format receiver control signal to each of the differential signal receivers 13a to 13c. Since serial-parallel conversion processing by a shift register is well known, description thereof is omitted here.

  The receiver control signal in the parallel signal format is input to the input terminals PS0 to D1 of the differential signal receivers 13a to 13c, respectively. A receiver control signal of receiver setting 1 (see FIG. 11) for setting the differential signal receiver 13a is input to each input terminal PS0 to D1 of the differential signal receiver 13a. Specifically, receiver control signals PS0-1, PS1-1, MS0-1, MS1-1 (which drive the waveform adjustment circuits 18a, 18b are applied to the input terminals PS0, PS1, MS0, MS1 of the differential signal receiver 13a. Each of the waveform adjustment circuit settings 1) is input. In addition, receiver control signals D0-1 and D1-1 (delay circuit setting 1) for driving the delay circuit 19 are input to the input terminals D0 and D1, respectively.

  Similarly, receiver control signals of receiver setting 2 (see FIG. 11) for setting the differential signal receiver 13b are input to the input terminals PS0 to D1 of the differential signal receiver 13b. Specifically, for each of the input terminals PS0 to D1, receiver control signals PS0-2 to MS1-2 (waveform adjustment circuit setting 2) for driving the waveform adjustment circuits 18a and 18b and receiver control for driving the delay circuit 19 are provided. Signals D0-2 and D1-2 (delay circuit setting 2) are respectively input. Further, the receiver control signals PS0-3 of the receiver setting 3 (waveform adjustment circuit setting 3, delay circuit setting 3) for setting the differential signal receiver 13c are input to the input terminals PS0 to D1 of the differential signal receiver 13c. To D1-3 are input.

  After determining the switch setting and the line setting as described above, the driving circuit of the digital camera appropriately sets the frequency and waveform of the clock signal and the receiver control signal to be input to the driving circuit 14, so that each difference from the driving circuit 14 is set. The dynamic signal receivers 13a to 13c are caused to output a receiver control signal for executing switch setting and line setting. As a result, the waveform adjustment circuits 18 a and 18 b and the delay circuit 19 of each of the differential signal receivers 13 a to 13 c can be collectively controlled by the drive circuit 14. As a result, it is not necessary to provide a plurality of drive circuits, so that the differential interface 10 can be reduced in cost.

  Next, the skew correction process of the differential interface 10 of this embodiment will be described. Note that the line lengths and wiring capacities of the transmission lines 12 (see FIG. 1) and the connection lines 20c (see FIG. 3) of the differential interface 10 are basically the same. It may be performed once in the inspection process.

  An inspector in the inspection process inputs a test image data signal to each of the differential signal drivers 11a to 11c from a test apparatus (not shown). Next, the inspector uses the waveform detection device 30 to transmit each differential signal transmitted through the connection lines 20 a and 20 b of each differential signal receiver 17, that is, each difference input to each differential signal receiving circuit 17. The change time of each differential signal is obtained by detecting the waveform of the dynamic signal. The inspector determines a differential signal having the longest change time as a reference, and obtains a difference between the change time of the reference differential signal and the change time of another differential signal. Then, the inspector inputs the obtained shift in the change time into a drive circuit (not shown) of the digital camera.

  The drive circuit of the digital camera refers to the above-described capacitor performance measurement result obtained in advance based on the input shift time shift, and sets the switch setting that minimizes the shift time shift to each of the differential signal receivers 13a to 13a. It is determined for each of the waveform adjustment circuits 18a and 18b of 13c (excluding the waveform adjustment circuit corresponding to the reference differential signal).

  The inspector detects the waveform of the image data signal output from each differential signal receiving circuit 17 by using the waveform detection device 30 when the input of the shift of the change time is completed. Then, the inspector determines the image data signal having the longest delay time as a reference, and obtains a delay time difference between the reference image data signal and another image data signal. Then, the inspector inputs the obtained delay time deviation to the drive circuit of the digital camera.

  The driving circuit of the digital camera refers to the above-described gate performance measurement result obtained in advance based on the input delay time deviation, and sets the line setting that minimizes the delay time delay to each differential signal receiver 13a. 13c is determined for each delay circuit 19 (excluding the delay circuit corresponding to the reference image data signal).

  Next, the drive circuit of the digital camera inputs the clock signal, the waveform and frequency of which are appropriately set in accordance with the previously determined switch setting and line setting, and the serial signal receiver control signal to the drive circuit 14. The drive circuit 14 converts the received serial signal format receiver control signal into a parallel signal, and outputs the converted parallel signal format receiver control signal to the input terminals PS0 to D1 of the differential signal receivers 13a to 13c, respectively. .

  Based on the receiver control signal input from the drive circuit 14, the waveform adjustment circuits 18a and 18b of the differential signal receivers 13a to 13c turn on the switches SW1 to SW3 according to the switch setting that minimizes the change in the change time. -While turning OFF, the delay circuit 19 selects the line (delay gate) with the smallest delay time deviation. Thereby, the skew between the differential signals input to the differential signal receiving circuit 17 of each of the differential signal receivers 13a to 13c (shift in change time) and the image data output from the differential signal receiving circuit 17 respectively. The skew (delay in delay time) between signals is corrected.

  As described above, in the differential interface 10 of the present invention, not only skew correction between differential signals input to individual differential signal receivers but also skew correction between image data signals output from each differential signal receiver. It can be performed. As a result, when the differential interface includes a plurality of pairs of differential signal drivers and differential signal receivers, the occurrence of skew between signals and the occurrence of common mode noise due to the occurrence of skew are reduced. Can do.

  In the above embodiment, the first and second selection circuits 23 and 41 have been described by taking the decoder circuit and the multiplexer circuit as examples. However, the present invention is not limited to this, and the first to second selection circuits 23 and 41 are not limited thereto. Various circuits capable of turning ON / OFF the third switches SW1 to 3 and selecting the lines L1 to L3 may be used.

  The waveform adjustment circuits 18a and 18b of the above embodiment will be described by taking as an example the case where the capacitor parallel circuit 22 is provided as a circuit for adjusting the change time (time constant) of the differential signal. However, the present invention is not limited to this, and various circuits may be used as long as the change time of the differential signal can be adjusted. Furthermore, the delay time deviation between the operation signals may be corrected using the above-described delay circuit or the like.

  In the above embodiment, the case where the skew correction by the differential signal receivers 13a to 13c is performed only once in the inspection process of the digital camera has been described as an example. However, the present invention is not limited to this. Instead, the digital camera may perform skew correction constantly or periodically. In this case, the digital camera (differential interface) is provided with a waveform detection circuit for detecting the waveform of the differential signal and the image data signal, and the waveform detection is performed in the same manner as when the waveform detection device 33 performs the waveform detection. Then, the deviation of the change time and the delay time is obtained, and the obtained deviation of the change time and the delay time is input to the driving circuit of the digital camera. Thereby, skew correction can be performed constantly or periodically.

  In the above-described embodiment, the case where the skew correction between the differential signals and the skew correction between the image data signals are performed simultaneously has been described as an example, but the present invention is not limited to this. For example, after the skew correction between the differential signals is completed, the skew (delay in the delay time) between the image data signals may be detected to perform the skew correction.

  In the above embodiment, the waveform adjustment circuits 18a and 18b have been described by taking as an example a circuit that can adjust the change time of each differential signal input to each differential signal receiving circuit 17 in three stages. However, the present invention is not limited to this, and a circuit capable of adjusting the change time in two stages or four or more stages may be used. Further, as the delay circuit 19, a circuit that can increase the delay time of the image data signal by three or more stages may be used.

  In the above embodiment, the differential interface provided in the digital camera has been described as an example, but the present invention is not limited to this. For example, the present invention can be applied to differential interfaces provided in various electronic devices (devices) such as a differential interface that connects a probe of a measurement device (such as an oscilloscope) and a device main body for various measurements.

It is explanatory drawing for demonstrating the structure of a differential interface roughly. It is explanatory drawing for demonstrating schematically the structure of a skew correction operation signal receiver. It is explanatory drawing for demonstrating schematically the structure of a waveform adjustment circuit. It is explanatory drawing for demonstrating the skew correction of the differential signal by a waveform adjustment circuit. It is explanatory drawing for demonstrating switching of ON / OFF of the 1st-3rd switch by a waveform adjustment circuit. It is explanatory drawing for demonstrating the structure of a delay circuit roughly. It is explanatory drawing for demonstrating the skew correction of the image data signal by a delay circuit. It is explanatory drawing for demonstrating selection of the lines L1-L3 by a delay circuit. It is explanatory drawing for demonstrating that the waveform adjustment circuit and delay circuit of each differential signal receiver are collectively driven by one differential signal receiver drive circuit. It is explanatory drawing for demonstrating schematically the structure of a differential signal receiver drive circuit. It is explanatory drawing for demonstrating the serial-parallel conversion process of the receiver control signal by a differential signal receiver drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Differential interface 11 Differential signal driver 12 Differential signal transmission path 13 Skew correction | amendment differential signal receiver 14 Differential signal receiver drive circuit 17 Differential signal receiving circuit 18a, 18b Waveform adjustment circuit 19 Delay circuit

Claims (4)

Connected to each of a plurality of differential signal output circuits that output differential signals via a pair of differential signal transmission paths, receives the differential signals output from the differential signal output circuits, and converts them into data signals A plurality of differential signal receiving circuits,
A plurality of first skew corrections that are provided in front of each of the differential signal receiving circuits and correct the skew between the differential signals that are input to the differential signal receiving circuit via the pair of differential signal transmission paths. Circuit,
A differential circuit comprising: a plurality of second skew correction circuits which are provided in a subsequent stage of each of the differential signal reception circuits and correct skews between the data signals output from the differential signal reception circuits. Signal receiving device.   A drive circuit that receives a clock signal and a serial signal from the outside and drives the plurality of first and second skew correction circuits collectively based on a parallel signal obtained by parallelizing the serial signal in synchronization with the clock signal The differential signal receiving apparatus according to claim 1, further comprising: The first skew correction circuit includes a plurality of capacitors having different capacities, and a first selection circuit capable of individually selecting connection and disconnection between the capacitors and the pair of differential signal transmission lines,
The drive circuit drives the first selection circuit and selects the capacitors connected to the pair of differential signal transmission lines, whereby the differential signals input to the differential signal reception circuits, respectively. 3. The differential signal receiving apparatus according to claim 2, wherein a skew between the differential signals is corrected by adjusting a rise time and a fall time of the differential signal. The second skew correction circuit includes a plurality of delay gates having different delay times for delaying the data signal, and a second selection circuit capable of selecting any one of the delay gates.
The driving circuit drives the second selection circuit and selects the delay gate for delaying the data signal, thereby reducing the delay time of the data signal output from each differential signal receiving circuit. 4. The differential signal receiving apparatus according to claim 2, wherein a skew between the data signals is corrected by adjustment.

Images