JP2009170731A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small and easy to mount semiconductor device. <P>SOLUTION: There are provided: a first conductive type first semiconductor layer 12 formed on a first face of a semiconductor substrate 11; a second conductive type second semiconductor layer 13 formed on the first semiconductor layer 12; a first connective conductor 14 formed on a second face of the semiconductor substrate 11 opposite to the first face and connected to the first semiconductor layer 12; a second connective conductor 15 formed on the first face of the semiconductor substrate 11 including the second semiconductor layer 13 and connected to the second semiconductor layer 13; a third connective conductor 16 formed on at least one side face of the first connective conductor 14; and a fourth connective conductor 17 formed on the side face on the same side of the side face where at least the third connective conductor 16 of the second connective conductor 15 is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

In recent years, further downsizing and higher performance of semiconductor devices have been demanded in accordance with downsizing of electronic devices and progress in mounting technology.
A conventional semiconductor device has a semiconductor chip and a package for protecting the semiconductor chip, and the semiconductor chip mounted on the electrode material frame and wire-bonded is molded with resin.

  For this reason, the size of the semiconductor device is controlled not only by the size of the semiconductor chip but also by the size of the electrode material frame and the height of the wire, which makes it difficult to reduce the size of the semiconductor device. is there.

  Furthermore, due to the inductance components of the bonding wire and the electrode material frame, there is a problem that it takes time until the transient characteristics during voltage application (current application) are clamped and stabilized. There is a problem that the frequency characteristics of the diode for use deteriorate.

  On the other hand, as a chip scale package (Chip Scale Package), a semiconductor chip itself is also known as a package (see, for example, Patent Document 1).

  A semiconductor device disclosed in Patent Document 1 includes a chip element having a first surface on which two terminals are formed, a second surface on which one terminal is formed opposite to the first surface, and two terminals. An insulating layer formed on the first surface excluding the region, and first and second conductive layers formed on the insulating layer and connected to each terminal on the first surface and electrically separated at a predetermined interval; A third conductive layer formed on the second surface of the chip element and connected to a terminal on the second surface; and a side surface in contact with the same side surface of the chip element in the side surfaces of the first, second, and third conductive layers. Each formed electrode surface.

However, since the semiconductor device disclosed in Patent Document 1 is a three-terminal transistor and has a limited surface for forming an electrode connected to the substrate, it is difficult to form an electrode and mount it on the substrate as the size is reduced. There is. Further, there is no disclosure of a diode that is a two-terminal element.
JP 2003-273281 A

  The present invention provides a semiconductor device that is small and easy to mount.

  A semiconductor device of one embodiment of the present invention includes a first conductivity type first semiconductor layer formed on a first surface of a semiconductor substrate, and a second conductivity type second semiconductor formed on the first semiconductor layer. A first connection conductor formed on a second surface opposite to the first surface of the semiconductor substrate and connected to the first semiconductor layer; and the semiconductor substrate including the second semiconductor layer. A second connection conductor formed on the first surface and connected to the second semiconductor layer; a third connection conductor formed on at least one side surface of the first connection conductor; and at least the second connection conductor. And a fourth connection conductor formed on the side surface on the same side as the side surface on which the third connection conductor is formed.

  According to the present invention, a semiconductor device that is small and easy to mount can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a semiconductor device, FIG. 2 is a cross-sectional view showing a state in which the semiconductor device is mounted on a substrate, and FIGS. 3 to 7 are cross-sectional views sequentially showing manufacturing steps of the semiconductor device.

  As shown in FIG. 1, the semiconductor device 10 of this example is formed on a first semiconductor layer 12 of a first conductivity type formed on a first surface of a semiconductor substrate 11 and on the first semiconductor layer 12. A second conductive type second semiconductor layer 13; a first connection conductor 14 formed on a second surface opposite to the first surface of the semiconductor substrate 11; and connected to the first semiconductor layer 12, and a second semiconductor A second connection conductor 15 formed on the first surface of the semiconductor substrate 11 including the layer 13 and connected to the second semiconductor layer 13, and a third connection conductor 16 formed on at least one side surface of the first connection conductor 14. And a fourth connection conductor 17 formed on the side surface of the second connection conductor 15 on the same side as at least the side surface on which the third connection conductor 16 is formed.

  The semiconductor substrate 11 is a silicon substrate, for example. The semiconductor substrate 11 has an outer peripheral surface exposed, and functions as a package that protects the first and second semiconductor layers 12 and 13 from the outside.

For this reason, the semiconductor substrate 11 is desirably a substrate having as high a resistance as possible. For example, a non-doped high-resistance substrate, or a high-resistance substrate in which impurities are compensated by doping both P-type impurities and N-type impurities.
If the semiconductor substrate 11 is a high resistance substrate, the conductivity type of the semiconductor substrate 11 may be either P type or N type.

The first semiconductor layer 12 is, for example, a P-type semiconductor layer, and the second semiconductor layer 13 is an N ⁺ -type semiconductor layer having a carrier concentration higher than that of the P-type semiconductor layer.
The first and second semiconductor layers 12 and 13 form a diode having a PN junction in the semiconductor substrate 11.

  The first and second semiconductor layers 12 and 13 include an insulating film 18 that covers the inner wall of the trench formed in the semiconductor substrate 11 so as to surround the first and second semiconductor layers 12 and 13, for example, a silicon oxide film, The semiconductor substrate 11 is electrically isolated by an STI (Shallow Trench Isolation) 20 having an insulating material 19 embedded therein, for example, non-doped polysilicon.

  Furthermore, an insulating film 21, for example, a silicon oxide film is formed on the semiconductor substrate 11 including the outer peripheral portion of the second semiconductor layer 13. This is to ensure insulation between a first connection conductor 14 and a second connection conductor 15 described later.

  The first connection conductor 14 includes a nickel (Ni) film 22 formed on the second surface of the semiconductor substrate 11 including the inner surface of the contact hole extending from the second surface of the semiconductor substrate 11 to the first semiconductor layer 12, and a contact A copper (Cu) film 23 is formed on the nickel film 22 by filling the holes.

  The second connection conductor 15 is made of aluminum (Al) formed on the second semiconductor layer 13 with a barrier metal film (not shown), for example, a TiN / Ti film, and the outer peripheral portion overlapping the middle of the insulating film 21. ) A film 24, a nickel film 25 that covers the aluminum film 24 and has an outer peripheral portion that overlaps with the end of the insulating film 21, and a copper film 26 that is formed on the nickel film 25. .

  The copper films 23 and 26 are sufficiently thicker than the nickel films 22 and 25, for example, are formed with a thickness of about 80 μm, and constitute the main parts of the first and second connection conductors 14 and 15.

The third connection conductor 16 is a tin film formed on the entire five surfaces including at least one side surface, here, the four side surfaces and the surface of the first connection conductor 14.
Similarly, the fourth connection conductor 17 is a tin film formed on at least one side surface of the second connection conductor 15, here, the entire five surfaces including the four side surfaces and the surface.

  The four side surfaces of the third connection conductor 16 are located outside the four side surfaces of the semiconductor substrate 11 by δL, for example, about 20 to 30 μm. Similarly, the four side surfaces of the fourth connection conductor 17 are located outside the four side surfaces of the semiconductor substrate 11 by δL.

  The semiconductor device 10 functions as a package in which the outside (four side surfaces, first and second surfaces) of the high-resistance semiconductor substrate 11 protects the first and second semiconductor layers 12 and 13, The second surface functions as an electrode forming surface for connecting to the outside.

  Therefore, the semiconductor device 10 includes a substrate on which the semiconductor substrate 11 is placed, a bonding wire for connecting the first and second semiconductor layers 12 and 13 to the outside, and the first and second semiconductor layers 12 and 13. No mold resin or the like for protecting the semiconductor device 10 is required, and a miniaturized semiconductor device 10 can be obtained.

FIG. 2 is a cross-sectional view showing a state in which the semiconductor device 10 is mounted on a printed circuit board (PWB: Printed Wiring Board).
As shown in FIG. 2, the semiconductor device 10 is arranged and mounted so that the side surface 11 a of the semiconductor substrate 11 is parallel to the printed circuit board 30, similarly to chip components such as a chip capacitor and a chip resistor.

The printed circuit board 30 includes wirings 32a and 32b formed on an insulating substrate 31, and bumps 33a and 33b formed at one end of the wirings 32a and 32b that face each other at a distance.
The side surface 16a of the third connection conductor 16 is connected to the bump 33a via the solder 34a. Similarly, the side surface 17a of the fourth connection conductor 17 is connected to the bump 33b via the solder 34b.

Since the side surfaces 16 a and 17 a of the third connection conductor 16 and the fourth connection conductor 17 are outside the side surface 11 a of the semiconductor substrate 11, the semiconductor device 10 is mounted sufficiently away from the printed board 30.
Thereby, even if solder or the like hangs down in the gap between the semiconductor substrate 11 and the printed board 30, it is possible to ensure insulation between the semiconductor substrate 11 and the printed board 30.

  Since the third connection conductor 16 and the fourth connection conductor 17 are formed on the entire five surfaces of the first connection conductor 14 and the second connection conductor 15, the third connection conductor 16 and the fourth connection conductor 17 can be reliably mounted on the printed circuit board 30 regardless of which side surface is used. Can be mounted easily.

  Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 3 to 7 are cross-sectional views sequentially showing the manufacturing process of the semiconductor device 10.

First, as shown in FIG. 3A, a trench 40 having a depth of about 40 μm is formed on the first surface of the semiconductor substrate 11 by, for example, RIE (Reactive Ion Etching).
Next, a thermal oxide film 41 having a thickness of about 100 nm is formed on the semiconductor substrate 11 including the inside of the trench 40 by, for example, a thermal oxidation method.

  Next, as shown in FIG. 3B, a non-doped polysilicon film 42 is formed on the semiconductor substrate 11 by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the inside of the trench 40.

Next, as shown in FIG. 3C, the polysilicon film 42 and the thermal oxide film 41 on the semiconductor substrate 11 are removed by, for example, a CMP (Chemical Mechanical Polishing) method to expose the semiconductor substrate 11.
As a result, the thermal oxide film 41 becomes the insulating film 18 covering the inner wall of the trench, the polysilicon film 42 becomes the insulating material 19 embedded in the trench, and the STI 20 is formed.

Next, as shown in FIG. 4A, a silicon oxide film 43 is formed on the semiconductor substrate 11 including the STI 20 by, for example, a CVD method.
Next, a resist film 44 having an opening 44a is formed in a region where one semiconductor layer 12 surrounded by the STI 20 is formed, and a P-type impurity such as boron ion (B ⁺ ) is applied to the semiconductor substrate 11 using the resist film 44 as a mask. Inject selectively.
Next, after removing the resist film 44, heat treatment is performed to form the first semiconductor layer 12 which is deep P-type diffusion having a thickness of about 30 μm.

Next, as shown in FIG. 4B, a resist film 45 having an opening 45a is formed in the region where the second semiconductor layer 12 is formed, and an N-type impurity, for example, is formed in the semiconductor substrate 11 using the resist film 45 as a mask. Phosphorus ions (P ⁺ ) are selectively implanted.
Next, after removing the resist film 45, a short heat treatment is performed to form the second semiconductor layer 13 which is a shallow N ⁺ type diffusion layer having a thickness of about 1 μm.

  Next, as shown in FIG. 4C, after the insulating film 43 is removed, an insulating film 21 that is a silicon oxide film is formed on the semiconductor substrate 11 by, for example, a CVD method, and is insulated by a lithography method and an RIE method. The film 21 is selectively removed, and the second semiconductor layer 13 is exposed except for the outer peripheral portion.

Next, an aluminum film 24 whose outer peripheral portion overlaps the insulating film 21 via a barrier metal (not shown) on the insulating film 21 including the exposed second semiconductor layer 13 and an aluminum film 24 by a known method. A lower portion of the second connection conductor 15 having the nickel film 25 whose outer peripheral portion overlaps the insulating film 21 is formed thereon.
The aluminum film 24 is formed by, for example, a vacuum deposition method, and the nickel film 25 is formed by, for example, an electroless plating method.

  Next, the insulating film 21 around the nickel film 25 is removed by, for example, RIE to expose the dicing region 46 on the first surface of the semiconductor substrate 11.

  Next, as shown in FIG. 5A, the second surface of the semiconductor substrate 11 is polished and processed to a thickness of about 400 μm, and then patterned by a photolithography method using, for example, a double-side aligner, A contact hole 47 having a diameter of about 50 μm is formed from the second surface of the semiconductor substrate 11 to the first semiconductor layer 12 by RIE.

Next, the nickel film 22 is formed on the second surface of the semiconductor substrate 11 including the inside of the contact hole 47 by electroless plating.
Next, the nickel film 22 corresponding to the dicing region 46 on the first surface is selectively removed to expose the dicing region 48 on the second surface of the semiconductor substrate 11.

  Next, as shown in FIG. 5B, after forming a resist film 49 covering the dicing region 48 on the second surface of the semiconductor substrate 11 by photolithography, contacts are made by electrolytic plating using the resist film 49 as a mask. A copper film 23 having a thickness of about 80 μm is formed on the nickel film 22 so as to fill the holes 47. Thereby, the first connection conductor 14 is formed.

  Next, as shown in FIG. 6A, after forming a resist film 50 that covers the dicing region 46 on the first surface of the semiconductor substrate 11 by photolithography, the resist film 50 is used as a mask by electrolytic plating. A copper film 26 having a thickness of about 80 μm is formed on the nickel film 25. Thereby, the 2nd connection conductor 15 is formed.

Next, as shown in FIG. 6B, after the resist films 49 and 50 are removed and a thin nickel film (not shown) is formed on the surfaces of the copper films 23 and 26, the second film of the semiconductor substrate 11 is formed. The surface side is affixed to the adhesive sheet 51.
Next, the semiconductor substrate 11 is cut from the first surface side by a blade or RIE method until the remaining thickness becomes about 50 to 100 μm.

  Next, as shown in FIG. 7A, the first surface side of the semiconductor substrate 11 is attached to the adhesive sheet 52, and the semiconductor substrate 11 is cut with a blade from the second surface side. Is divided into pieces.

  Next, as shown in FIG. 7B, the entire five surfaces including the four side surfaces and the surface of the first connection conductor 14 of the singulated semiconductor substrate 11 and the four side surfaces and the surface of the second connection conductor 15 are included. A tin film of about 20 to 30 μm is formed on the entire surface by, for example, barrel plating. As a result, the third connection conductor 16 and the fourth connection conductor 17 are formed.

  Barrel plating is also called glass plating, and is a method in which a large amount of articles are placed in a barrel and electroplated while rotating. The tin film is plated on the copper film having low resistance, but is not plated on the semiconductor substrate 11 having high resistance.

  As a result, the semiconductor device 10 in which the outside of the high-resistance semiconductor substrate 11 functions as a package for protecting the first and second semiconductor layers 12 and 13 from the outside and an electrode forming surface for connecting to the outside is completed.

Since the semiconductor device 10 does not require a substrate, a bonding wire, and a mold resin, the size can be freely determined according to the purpose. For example, a small chip diode of about 0.6 × 0.3 × 0.3 mm to about 0.4 × 0.2 × 0.2 mm can be obtained.
Furthermore, since unnecessary inductance components due to bonding wires and the like are reduced, the influence on the semiconductor element characteristics can be suppressed.

  As described above, in the semiconductor device 10 of the present embodiment, the outer side of the high-resistance semiconductor substrate 11 is formed with a package for protecting the first and second semiconductor layers 12 and 13 from the outside and an electrode for connecting to the outside. It functions as a surface.

  As a result, a resin for protecting the first and second semiconductor layers 12 and 13 from the outside and a bonding wire for connecting to the outside become unnecessary. Therefore, a semiconductor device that is small and easy to mount can be obtained.

Although the case where the semiconductor device 10 is a PN junction diode has been described here, other diodes such as a PIN junction diode may be used.
A two-terminal element may be used, and for example, it can be applied to a Schottky junction diode.

  The case where the first semiconductor layer 12 and the first connection conductor 14 are connected via a via in which the contact hole 47 extending from the second surface of the semiconductor substrate 11 to the first semiconductor layer 12 is filled with the copper film 23 has been described. However, the contact hole 47 may be connected via a through hole in which a copper film is formed on the inner surface.

Sectional drawing which shows the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the state which mounted the semiconductor device based on the Example of this invention on the board | substrate. Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order. Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order. Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order. Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order. Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 12 1st semiconductor layer 13 2nd semiconductor layer 14 1st connection conductor 15 2nd connection conductor 16 3rd connection conductor 17 4th connection conductor 18, 21 Insulating film 19 Insulating material 20 STI
22, 25 Nickel film 23, 26 Copper film 24 Aluminum film 30 Printed circuit board 31 Substrate 32a, 32b Wiring 33a, 33b Bump 34a, 34b Solder 40 Trench 41 Thermal oxide film 42 Polysilicon film 43 Silicon oxide films 44, 45, 49, 50 Resist films 44a and 45a Openings 46 and 48 Dicing region 47 Contact holes 51 and 52 Adhesive sheet

Claims (5)

A first semiconductor layer of a first conductivity type formed on a first surface of a semiconductor substrate;
A second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
A first connection conductor formed on a second surface opposite to the first surface of the semiconductor substrate and connected to the first semiconductor layer;
A second connection conductor formed on the first surface of the semiconductor substrate including the second semiconductor layer and connected to the second semiconductor layer;
A third connection conductor formed on at least one side surface of the first connection conductor;
A fourth connection conductor formed on a side surface on the same side as the side surface on which at least the third connection conductor is formed of the second connection conductor;
A semiconductor device comprising:   The first semiconductor layer and the first connection conductor are connected via a via or a through hole extending from the second surface of the semiconductor substrate to the first semiconductor layer, and the second semiconductor layer and the first connection conductor are connected to each other. 2. The semiconductor device according to claim 1, wherein the second connection conductor is connected by forming the second connection conductor on the second semiconductor layer.   The first semiconductor layer and the second semiconductor layer are electrically connected to the semiconductor substrate by an insulating material embedded in a groove formed in the semiconductor substrate so as to surround the first semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor device is separated into two.   2. The semiconductor device according to claim 1, wherein the third connection conductor is formed on all side surfaces of the first connection conductor, and the fourth connection conductor is formed on all side surfaces of the second connection conductor. .   5. The semiconductor device according to claim 1, wherein side surfaces of the third connection conductor and the fourth connection conductor are located outside a side surface of the semiconductor substrate.

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