JP2009170632A - Manufacturing method of semiconductor device, and semiconductor device manufacturing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device without changing design data. <P>SOLUTION: By this manufacturing method of a semiconductor device including: a process (S1) of setting a process condition of a film based on setting data; a process (S2) of executing flattening simulation of the film based on the process condition; a process (S3) of determining presence of a dangerous part of the film from the flattening simulation; and a process (S4) of flattening the film based on the determination of the flattening simulation, a semiconductor device improved in reliability without changing design data is provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing system, and more particularly to a semiconductor device manufacturing method and a semiconductor device manufacturing system that perform planarization simulation using design data.

In recent years, simulation called DFM (Design For Manufacturing) has been applied to semiconductor device manufacturing methods.
A general method of DFM will be described below.

  First, design data called GDS (Graphic Data System) II data or CIF (Common Intermediate Format) for describing a mask pattern is input. Next, for example, based on GDSII data, an input file with wiring and the like is created, and process conditions such as mask material, film thickness, gas type, and polishing time are determined. Next, using the determined process conditions, a simulation is performed for the manufacturing process of the target semiconductor device. Next, the presence / absence of a dangerous place is determined from the simulation result of the process. If there is no dangerous part, the actual process is performed using the determined process condition. If there is an abnormal part, the GDSII data is corrected, and the above process is performed again according to the corrected GDSII data.

  Therefore, when a semiconductor device is manufactured by applying DFM, for example, the result of the simulation performed as described above is reflected in the actual manufacturing process of the semiconductor device, thereby suppressing the occurrence of a dangerous location or the like. Thus, a semiconductor device with improved reliability can be manufactured (see, for example, Patent Document 1).

  On the other hand, the completeness of copper (Cu) wiring largely depends on the completion of a CMP (Chemical Mechanical Polishing) process in the manufacturing process of the semiconductor device. Therefore, in recent years, DFM has been actively applied to the CMP process (for example, see Non-Patent Document 1).

Now, a case where DFM is applied to the CMP process will be described.
First, as described above, the CMP process is simulated using design data which is GDSII data. Then, from the simulation result of the CMP process, it is determined whether or not there is a location where the Cu wiring is extremely recessed or a danger location (hot spot) where Cu residue is likely to occur. As a result of the determination, if there is a hot spot, the design is changed or the dummy pattern is optimized. This process is repeated until there are no hot spots. In this way, by applying DFM to the CMP process, it is possible to appropriately modify the design data and manufacture a semiconductor device with no hot spots and improved reliability.
JP 2003-92237 A TH Park, “Characterization and Modeling of Pattern Dependencies in Copper Interconnects for Integrated Circuits”, Ph. D. thesis, Massachusetts Institute of Technology, 2002.

  However, in the CMP simulation, if the design data is changed so that there are no hot spots, it takes time to perform the simulation again according to the changed design data, and the throughput until mask creation is reduced. It was.

  Moreover, if it is necessary to change even the macro design as a result of the CMP simulation, it is necessary to review all the designs, and if the review is small, another problem that the chip size becomes large There was a point.

  The present invention has been made in view of these points, and an object thereof is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing system in which the reliability of the semiconductor device is increased without changing design data. To do.

In order to achieve the above object, there is provided a method for manufacturing a semiconductor device that performs flattening simulation using design data.
The method of manufacturing a semiconductor device includes a step of setting a film process condition based on setting data, a step of performing a flattening simulation of the film based on the process condition, and a risk location of the film from the flattening simulation. A step of determining the presence or absence, and a step of flattening the film based on the determination of the flattening simulation.

In order to achieve the above object, there is provided a semiconductor device manufacturing system that performs flattening simulation using design data.
The semiconductor device manufacturing system performs a process condition setting unit that sets a film process condition based on setting data, and performs a flattening simulation of the film based on the process condition to determine the presence / absence of a dangerous part of the film. And a flattening simulation unit.

In the semiconductor device manufacturing method, a semiconductor device with improved reliability is manufactured without changing design data.
In the semiconductor device manufacturing system, the process conditions of the semiconductor device with improved reliability are output without changing the design data.

  Hereinafter, as an embodiment of the present invention, an outline of the embodiment will be described, and then an embodiment based on the outline will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.

First, an outline of the embodiment will be described with reference to the drawings.
FIG. 1 is a flowchart for explaining an outline of planarization in a method for manufacturing a semiconductor device.

First, process conditions such as a thickness (film thickness) of a film to be planarized and a polishing time for the film are set based on design data of a desired semiconductor device (step S1).
Next, a planarization simulation is performed using the set process conditions (step S2).

Next, from the result of the flattening simulation, it is determined whether or not there are dangerous parts such as recesses and residues in the film (step S3).
If there is a dangerous part, the process condition is changed and a flattening simulation is performed. This process is repeated until there is no danger area. Then, the actual film is flattened using the obtained process conditions having no dangerous part (step S4).

Then, the normal semiconductor device manufacturing process is continued.
As described above, when the existence of a dangerous part of the film is confirmed by the flattening simulation, in order to eliminate the dangerous part, the process condition is changed instead of the design data, and the flattening is performed using the changed process condition. The semiconductor device with improved reliability is manufactured by performing the process. As a result, the time required for the simulation can be shortened, and it is possible to minimize a decrease in throughput until the mask is created, thereby preventing an increase in chip size.

Next, an embodiment based on this outline will be described.
In the present embodiment, a user performs a CMP simulation using a simulation apparatus, determines the film thickness of the Cu wiring and the polishing time for the Cu wiring, and manufactures the semiconductor device using the determined film thickness and polishing time. can do.

FIG. 2 is a diagram illustrating a hardware structure of the simulation apparatus according to the embodiment.
The entire simulation apparatus 100 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, and an input interface 105 are connected to the CPU 101 via a bus 106.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS program and application programs.

  A monitor 21 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 21 in accordance with a command from the CPU 101. A keyboard 22 and a mouse 23 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 22 or the mouse 23 to the CPU 101 via the bus 106.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
Next, the module configuration of the simulation apparatus 100 will be described.

FIG. 3 is a block diagram illustrating functions of the simulation apparatus according to the embodiment.
The simulation apparatus 100 includes a process condition storage unit 110, a design data storage unit 120, a design data creation unit 130, a process condition setting unit 140, and a simulation unit 150.

  The process condition storage unit 110 stores, as a database, film thickness data at various portions of the Cu wiring for each polishing time of the CMP process. This database is acquired in advance by a sample in which a groove for wiring is formed. The process condition database stored in the process condition storage unit 110 will be described later.

  The design data storage unit 120 stores design data called GDSII data created by the design data creation unit 130 for describing a mask pattern of a desired semiconductor device.

  The design data creation unit 130 creates design data of a mask pattern corresponding to a desired semiconductor device through a keyboard 21 and a mouse 23 via a monitor 21 by a user. In addition, the design data creation unit 130 stores the created design data in the design data storage unit 120.

  The process condition setting unit 140 refers to the database of the process condition storage unit 110 based on the design data stored in the design data storage unit 120, and sets the film thickness and the polishing time for the film as process conditions.

The simulation unit 150 includes a CMP simulation unit 151, a process condition change unit 152, and a design data change unit 153.
The CMP simulation unit 151 uses the process condition data set by the process condition setting unit 140 to simulate the CMP process. Further, the CMP simulation unit 151 determines the presence / absence of a dangerous portion of the Cu wiring from the result of the simulation using the process condition data, and outputs the process condition determined to have no dangerous portion.

  The process condition changing unit 152 changes the data of the process condition set by the process condition setting unit 140 when it is determined from the simulation result that there is a dangerous part in the Cu wiring.

  If the process condition change unit 152 changes the process condition data and the CMP simulation unit 151 performs the simulation, the design data change unit 153 determines that there is a dangerous part in the Cu wiring. The design data stored in 120 is changed.

  In the simulation apparatus 100 configured by the above elements, the process condition in which the simulation unit 150 performs the CMP simulation using the process condition data set by the process condition setting unit 140 and is determined that there is no dangerous part in the Cu wiring. Is output.

The output process conditions are applied to the CMP apparatus / film forming apparatus 160, and the semiconductor device is continuously manufactured.
Next, acquisition of process condition data such as film thickness and polishing time of a sample in which a wiring groove is formed, which is stored in advance in the process condition storage unit 110 will be described.

4 to 7 are schematic cross-sectional views of the main part of the sample wiring in the embodiment, and FIG. 8 is a table of measured values of the sample wiring in the embodiment.
As shown in FIG. 4, the sample wiring 200 includes a substrate 201, an interlayer insulating film 202 in which wiring grooves 202 a are formed, a barrier metal film 203, a seed film (not shown), and a plating film 204 are sequentially stacked. It is configured. It is assumed that the wiring interval of the sample wiring 200 is about 0.14 μm and the wiring area ratio is about 50%. The film thickness of each component is about 300 nm for the interlayer insulating film 202, about 10 nm for the barrier metal film 203, about 70 nm for the seed film, and about 700 nm for the plating film 204. The constituent materials are, for example, tantalum (Ta) for the barrier metal film 203 and Cu for the seed film and the plating film 204. Further, it is known that when the seed film and the plating film 204 are laminated on the interlayer insulating film 202 in which the groove 202a is formed, the thickness of the plating film 204 above the groove 202a is increased. Therefore, as shown in the figure, the plating film 204 has a raised central portion and has a step.

  For such a sample wiring 200, first, as shown in FIG. 4, the film thickness A at the end of the plating film 204 and the film thickness B at the center before the CMP process, the height C of the wiring, and the interlayer The depth D of the groove 202a of the insulating film 202 is measured. For the measurement, for example, a step measuring device, an AFM (Atomic Force Microscope) or a cross-sectional SEM (Scanning Electron Microscope) is used. Moreover, each measured value is described in time t0 of FIG.

  Next, FIG. 5 shows a case where the CMP process is performed on the sample wiring 200 from time t0 to time t1. According to this, the upper part of the plating film 204 is polished by CMP to reduce the film thickness. And the measured value of each part measured as mentioned above is described in time t1 of FIG.

  Next, FIG. 6 shows a case where the CMP process is performed on the sample wiring 200 from time t0 to time t2. According to this, all the plating films 204 on the barrier metal film 203 are polished and removed. And the measured value of each part measured as mentioned above is described in time t2 of FIG.

  Finally, FIG. 7 shows a case where the CMP process is performed on the sample wiring 200 from time t0 to time t3. According to this, the groove 202a of the interlayer insulating film 202 and the upper part of the wiring are polished, and the upper part of the wiring is removed. And the measured value of each part measured as mentioned above is described in time t3 of FIG.

  Therefore, as shown in FIG. 8, as the polishing time elapses, the film thickness A and the film thickness B at the end of the plating film 204, the height C of the wiring, and the depth of the groove 202a in the interlayer insulating film 202 are obtained. D is measured. The data measured in this way is stored in the process condition storage unit 110 as a database. Note that the data in FIG. 8 is an example, and the simulation can be performed with higher accuracy if a more detailed database such as increasing the number of measurement points is used.

  In addition to the pattern of the sample wiring 200 (wiring interval: 0.14 μm, wiring area ratio: 50%), a sample wiring having the following wiring interval and area wiring ratio patterns is similarly prepared and measured. A database for simulation was created.

Wiring interval: 0.1 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 0.14 μm, wiring area ratio: 10%, 20%, 30%, 50% (sample wiring 200), 70%, 80%, 90%
Wiring interval: 0.3 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 0.5 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 1.0 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 3.0 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 5.0 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 10.0 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
Wiring interval: 20.0 μm, wiring area ratio: 10%, 20%, 30%, 50%, 70%, 80%, 90%
In addition, the sample pattern measured using these does not limit this Embodiment, What is necessary is just to change as needed.

Next, processing for determining parameters by executing the simulation apparatus 100 will be described using a flowchart.
FIG. 9 is a flowchart illustrating a CMP simulation processing procedure according to the embodiment. The CMP simulation process performed by the simulation apparatus 100 will be described with reference to FIG.

  [Step S11] The design data creation unit 130 creates design data of a mask pattern corresponding to a desired semiconductor device through the keyboard 21 and the mouse 23 via the monitor 21 by the user. In addition, the design data creation unit 130 stores the created design data in the design data storage unit 120. In addition, as an initial setting, a change amount and a change range of process conditions to be used later are set. For example, the film thickness and the polishing time in the process conditions are set to be increased or decreased by 1% and changed to ± 10%.

  [Step S12] The process condition setting unit 140 sets a film thickness and a polishing time as process conditions while referring to the process condition storage unit 110 prepared in advance based on the design data storage unit 120.

  [Step S13] The CMP simulation unit 151 uses the process conditions set by the process condition setting unit 140 to perform a CMP process simulation on the Cu wiring.

  [Step S14] The CMP simulation unit 151 determines the presence / absence of a hot spot that is a dangerous part for the Cu wiring from the simulation result of Step S13. If it is determined that there is no hot spot, the process proceeds to step S15. If it is determined that there is a hot spot, the process proceeds to step S16.

[Step S15] The CMP simulation unit 151 outputs a process condition determined to have no hot spot as a file.
[Step S16] The process condition changing unit 152 changes the polishing time of the process condition determined to have a hot spot in step S14. The polishing time is changed according to the initial setting in step S11. For example, from the simulation result of step S13, if the polishing time is long, it is decreased by 1%, and if the polishing time is short, it is increased by 1%. Then, in the next flow, it is decreased or increased by 1% again, and is changed by 1% for each flow. However, the upper and lower limits of the change are 10%.

  [Step S17] The CMP simulation unit 151 performs a CMP process simulation using the polishing time which is the process condition changed by the process condition changing unit 152 in step S16.

  [Step S18] The CMP simulation unit 151 determines the presence or absence of a hot spot with respect to the Cu wiring from the simulation result of Step S17. If it is determined that there is no hot spot, the process proceeds to step S15, and if it is determined that there is a hot spot, the process proceeds to step S19.

  [Step S19] If it is determined in step S18 that there is a hot spot, the process condition changing unit 152 further changes the film thickness of the process condition while maintaining the change of the polishing time. The film thickness is also changed according to the initial setting in step S11. For example, in the first flow after the polishing time is changed, the process condition changing unit 152 reduces the film thickness by 1% if the film thickness is thick in the simulation result of step S17, and if the film thickness is thin, Change to increase film thickness by 1%. And in the flow repeated by step S19-step S22 after the next time, it changes so that a film thickness may be increased / decreased 1% according to the film thickness in the simulation result of the last step S20. However, the upper and lower limits of the change in film thickness are 10%.

  [Step S20] The CMP simulation section 151 performs a CMP process simulation using the film thickness that is the process condition changed by the process condition changing section 152 in step S19.

  [Step S21] The CMP simulation unit 151 determines the presence or absence of a hot spot with respect to the Cu wiring from the simulation result in step S20. If it is determined that there is no hot spot, the process proceeds to step S15. If it is determined that there is a hot spot, the process proceeds to step S22.

  [Step S22] The CMP simulation unit 151 determines whether or not the change amount of the film thickness in step S19 has reached the upper and lower limits. If it is determined that the upper and lower limits have not been reached, the process proceeds to step S19, and if it is determined that they have reached, the process proceeds to step S23. For example, when the film thickness is decreased by 1%, if the change amount of the film thickness does not reach the lower limit of 10%, the process proceeds to step S19 and the film thickness is continuously decreased. On the other hand, if the change amount of the film thickness has reached the lower limit of 10%, the process proceeds to step S23.

  [Step S23] The CMP simulation unit 151 determines whether or not the amount of change in the polishing time in step S16 has reached the upper and lower limits. If it is determined that the upper and lower limits have not been reached, the process proceeds to step S16. If it is determined that the upper and lower limits have been reached, the process proceeds to step S24. For example, when the polishing time is increased by 1% and the film thickness is changed, if the change amount of the polishing time does not reach the upper limit of 10%, the process proceeds to step S16 and the polishing time is continuously increased. . On the other hand, if the change amount of the polishing time has reached the upper limit of 10%, the process proceeds to step S24. When the process proceeds to step S16, the change amount of the film thickness is reset.

[Step S24] The design data changing unit 153 changes the design data storage unit 120 when it is determined in step S23 that the polishing time cannot be changed.
With the above flow, the obtained process conditions are applied to the CMP apparatus and the film forming apparatus, and the manufacture of the semiconductor device is continued.

  As described above, when the CMP simulation is performed by the simulation apparatus 100 and it is determined that there is a hot spot of the Cu wiring, the process condition is changed instead of the design data in order to eliminate the hot spot. A CMP process or the like is performed using the process conditions to manufacture a semiconductor device with improved reliability. As a result, the time required for the simulation can be shortened, and it is possible to minimize a decrease in throughput until the mask is created, thereby preventing an increase in chip size.

  In the present embodiment, the case where the polishing time is changed in step S16 and the film thickness is changed in step S19 has been described as an example. In addition, the film thickness may be changed in step S16, and the polishing time may be changed in step S19.

  In the present embodiment, the case of Cu wiring has been described as an example based on design data as a target of the CMP process. In addition, STI (Shallow Trench Isolation) or the like instead of Cu wiring, or EB (Electron Beam) exposure data may be applied instead of design data.

(Appendix 1) A step of setting the film process conditions based on the setting data;
Performing a planarization simulation of the film based on the process conditions;
Determining the presence or absence of a dangerous part of the film from the planarization simulation;
Performing the planarization of the film based on the determination of the planarization simulation;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 2) When the presence or absence of the dangerous part is determined, and it is determined that the dangerous part is present, the process condition is changed, and the flattening simulation is performed again based on the changed process condition,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing planarization based on the process condition determined to have no dangerous part when it is determined that the dangerous part does not exist.

(Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 2, wherein the design data is changed when the dangerous part does not disappear.
(Additional remark 4) The said process conditions are the film thickness of the said film | membrane planarized by the said planarization simulation, and / or the grinding | polishing time of the said film | membrane, Any one of the additional marks 1 thru | or 3 characterized by the above-mentioned. Semiconductor device manufacturing method.

(Additional remark 5) EB exposure data are used instead of the said setting data, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned.
(Additional remark 6) The process condition setting part which sets the process condition of a film | membrane based on setting data,
A flattening simulation unit that performs the flattening simulation of the film based on the process conditions and determines the presence or absence of a dangerous portion of the film;
A semiconductor device manufacturing system comprising:

(Additional remark 7) When the said flattening simulation part judges the presence or absence of the said dangerous part and it is judged that the said dangerous part exists, the said process condition setting part changes the said process condition, The said flattening simulation part Performs the flattening simulation again based on the changed process conditions,
7. The semiconductor device manufacturing system according to appendix 6, wherein when it is determined that there is no dangerous part, the flattening unit performs flattening based on the process condition determined that there is no dangerous part.

  (Supplementary note 8) The semiconductor device manufacturing system according to supplementary note 7, further comprising a design data changing unit that changes the design data when the dangerous part does not disappear.

It is a flowchart figure explaining the outline | summary of the planarization in the manufacturing method of a semiconductor device. It is a figure which shows the hardware structure of the simulation apparatus in embodiment. It is a block diagram which shows the function of the simulation apparatus in embodiment. It is a principal part cross-sectional schematic diagram (1) of the sample wiring in embodiment. It is a principal part cross-sectional schematic diagram (2) of the sample wiring in embodiment. FIG. 6 is a schematic cross-sectional view (No. 3) of relevant parts of the sample wiring in the embodiment. FIG. 4 is a schematic cross-sectional view (No. 4) of relevant parts of a sample wiring in the embodiment. It is a table | surface of the measured value of the sample wiring in embodiment. It is a flowchart figure which shows the process sequence of CMP simulation in embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Simulation apparatus 110 Process condition storage part 120 Design data storage part 130 Design data creation part 140 Process condition setting part 150 Simulation part 151 CMP simulation part 152 Process condition change part 153 Design data change part 160 CMP apparatus and film-forming apparatus

Claims (6)

A step of setting film process conditions based on the setting data;
Performing a planarization simulation of the film based on the process conditions;
Determining the presence or absence of a dangerous part of the film from the planarization simulation;
Performing the planarization of the film based on the determination of the planarization simulation;
A method for manufacturing a semiconductor device, comprising: If it is determined that there is the dangerous part by determining the presence or absence of the dangerous part, the process condition is changed, and based on the changed process condition, the flattening simulation is performed again,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing flattening based on the process condition determined to have no dangerous part when it is determined that there is no dangerous part.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the design data is changed when the dangerous part does not disappear.   4. The semiconductor device according to claim 1, wherein the process condition is a film thickness and / or a polishing time of the film that is planarized in the planarization simulation. 5. Manufacturing method. A process condition setting unit for setting film process conditions based on the setting data;
A flattening simulation unit that performs the flattening simulation of the film based on the process conditions and determines the presence or absence of a dangerous portion of the film;
A semiconductor device manufacturing system comprising: When the flattening simulation unit determines the presence or absence of the dangerous part and determines that the dangerous part is present, the process condition setting unit changes the process condition, and the flattening simulation unit changes Based on the process conditions, perform the planarization simulation again,
6. The semiconductor device manufacturing system according to claim 5, wherein, when it is determined that there is no dangerous part, the flattening unit performs flattening based on the process condition determined that there is no dangerous part.

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