JP2013236031A - Defect classification device, and defect classification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for creating a reference layout supporting double patterning exposure, and comparing a sample image with the reference layout to classify defects.SOLUTION: A defect classification method includes a step of matching an image for inspection 64 that is an image of a pattern of a sample obtained by a defect inspection device or a defect reviewing device, with a reference layout 63 that corresponds to the pattern created on the basis of design data, so as to classify defects that occur in the pattern. The reference layout 63 is created by adding or subtracting design layouts 60 and 61 of a plurality of layers to/from the design data.

Description

  The present invention relates to a defect classification device and a defect classification method. In particular, the present invention relates to semiconductor defect classification for classifying defects including systematic defects in a wafer or chip in the process of manufacturing a semiconductor device.

  Conventionally, the main cause of yield reduction in semiconductor pre-process wafer manufacturing is foreign matter randomly generated on the semiconductor wafer. The cause is investigated by defect inspection equipment and defect review equipment and measures are taken in the manufacturing process. Was able to be maintained. However, in recent years, the pattern minimum line width of semiconductor devices has been miniaturized from 32 nm and beyond, and the ratio of defects depending on the design layout has increased. This layout-dependent defect is called a systematic defect.

  In order to reduce defects in the semiconductor wafer, inspection is performed by a defect inspection apparatus during the manufacturing process. Based on the defect position information detected by the inspection device, a clear image of the defect is acquired by the review device, ADC (Automatic Defect Classification) is performed to automatically classify the defect based on this image, and the classified defect category Measures are taken to reduce the defect rate according to the frequency.

  However, the conventional ADC classification is limited to the category classification based on the defect shape and brightness observed by the review apparatus, and the cause of the occurrence of the systematic defect due to the layout cannot be investigated. Therefore, recently, a technique for classifying defects using design layout data is required.

  In addition, with the miniaturization, double patterning is used as a recent lithography technique. This double patterning includes a LELE (Litho-Etch-Litho-Etch) method and a SADP (Self-Aligned Double Patterning) method. In conventional lithography, exposure is performed with one mask, whereas in double patterning, two divided masks are used and exposure is performed twice in succession.

  By dividing the mask into two, the design layout of one mask can be simplified. Further, in the exposure, there is a merit that a high resolution can be realized by performing the second exposure between the lines of the first exposure pattern, and it has been used in a manufacturing process of a layer having a high pattern density.

  For this reason, a technique for matching the image to be inspected with the design layout data corresponding to double patterning is required.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses that in a technique for measuring a pattern by comparing design layout data and an image, resist positive / negative discrimination information is added to the design layout data.

JP 2006-215077 A (US2006 / 0169896)

  As described above, systematic defect classification corresponding to double patterning exposure is necessary. In double patterning, exposure is performed using two or more design layouts. Therefore, when the defect is classified by comparing the design layout and the image, it is necessary to generate a reference layout corresponding to the pattern image of the sample using two or more design layouts.

  In Patent Document 1, it is reported that layout information using positive and negative information of a design layout is used for matching. However, a specific matching process corresponding to double patterning is not described.

  An object of the present invention is to provide an apparatus or method that realizes highly accurate defect classification by generating a reference layout corresponding to a pattern image of a sample using a design layout of two or more layers. is there.

  In order to solve the above problems, the present invention provides an image to be inspected that is an image of a pattern of a sample obtained by a defect inspection apparatus or a defect review apparatus, and a reference for a pattern corresponding to the pattern generated based on design data. In the defect classification method or the defect classification apparatus for classifying defects generated in the pattern by matching the layout, the reference layout is generated by adding or subtracting the design layout of a plurality of layers in the design data. It is characterized by.

  With the above configuration, it is possible to realize highly accurate defect classification by generating a reference layout corresponding to a pattern image of a sample using a design layout of two or more layers.

The figure which shows the whole structure of a defect classification system. The figure which shows a defect classification | category procedure. The figure which shows an example of a layer process information file. The figure explaining the production | generation process of the reference | standard layout in a double patterning LELE (Litho-Etch-Litho-Etch) system. The figure which shows the design layout in a double patterning SADP (Self-Aligned Double Patterning) system. The figure explaining the production | generation process of the reference | standard layout in a double patterning SADP system. The figure which shows the user screen in a defect classification device. The figure which shows the matching procedure of a to-be-inspected image and a design layout. The figure which shows the output file of a matching result.

Hereinafter, embodiments of the present embodiment will be described with reference to the drawings.
In the following, a configuration example of a defect classification system having a function of performing systematic defect analysis based on the acquired sample pattern image will be described. However, the configuration of the system is not limited to this, and part or all of the devices constituting the system May be a common device.

  The processing described below can be realized by either hardware or software. When configured by hardware, it can be realized by integrating a plurality of arithmetic units for executing processing on a wiring board or in a semiconductor chip or package. When configured by software, a program for executing desired arithmetic processing by a central processing unit (CPU) mounted on a device constituting the system or a general-purpose CPU mounted on a general-purpose computer connected to the system. It can be realized by executing. It is also possible to upgrade an existing apparatus with a recording medium in which this program is recorded.

  The overall configuration of the defect classification system of the present embodiment will be described with reference to FIG. The semiconductor manufacturing process is usually in a clean room 8 kept in a clean environment. In the clean room 8, a defect inspection apparatus 1 for inspecting defects of product wafers is installed. The defect inspection apparatus 1 is an optical dark field defect inspection apparatus, an optical bright field defect inspection apparatus, an electron beam defect inspection apparatus, or the like, and detects defects generated on the surface of a device to be inspected. Further, the defect inspection apparatus 1 may have a function of acquiring a review image (inspected image 10) that is a high-magnification image of a detected defect. In the clean room 8, a review device 2 that observes defects at a higher magnification than the defect inspection device 1 is installed based on the coordinate information of the defects detected by the defect inspection device 1. As the review device 2, an electronic defect review device is mainly used. The electronic defect review apparatus is an apparatus that can obtain an image with higher image quality and higher magnification than a defect inspection apparatus by using a scanning electron microscope (SEM). Note that the review device 2 may have a defect inspection function.

  Moreover, the defect information server 3 which preserve | saves the data of these defect inspection apparatuses 1 and the review apparatus 2 is installed.

  A personal computer 14 is installed in the office 13. The personal computer 14 can confirm information such as a design layout and a process. The user creates the layer process information 15 and inputs information such as the layer flow into the file. Note that the layer flow is layer information used in each manufacturing process. The layer process information 15 will be described later with reference to FIG.

  In this embodiment, the personal computer 14, the defect classification device 4, and other devices are connected via the communication network 6. A design database server 5 is also connected to the communication network 6. The design database server 5 stores a design layout 7 of a semiconductor device to be subjected to defect inspection, and the defect classification device 4 can obtain the design layout 7 through the communication network 6.

  Next, the data flow between the devices in FIG. 1 will be described. Defect data 9 (including information such as defect coordinates and categories detected by the defect inspection apparatus 1) and an image to be inspected 10 (in the defect inspection apparatus 1 or the review apparatus 2) obtained by the defect inspection apparatus 1 or the review apparatus 2 A series of data including an image of each defect acquired) and an image information file 11 (including information such as an image acquisition condition of the image to be inspected 10) are referred to as defect information 12, and these are referred to as defect information server 3. Send to.

  As preparation for performing defect classification, the defect information 12 stored in the defect information server 3 is sent to the defect classification device 4. Further, the design layout 7 of the target sample pattern is sent from the design database server 5 to the defect classification device 4. Further, the layer process information 15 created by the personal computer 14 is sent to the defect classification device 4.

  Next, the system configuration of the defect classification device 4 in FIG. 1 will be described. The defect classification device 4 is configured by a workstation, a personal computer, or the like, and has a function of classifying systematic defects from defects detected by the defect inspection device 1 and the review device 2. Specifically, the network interface 20 for exchanging data with other devices, the main storage device 21 for storing the design layout 7, the defect information 12, the layer process information 15 and the like, and the layer process information acquired from the personal computer 14 15 includes a layout conversion operation unit 22 that performs conversion, generation, and composition processing so that information such as layer flow from 15 and the design layout 7 acquired from the design database server 5 can be read into the system. A matching processing unit 23 for performing alignment, a sampling unit 24 for selecting whether or not the target systematic defect is based on category information such as a defect type and a defect size of the defect information 12, and a defect area and a reference layout in the inspected image 10 And a superimposition processing unit 25 that superimposes A defect classification unit 26 that classifies defects by determining the overlapping state of the recessed area and the layout pattern, a layout characteristic calculation unit 27 that obtains the characteristics of the design layout 7 such as the pattern density of the design layout 7, display of layout data, etc. A user interface 28 such as a keyboard, a mouse, and a display for inputting contents is provided. 21-27 are collectively referred to as an arithmetic control unit. Note that not all functions included in the arithmetic control unit need be implemented in the defect classification apparatus, and some functions may be executed by different apparatuses.

  FIG. 2 is a diagram showing an outline of the defect classification procedure of this embodiment. The flow described below is performed by the defect classification device 4 described above.

  First, the design layout 7 is input (S101), the defect information 12 is input (S102), and the layer process information 15 is input (S103), and the layout conversion calculation unit 22 performs preprocessing such as graphic conversion and format conversion. I do.

  Next, the layer definition (S104) of the design layout 7 is performed. The layer definition (S104) is a process of combining these into one layer based on the information input from the layer process information 15 (S103). Unlike the design layout generation (S106) corresponding to double patterning, which will be described later, the synthesis process here is a process of simply adding a design layout without defining a positive / negative. This process is performed in order to accurately perform the origin adjustment in the next step 105 when a plurality of layer numbers and design layouts 7 of a plurality of data types are used in one manufacturing process. This processing is similarly performed by the layout conversion calculation unit 22.

  Next, the origin alignment of the defect information 12 and the design layout 7 is performed (S105). The design layout 7 has the origin at the center of the die, and the defect information 12 has the coordinate system of the design layout 7 and the defect information 12 actually obtained from the defect inspection apparatus and review apparatus as in the case where the origin is the lower left corner of the die. May be different. By aligning the origin of the design layout 7 and the defect information 12 at the same pattern position at the same place, these two coordinate systems can be made the same. The coordinate system may be unified with the coordinate system of the design layout, or may be unified with the coordinate system of the defect information. A new coordinate system may be used. It is also possible to input coordinates of this error on the user interface 28. Also, the origin position can be specified on the design layout display screen.

  Next, design layout generation corresponding to double patterning is performed (S106). Here, in order to match the shape of the design layout 7 to the pattern exposed by double patterning so as to correspond to the pattern of the image to be inspected, a reference layout is generated using the design layout 7 of a plurality of layers.

  In order to generate the reference layout, the user interface 28 can generate the reference layout while confirming the actual inspected image.

The reference layout is an ideal pattern layout corresponding to the pattern of the inspected image, and this reference layout is used for comparison processing with the inspected image for defect classification.
The processing contents in S106 will be described later with reference to FIGS.

Next, matching between the inspection image 10 and the reference layout is performed for each defect (S107).
Since the coordinate systems are matched by the processing in S105, the coordinate system is moved to a position corresponding to the inspection image 10 on the reference layout based on the defect coordinates. However, there are many cases where the defect coordinates detected by the defect inspection device are misaligned, and here the search is performed in a wider range than the field of view of the acquired image and pattern matching is performed, so that the position of the defect is indicated on the reference layout. Identify. The processing of S107 is performed by the matching processing unit 23.

  Next, sampling based on the ADC classification category by the review apparatus (S108) is performed. For example, by filtering random defects such as foreign matters and scratches, only categories that may be systematic defects such as short defects and open defects can be extracted as targets for the following analysis. Note that the matching (S107) and sampling (S108) can be performed in reverse order. The processing of S108 is performed by the sampling unit 24.

  Next, superimposed display (S109) of a predetermined layer of the inspected image 10 including an arbitrary defect and the design layout 7 is performed. Here, the “predetermined layer” means a layer to be inspected and other layers located in the upper layer and the lower layer, and a plurality of layers can be selected. By selecting a layer that is likely to cause a defect and displaying it in a superimposed manner, the influence of the defect on the pattern of the layer can be visually confirmed. This process is performed by the superimposition processing unit 25.

  Next, automatic classification (S110) based on the overlap state of the defect and the layout pattern is performed using the inspected image 10 and the reference layout. Here, the automatic classification is to classify a defect that may be a systematic defect in more detail. This process is performed by the defect classification unit 26. For example, when the inspection target layer is a PolySi layer, there are layers such as an N-type or P-type active region and a field region in the lower layer. Using these layers, defects can be classified in detail, or classified based on pattern information such as cells, peripheral circuits, and dummy patterns.

  Finally, layout characteristics such as pattern density, area ratio, minimum space dimension, and minimum line width in the vicinity of the defect are obtained (S111). The layout characteristic is a feature of the pattern of the design layout 7. Based on this result, it is possible to determine whether or not it is a systematic defect. The systematic defect is often a defect that occurs due to the design layout, and it is effective to analyze the cause of the systematic defect by obtaining the layout characteristics. This process is performed by the layout characteristic calculator 27.

  FIG. 3 shows an example of a layer process information file. The layer process information file 15 is a file that stores the following information as preparation before matching or defect classification. However, it is not always necessary to store all of these pieces of information, and any file in which the design layout and the manufacturing process are associated with each other may be used.

  FIG. 3 shows an example of a file. Layer flow (Flow), layer definition (Layer Name, LayerNo_DataType), positive / negative (P / N), processing information (Process), dummy pattern (Dummy), double patterning (DP) ), Information such as addition / difference (Add / Dif).

  A layer flow (Flow) means the order of processes in which each layer is used, and a determination is made by numerical input.

  The layer definition (Layer Name, LayerNo_DataType) is information for combining a plurality of layers of the design layout 7 into one layer in S104. In the design layout 7, layers are managed by layer numbers and data types, but this information is necessary because design data of a plurality of data types may be used even in one manufacturing process.

  The positive / negative (P / N) can be set for each layer number and data type of the design layout, and is selected to be the same as the pattern formation on the target wafer. That is, positive / negative (P / N) information is given for each layer.

  Processing information (Process) contains information on processing contents such as lithography, etching, and implantation, and is handled as process information of the layer.

  The dummy pattern (Dummy) is information indicating whether or not it is a dummy pattern. In multi-layer wiring processes, etc., by forming dummy patterns in areas where wiring patterns are sparsely distributed, it is possible to ensure flatness of interlayer insulating films and the like, and to improve processing accuracy Yes. However, the defects present on the dummy pattern are less likely to have a direct influence on the yield and can be excluded from the analysis target. This is effective when sampling the analysis target.

  Double patterning (DP) is information for recognizing a layer exposed by double patterning. Based on this information, the user can register in advance information necessary for the layer calculation processing corresponding to the double patterning described below.

  FIG. 4 is a diagram showing a reference layout generation process in the double patterning LELE (Litho-Etch-Litho-Etch) method. As described above, since double patterning uses two or more design layouts, it is necessary to generate a reference layout that is an ideal shape of a pattern on a wafer using these two design layouts.

  For example, a case where a pattern on the wafer such as the pattern 56 is generated using the design layout A and the design layout B will be described. From the layout A, it is possible to generate either data of the positive 50 pattern and the inverted negative 51 pattern. Here, the positive 50 is selected so as to have the same shape as the pattern 56 on the wafer. Similarly, regarding the layout B, the positive 52 is selected from the positive 52 and the negative 53. Here, a design layout is created by using the positive 50 of the layout A and the positive 52 of the layout B. The selection of positive / negative is determined by how the pattern appears in the inspected image. Next, an overlay layout 54 is obtained by superimposing the two layouts selected here. However, a shape similar to that of the pattern 56 cannot be obtained simply by superimposing them as they are.

  Therefore, the calculation method of the selected layouts A and B is determined, and the calculation process is performed between the selected layouts. Specifically, it is determined whether to perform layout A + B (addition of the two layouts A and B) or A-B (subtract B from layout A). Here, the reference layout 55 is obtained by subtracting the pattern difference of the layout B (A−B), and can be matched to the shape of the sample pattern 56. This allows subsequent matching processing. As described with reference to FIG. 4, it may be necessary to perform subtraction processing of a plurality of design layouts in particular in order to cope with double patterning. Although not described in detail here, for example, a process of subtracting A from the layout B is also possible.

  FIG. 5 is a diagram showing a design layout in a double patterning SADP (Self-Aligned Double Patterning) system.

  In the SADP method, etching is required twice, and since a process of depositing a spacer thin film by CVD (Chemical Vapor Deposition) is used, there is a process that does not require a design layout (here, a mask). Since a pattern is not formed only by exposure and etching as in the past, it is difficult to create a shape similar to a pattern only with an existing design layout.

  Therefore, in the SADP method, it is necessary to form a reference layout 63 corresponding to the pattern 64 from the existing design layout C60 and design layout D61. In the method of FIG. 4 described above, it is difficult to create the reference layout 63. Therefore, by using the design layout C60 and the design layout D61 and performing the enlargement / reduction process before these two addition or subtraction processes, a process for generating a new reference layout is performed, thereby generating the reference layout 63. To do. Next, this process will be described.

  FIG. 6 is a diagram illustrating a process of generating a reference layout in the double patterning SADP method. This will be described using the design layouts C and D shown in FIG. However, for the sake of clarity, the description here will be made by a method of forming a pattern 77 of two lines as a basic unit.

6 shows a method of generating a layout c ₃ 76 (reference layout 63 in FIG. 5) by performing arithmetic processing using the layout c70 (design layout C60 in FIG. 5) and layout d71 (design layout D61 in FIG. 5). Is shown. Hereinafter, the content of this calculation process will be described in detail.

  First, in the case of a quadrangle such as the layout c70, the coordinate data of the layout has coordinate information of vertices at four corners. For this reason, it creates based on this coordinate.

The layout c ₁ 72 is enlarged by a value X ₁ corresponding to a pattern dimension (here, dimension X ₁ 78) processed on an actual wafer. Up from the coordinates of the four corners of the layout c70 right and left sides in the X-axis direction by the width of the X ₁ to perform the deformation of the layout.

Next, the difference between the layout c ₁ 72 changed to the layout (c ₁ -c) 73 and the layout c 70 is taken.

Layout c ₂ 74 is the result obtained by subtracting the difference. This completes the calculation process in the X direction.

Next, as shown by the layout (c ₂ −d) 75, the difference between the layout c ₂ 74 and the layout d71 is taken. Note that the difference here is to cancel the overlapping portion of the layout c ₂ 74 and the layout d 71.

The layout c ₃ 76 is a result obtained by the difference. From this result, a reference layout corresponding to the pattern 77 is obtained. In practice, a repeatable pattern can be formed by repeating this with a plurality of patterns. Thus, the subsequent matching process can be performed. As described above, also in the case of SADP double patterning, as in the case of the LELE method, it is necessary to perform subtraction processing of a plurality of design layouts in order to cope with double patterning.

  FIG. 7 is a diagram showing a user screen 80 in the defect classification apparatus. This screen is particularly used as a condition setting screen when generating a reference layout for double patterning.

  As shown in FIG. 7, the user screen 80 includes layer information 81 such as layer and process information, a design layout 82, an inspected image / superimposed image 83, a positive / negative button 86, an add / difference button 87, an enlargement / reduction value. An input box 88 or the like is displayed.

  The layer information 81 displayed on the left side of the screen is a screen 81 for displaying and setting the layer flow, the layer definition, the positive / negative, the processing information, the dummy pattern, and the double patterning, which are information obtained from FIG. is there. Here, it is also possible to confirm the setting of the positive / negative of the target layer and the conditions for addition / difference between layers.

  A design layout 82 displayed at the center of the screen is an image generated based on the design layout 7. As the design layout 82, the design layout of the selected layer may be displayed simply superimposed, or a reference layout generated by computing the design layout as described in FIGS. 4 and 6 is displayed. Also good. While looking at the screen, it is possible to confirm the design layout and change the layer to be superimposed.

  The right inspection image / superimposed image 83 is a review image acquired by the review device 2 or the like, and is displayed based on the inspection image 10 included in the defect information 12. Further, the inspection button and the superimposed image can be switched by the switching button 84. The superimposed image is a display in which the design layout 82 and the inspected image 10 are superimposed. By superimposing these images, it is easy to determine whether the image to be inspected matches the reference layout.

  The up / down buttons 85 are used to change the display order of the layers in the layer information 81. It is possible to change the order of the layers by pressing the upper and lower buttons after selecting the layer on the layer information 81.

  The positive / negative button 86 is used to switch the display of the positive and negative of each layer. A method for directly specifying a layer to be subjected to positive / negative switching in the layer information 81 or a layer to be subjected to positive / negative switching in the design layout 82 and then pressing the positive / negative button to select the positive / negative. Switch to display.

  The add / difference button 87 is a button for setting an arithmetic processing method for generating a reference layout from a plurality of target layers. That is, it is a button for setting whether a plurality of target layers are added together or generated as a difference. The user can select an arithmetic processing method while viewing the design layout screen 82.

  In the layout enlargement / reduction value input box 88, an instruction to input a layout enlargement ratio or reduction ratio can be given. Here, the enlargement and reduction of the layer described in FIG. 6 can be set in the X direction and the Y direction, and can be input as a sign and a numerical value.

  In this way, on this user screen, you can easily set the standard layout generation conditions by selecting the layer used to generate the standard layout, changing the standard layout, setting the calculation processing method for generating the standard layout, etc. it can.

  FIG. 8 is a diagram showing in detail a procedure for generating a reference layout corresponding to double patterning, an image to be inspected, and a matching procedure. This is a detailed description of the procedure for design layout generation (S106) corresponding to double patterning in FIG. Note that S104, 105 and S108-S111 in FIG. 2 are omitted from the flow.

  First, defect position recognition (S201) is performed from information such as an image and a category input by inputting defect information (S102). 1 includes a secondary electron image 31, a reflected electron image (Left) 30, and a reflected electron image (Right) 32. A reference image is generated from these images, and the image to be inspected and this reference are generated. A difference is obtained from the image, and the defect position is recognized using the difference as a defect. Alternatively, when the review device 2 acquires an image, a reference image may be acquired at the same time, and the difference may be obtained using this. Here, the reference image is an image to be compared with the inspected image 10 when a defect is detected.

  Next, in the defect mask (S202), an area recognized at the obtained defect position is generated as a defect mask. The defect mask is a defect mask image showing a difference between the image to be inspected and the reference image.

  Next, in image selection (S203), a secondary electron image 31, a reflected electron image (Left) 30, and a reflected electron image (Right) 32 are used in order to recognize a pattern and a space portion in the subsequent process (S207). Select which image to use from one image. One image may be processed, or an image obtained by combining a plurality of images may be used.

  Next, in the edge determination (S204), the line edge that separates the pattern and the space portion is recognized. Here, an image including a defect may be used, or edge determination processing may be performed from an image obtained by subtracting only the defective portion from the defect mask.

  Next, in the brightness determination (S205), the brightness in the inspected image is obtained. Specifically, a frequency distribution of brightness (pixel value) in the image to be inspected is obtained and separated into two or more frequency distributions with an appropriate threshold determined from the frequency distribution. Each separated frequency distribution corresponds to the brightness of the pattern or space portion. A pattern and a space can be determined from the frequency distribution of brightness (pixel value) in the image to be inspected.

  Next, in the layer setting (S206), it is selected whether the target layer is a single layer or a multilayer layer. In the case of a multilayer layer, first, the upper layer and the lower layer are separated, and then the brightness of the pattern and space is individually recognized. Note that S205 and S206 may be performed in the reverse order.

  Next, in pattern / space recognition (S207), the pattern portion and the space portion are finally recognized from the state of these processes. Specifically, the user sets which brightness the pattern portion corresponds to from the pattern and space area in which the edge is recognized in S204 and the brightness information obtained in S205. Further, if the material of the sample is known in advance and it is known which of the pattern portion and the space portion looks bright, it can be automatically recognized.

  Next, the generation of the reference layout will be described in detail. S208 to S219 described below may be performed in parallel with the processing of S201 to S207 described above.

  First, after inputting a design layout (S101) and layer process information (S103), matching layer selection (S208) is performed. Since layer information such as layer flow and layer definition (Layer No, Layer Name) has already been input in the layer definition (S104) of the design layout, here one or more layers used for matching in S107 in the subsequent stage Make a selection. By inputting this information in the layer process information (S103) in advance, the defect classification device 4 can be automatically set based on the information.

  Next, in a double patterning determination step (S209), it is determined whether or not the target layer is a layer exposed using double patterning. This can be determined based on the layer process information.

  When the double patterning is not used, the positive / negative information of the target layer is acquired (S210) after S209. The design layout of the target layer has a layer number and a layer type, and positive / negative can be set for each layer number.

  On the other hand, when double patterning is used, the positive / negative information acquisition (S211) of a plurality of layers is performed after S209. Since two design layouts are required as described above, positive / negative information is acquired for each design layout of each layer. Although the description here is for the case of two design layouts, it is also possible to add more layouts.

  Next, in double patterning method selection (S212), it is determined whether or not the original design layout shape is to be modified before adding or subtracting a plurality of design layouts according to the double patterning method. There are two types of double patterning: the LELE method and the SADP method. As described above, the original layout shape is used as it is as in the LELE method, and if addition / subtraction is possible, No, and the original pattern as in the SADP method. If the layout shape is changed to a new shape and addition / subtraction is performed on the deformed shape, Yes is selected. This selection is performed by the calculation method setting means provided in the defect classification apparatus of this embodiment. The calculation method setting means may be a GUI displayed on the screen, and the user may select a double patterning method while viewing the GUI. The calculation method setting means may automatically set the calculation method by reading the double patterning method from the layer / process information file stored in advance.

  Next, in the enlargement / reduction process (S213), the pattern can be expanded or reduced with respect to the specified pattern, and the size can be changed while considering the actual pattern dimensions, and a new pattern can be generated. It is. Also, a new pattern can be generated here. The pattern newly generated in S213 is, for example, 72 in FIG.

  Next, in the overlay with the generated layout (S214), the layout newly generated in S213 and the original design layout before the enlargement / reduction processing in S213 are overlapped, and it is determined whether these are added or subtracted. I do. Here, the original design layout before the enlargement / reduction processing in S213 is, for example, 70 in FIG.

  Next, in addition / subtraction processing (S215), after setting whether to perform processing based on the generated layout or the original layout, addition or subtraction processing is performed. Thus, for example, 74 in FIG. 6 is generated.

  Next, in the overlay with another layout (S216), it is determined whether or not the newly generated layout is to be overlaid with another existing layout. Here, the other existing layout is, for example, 71 in FIG. Further, the superposition state in S216 is, for example, 75 in FIG.

  Next, in addition / subtraction processing (S217), after setting which layout of the two layouts is to be executed, addition or subtraction processing is performed. Thereby, for example, 76 in FIG. 6 is generated.

  Through the above processing, the processing for generating the reference layout of the ideally shaped pattern corresponding to the pattern to be inspected by performing arithmetic processing on the plurality of layers is completed (S218).

  Next, in line / space recognition (S219), the pattern / space relationship is recognized from the positive / negative information obtained in S210 and S211. For example, in the flow after S211 in which double patterning is performed, layout generation and addition / subtraction processing are newly performed, so the shape of the layout changes from that of S211. Therefore, after completion of the multi-layer processing (S218), it is necessary to finally recognize the pattern / space. Since the layout is created so as to correspond to the pattern to be inspected, a portion generated as a pattern shape is recognized as a pattern, and a portion having no pattern is recognized as a space. The same recognition is performed in the flow of S210.

  In the matching between the image to be inspected and the design layout (S107), matching is performed based on the result of the pattern / space recognition (S207) obtained from the defect information and the result of the pattern / space information (S219) of the design layer. If matching is performed without recognizing the pattern / space, the pattern portion may be shifted by a half pitch, and the pattern portion may be matched with the space portion. However, according to this method, matching can be performed without shifting by a half pitch. It is possible to improve performance.

  FIG. 9 is a diagram showing an example of an output file after matching between the image to be inspected and the design layout.

  The output file 90 includes defect ID (#ID), die XY coordinates (X, Y), in-die XY coordinates (coordinates at the time of inspection) (DieX, DieY), in-die XY coordinates (coordinates after matching) (C_DieX, C_DieY ), Defect size XY (sizeX, sizeY), defect classification result (Defect Class), and other information. Here, as the in-die XY coordinates (coordinates after matching), coordinates based on the design layout are output. Regarding this coordinate, the origin coordinate can be output in two ways. One is a coordinate system based on the inspection origin used in the defect inspection apparatus 1 or the review apparatus 2, and the other is the origin of the design layout 7 (mostly the center of the die is the origin). Both outputs are possible. Using this data, the processing after S108 described above is performed to identify a systematic defect.

  As described above, according to the present invention, the image to be inspected of the sample exposed by the double patterning method is image-matched with the reference layout generated by calculating a plurality of design layouts. Thereby, the matching failure rate is reduced, and as a result, the efficiency of matching is improved. Furthermore, it becomes possible to easily and efficiently classify systematic defects that have become a problem in recent fine devices, and to improve the efficiency of defect factor analysis. This makes it possible to quickly increase the yield during semiconductor device development, prototyping, and mass production.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

60 Design Layout C
61 Design Layout D
62 Reference layout generation 63 Reference layout 64 pattern

Claims (8)

Occurs in the pattern by matching the image to be inspected, which is an image of the pattern of the sample obtained by the defect inspection apparatus or the defect review apparatus, with the reference layout of the pattern corresponding to the pattern generated based on the design data In a defect classification device for classifying defects to be
A defect classification apparatus comprising: an operation control unit that generates the reference layout by adding or subtracting design layouts of a plurality of layers in the design data. The defect classification apparatus according to claim 1,
The pattern is a pattern manufactured by being exposed by a double patterning method,
A defect classification apparatus comprising: an arithmetic method setting unit capable of changing a generation method of the reference layout based on a double patterning exposure method. The defect classification apparatus according to claim 2,
When the exposure method is the first method, the reference layout is generated by adding or subtracting the design layout of the plurality of layers as it is,
When the exposure method is the second method, at least one of the plurality of layer design layouts is enlarged or reduced, and added or subtracted with a design layout of a layer different from the enlarged or reduced layer design layout. The defect classification apparatus characterized in that the reference layout is generated. The defect classification apparatus according to claim 1,
A defect classification apparatus according to claim 1, wherein positive or negative information is attached to each of the layers in the design layout. Occurs in the pattern by matching the image to be inspected, which is an image of the pattern of the sample obtained by the defect inspection apparatus or the defect review apparatus, with the reference layout of the pattern corresponding to the pattern generated based on the design data In a defect classification method for classifying defects to be
A defect classification method, wherein the reference layout is generated by adding or subtracting design layouts of a plurality of layers in the design data. The defect classification method according to claim 5,
The pattern is a pattern manufactured by being exposed by a double patterning method,
A defect classification method, wherein a method for generating the reference layout is changed based on a double patterning exposure method. The defect classification method according to claim 6,
When the exposure method is the first method, the reference layout is generated by adding or subtracting the design layout of the plurality of layers as it is,
When the exposure method is the second method, at least one of the plurality of layer design layouts is enlarged or reduced, and added or subtracted with a design layout of a layer different from the enlarged or reduced layer design layout. A defect classification method characterized by generating the reference layout. The defect classification method according to claim 5,
A defect classification method comprising adding positive or negative information to the design layout.