JP2009170471A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that avoids interference between adjacent cells without degrading the writing/clearing efficiency, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device includes a first insulating film 6 that is filled up from the bottom face of a trench formed from the front face toward the inside of a semiconductor substrate 1 up to a depth position lower than the top face of the substrate, and that has a concave structure in the shape where the side face is orthogonal to the substrate 1 or in the tapered shape at a part of a region that never comes in contact with an inner wall of the trench; a first gate electrode 9 formed on the top face and outer face of a gate oxide film 8 as well as on the front face of the first insulating film 6 that is related to a region interposed between the concave structure and the gate oxide film 8; and a second gate electrode 12 formed on the top face and outer face of a second insulating film 11 with the concave structure filled up. The lowest face of the second gate electrode 12 is formed at a position lower than the lowest face of the first gate electrode 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a transistor structure in which two gate electrodes are stacked with an insulating film interposed therebetween and a manufacturing method thereof.

  A flash memory, which is one of semiconductor memory devices, is a memory that utilizes the fact that a threshold value changes depending on the amount of charge in a floating gate electrode. Data can be rewritten electrically, and the charge accumulated in the floating gate electrode is Since the memory state is not changed even after the power is turned off, it is widely used as a nonvolatile memory mainly in portable devices.

  FIG. 5 is a schematic plan view of a conventional flash memory cell array. As shown in FIG. 5, control gate electrodes 12 (regions surrounded by thick lines) are arranged in stripes, and floating gate electrodes 9 are arranged independently for each memory cell under the control gate electrode 12. ing. A source / drain diffusion region 13 is formed on the active region 7 in a self-aligned manner with respect to the control gate electrode 12. The active region 7 is formed below the source / drain diffusion region 13 and below the floating gate electrode 9 and is arranged in a lattice pattern. A first insulating film 6 for element isolation is formed in a region where the active region 7 is not formed, and the floating gate electrode 9 extends in the extending direction of the control gate electrode 12 by this first insulating film 6 ( It is divided in the direction of the drawing AA ′. The floating gate electrode 9 is also divided in the BB ′ direction in the drawing by the source / drain diffusion region 13, whereby the floating gate electrode 9 is arranged independently for each memory cell. . Then, one memory cell is formed by the structure surrounded by the region 20 in FIG.

  FIG. 6 is a schematic cross-sectional view of a conventional flash memory cell array, and illustrates a part of the schematic cross-sectional view taken along the line AA ′ shown in FIG. 5 and the line BB ′ orthogonal thereto. ing.

  A conventional flash memory cell (array) shown in FIG. 6 has an active region (first impurity diffusion region) separated by an insulating film (first insulating film) 6 filled in a trench formed on a semiconductor substrate 1. ) 7, gate oxide film 8, floating gate electrode (first gate electrode) 9, ONO film (second insulating film) 11, control gate electrode (second gate electrode) 12, source / drain diffusion region 13, sidewall insulation A film 14, an interlayer insulating film 15, a contact plug 16, and a wiring layer (bit line) 17 are provided.

  As shown in FIG. 6, a gate oxide film 8, a first gate electrode 9, a second insulating film 11, and a second gate electrode 12 are stacked in this order from the bottom on the active region 7. A source / drain diffusion region 13 is formed in a self-aligned manner with respect to the second gate electrode 12 in a region on the semiconductor substrate 1 sandwiched between the structures. The drain side of the source / drain diffusion region 13 is electrically connected to the bit line 17 by the contact plug 16. Although not shown, each second gate electrode 12 is electrically connected to a word line. The source side of the source / drain diffusion region 13 is connected to the source side of the source / drain diffusion region 13 of the memory cell adjacent in the extending direction of the word line (12), and extends in the direction parallel to the word line. Is forming. In the following description, it is assumed that the active region 7 is a P-type region and the source / drain diffusion region 13 is a high-concentration N-type region.

  Under such a configuration, for example, 1V is applied to the bit line 17, 5V is applied to the word line, 0V is applied to the source diffusion region (source line), and the amount of current flowing through the source diffusion region (source line) is detected. Do. When information is stored in the flash memory cell, since electrons are held in the first gate electrode 9, the threshold voltage of the transistor (memory cell transistor) is in an initial state (electrons are stored in the first gate electrode 9). As compared with a state where information is not held, that is, a state where information is not stored. That is, since the amount of current flowing through the selected memory cell transistor varies depending on whether information is stored in the flash memory cell or not, the current amount is detected by the source line. It is possible to determine whether information is written in the memory cell.

  Further, for example, 4V is applied to the bit line 17, 9V is applied to the word line, and 0V is applied to the source line, thereby performing the writing process. When the voltage state as described above is formed, a channel region is formed in the active region 7 below the first gate electrode 9, and the memory cell transistor becomes conductive. At this time, a pinch-off point where the channel disappears is generated in the vicinity of the drain region, and electrons are drift-conducted in this portion. Therefore, a high electric field is generated in the region in the vicinity of the drain due to a high potential difference between the channel potential and the drain potential. Electrons are generated. Since a positive voltage is applied to the word line (second gate electrode 12), the channel hot electrons are attracted to the second gate electrode 12 side, and pass through the gate oxide film 8 into the first gate electrode 9. It is captured and information is written thereby.

  For example, the erase process is performed by applying 7 V to the active region 7 and −8 V to the word line. When the voltage state as described above is formed, an FN tunnel current that flows from the first gate electrode 9 to the active region 7 through the gate oxide film 8 is generated, and is thereby accumulated in the first gate electrode 9. Electrons are released and information is erased.

  As described above, when writing information to the flash memory cell, charge (hot electrons) is injected into the first gate electrode 9. At this time, in order to attract hot electrons accelerated by the electric field between the source and the drain into the first gate electrode 9, a positive voltage is applied to the second gate electrode 12 in order to raise the potential of the first gate electrode 9. Apply.

  At this time, the voltage induced in the first gate electrode 9 is induced in the operating voltage applied to the second gate electrode 12 and in the first gate electrode 9 when the voltage is applied to the second gate electrode 12. It is determined depending on the voltage ratio (hereinafter referred to as “coupling ratio”). That is, when the same operating voltage is applied to the second gate electrode 12, the induced voltage induced in the first gate electrode 9 increases as the coupling ratio increases. Therefore, by increasing the coupling ratio, it is possible to reduce the operating voltage to be applied to the second gate electrode 12, which is necessary for injecting charges into the first gate electrode 9, and to perform writing efficiently. be able to.

  The coupling ratio is such that the capacitance between the semiconductor substrate 1 (active region 7, source / drain diffusion region 13) and the first gate electrode 9 is C 1, and between the first gate electrode 9 and the second gate electrode 12. Is the value defined by C2 / (C1 + C2). Increasing the coupling ratio can be realized by decreasing C1 or increasing C2.

  However, C1 depends on the film thickness of the gate oxide film 8. Increasing the film thickness of the gate oxide film 7 in order to reduce C1 is the inflow of charges to the first gate electrode 9 or the first gate electrode 9. This makes it difficult to escape charges from the surface and deteriorates the write / erase characteristics. For this reason, it is practically difficult to reduce C1. Although it is theoretically possible to increase C2 by reducing the thickness of the second insulating film 11 between the first gate electrode 9 and the second gate electrode 12, the second insulating film 11 Therefore, there is a problem that the electric charge accumulated in the first gate electrode 9 easily escapes to the second gate electrode 12 and the data retention characteristics deteriorate.

  Accordingly, the area where the first gate electrode 9 and the second gate electrode 12 are opposed to each other from the area where the first gate electrode 9 and the semiconductor substrate 1 (the active region 7 and the source / drain diffusion region 13) are opposed to each other. In order to increase the coupling ratio, a method of increasing the coupling ratio is employed (see, for example, Patent Document 1 below). Hereinafter, a manufacturing process when a flash memory cell is manufactured by such a method will be described with reference to the drawings.

  7 to 10 schematically show schematic cross-sectional structure diagrams in each process when manufacturing a flash memory cell (array) using the above-described conventional method, and FIG. To (d), FIG. 8 (a) to (d), FIG. 9 (a) to (c), and FIG. 10 (a) to (c). I know). FIG. 11 is a flowchart showing the manufacturing process of the conventional method, and each step in the following sentence represents each step of the flowchart shown in FIG. Each cross-sectional structure diagram is illustrated by a cross-sectional view taken along line A-A 'and line B-B' in FIG.

  Each cross-sectional structure diagram is schematically illustrated, and the dimensional ratio on the drawing does not necessarily match the actual dimensional ratio.

  First, as shown in FIG. 7A, a silicon oxide film 2 and a silicon nitride film 3 are deposited on the entire surface of the semiconductor substrate 1 (step # 1).

  Next, as shown in FIG. 7B, a photoresist film 4 patterned by a photolithography method is formed in a predetermined region on the silicon nitride film 3 (step # 2). In this step # 2, the photoresist film 4 is left in a region other than the region where the trench 5 is formed by etching the semiconductor substrate 1 in the next step # 3. The formation region of the trench 5 can be, for example, a plurality of regions arranged in a matrix in a first direction parallel to the substrate surface of the semiconductor substrate 1 and a second direction orthogonal to the same direction.

  Next, as shown in FIG. 7C, the silicon nitride film 3 and the silicon oxide film 2 are etched by plasma etching using the photoresist film 4 formed in step # 2 as a mask, and then the photoresist film Using the silicon nitride film 3 remaining after peeling 4 as a mask, the semiconductor substrate 1 is etched to form a trench 5 (step # 3).

  Next, a silicon oxide film (hereinafter referred to as “first insulating film 6”) is deposited by a high density plasma CVD (High Density Plasma Chemical Vapor Deposition) method to completely fill the trench 5 (step # 4). ). Thereafter, a polishing process is further performed using a CMP (Chemical Mechanical Polishing) method until the surface of the silicon nitride film 3 around the trench 5 is exposed (see FIG. 7D). Thereafter, as shown in FIG. 8A, the silicon nitride film 3 and the silicon oxide film 2 are sequentially removed using a chemical solution (step # 5). As a result, the substrate surface (active region) of the semiconductor substrate 1 is exposed, and a difference occurs in the height position between the substrate surface of the semiconductor substrate 1 and the film formation surface of the first insulating film 6.

  The processes according to steps # 1 to # 5 described above are the same as the manufacturing process performed using a known trench isolation method called a so-called STI (Shallow Trenchi Isolation) method.

  Next, as shown in FIG. 8B, for example, B ions are implanted into the entire surface and then activated by heat treatment to form the first impurity diffusion region 7 on the semiconductor substrate 1 in the region outside the trench. (Step # 6).

  Next, as shown in FIG. 8C, a wet etching process (isotropic etching process) is performed on the first insulating film 6 using a chemical solution, so that a part of the exposed surface of the first insulating film 6 is exposed. Is retracted to a position below the uppermost surface of the first impurity diffusion region 7 (step # 7). The step # 7 has an effect of increasing the surface area of the first gate electrode 9 formed in the subsequent process and increasing the facing area between the gate electrode 9 and the second gate electrode 12.

  Next, as shown in FIG. 8D, the exposed substrate surface (first impurity diffusion region 7) of the semiconductor substrate 1 is subjected to thermal oxidation to form a gate oxide film 8 (step #). 8).

  Next, as shown in FIG. 9A, after a conductive first gate electrode film 9 (for example, a polysilicon film) is formed on the entire surface, a CMP method or the like is performed until the upper surface of the first insulating film 6 is exposed. Is used to flatten the surface (step # 9).

  Next, as shown in FIG. 9B, the first insulating film 6 formed in the region sandwiched between the first gate electrode films 9 is removed by wet etching, and the first insulating film 6 is removed. The exposed surface is retracted to form the opening 31 (step # 11).

  Next, as shown in FIG. 9C, after the second insulating film 11 (ONO film) is formed with a film thickness that does not completely fill the opening 31 (step # 12), immediately above it A conductive second gate electrode film 12 (for example, a polysilicon film) is formed (step # 13). As described above, the first gate electrode film 9 and the second gate electrode film 12 are in a direction perpendicular to the substrate surface by performing the wet etching process on the first insulating film 6 in advance in Step # 7. Can also be increased, thereby increasing the C2 and realizing a large coupling ratio.

  Next, the laminated film composed of the second gate electrode film 12, the second insulating film 11, the first gate electrode film 9 and the gate oxide film 8 is patterned to form the first gate electrode (floating gate electrode) 9 and the semiconductor substrate 1. A second gate electrode (control gate electrode) 12 extending in a first direction parallel to the substrate surface is simultaneously formed (step # 14). By this step # 14, a plurality of second gate electrodes 12 extending in the first direction are formed, and the outer active region (first impurity diffusion region 7) is exposed.

  After that, it conforms to a conventional method for manufacturing a nonvolatile semiconductor memory device. That is, after forming source / drain diffusion regions 13 by performing, for example, As ion implantation using these gate electrodes as a mask (FIG. 10A), an interlayer insulating film 15 is deposited on the entire surface (FIG. 10B). ). After a contact hole is formed in a predetermined region on the source / drain diffusion region, a contact plug 16 is formed by filling the contact hole with a metal film such as tungsten (W), and the contact hole 16 is electrically connected to the source / drain region. A wiring layer (bit line) 17 for general connection is formed (FIG. 10C).

  As shown in FIG. 10B, after the As ion implantation, after the sidewall insulating film 14 is formed on the outer surface of the multilayer film, the As ion implantation is performed again using the multilayer film and the sidewall insulating film 14 as a mask. It is good as a thing.

Japanese Patent No. 3362970 JP 2002-57228 A

  According to the conventional method, since the facing area between the first gate electrode 9 and the second gate electrode 12 increases, a large coupling ratio can be realized.

  By the way, when the memory cell size is reduced as the capacity is increased, the distance between adjacent cells is reduced, thereby increasing the capacitance between adjacent floating gate (first gate) electrodes, thereby increasing the distance between adjacent cells. Interference can no longer be ignored. When the degree of interference increases, the potentials of the adjacent first gate electrodes 9 are averaged, which causes problems such as erroneous data reading.

  In order to avoid such a problem, a method of shielding between adjacent first gate electrodes with a conductive layer has been conventionally disclosed (for example, see Patent Document 2). In the case of using the above-described method described with reference to FIGS. 7 to 10, it is only necessary to realize a shielding capability by sufficiently burying the second gate electrode between the adjacent first gate electrodes. In step # 11, the exposed surface of the first insulating film 6 may be sufficiently retracted. For this purpose, it is necessary to recede the exposed surface to a position deeper than the lowermost surface of the first gate electrode 9 in consideration of variations during wet etching.

  However, since the wet etching process is performed on the first insulating film 6 in the above step # 7, as shown in FIG. 9A, the first gate electrode film 9 is formed before the execution of the step # 11. The lower region shows a curved shape. Therefore, in step # 11, when the process of retracting the exposed surface of the first insulating film 6 to a position deeper than the lowermost surface of the first gate electrode film 9, an opening formed after the process is formed as shown in FIG. The portion 32 has a curved shape that expands as it advances in the depth direction.

  FIG. 13 is a schematic cross-sectional structure diagram when steps # 12 and # 13 are performed after the opening 32 having the shape as shown in FIG. 12 is formed. Since the opening 32 has an expansion at the bottom, as shown in FIG. 13, the second gate electrode film 12 formed thereafter is formed in the lower region of the first gate electrode film 9 (in FIG. Area A).

  When the second gate electrode film 12 is formed so as to wrap around the first gate electrode film 9 in this way, the second gate electrode film 12 is subjected to the second gate electrode film 12 in the patterning process in step # 14. The first gate electrode film 9 formed in the upper region of the gate electrode film 12 serves as a mask, and a part of the second gate electrode film 12 formed under the mask remains without being removed by etching. End up. Thereby, the adjacent second gate electrodes 12 are electrically connected to each other, which may cause a problem.

  In order to avoid such a state, a wet etching process is performed on the first insulating film 6 according to step # 11 so as not to go below the first gate electrode film 9 when the second gate electrode film 12 is formed. For example, as shown in FIG. 14, the first gate electrode film 9 is formed above the trench, and the second gate electrode film 12 is embedded between the adjacent first gate electrode films 9. What is necessary is just to form. However, in the case of such a structure, since the surface area of the first gate electrode film is reduced, the opposing area of both gate electrode films is reduced, thereby reducing the coupling ratio.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that avoids interference between adjacent cells without deteriorating write / erase efficiency and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a transistor structure in which two gate electrodes are stacked via an insulating film, and is formed from the surface of a semiconductor substrate into the semiconductor substrate. A trench recessed inward, a first impurity diffusion region of a first conductivity type formed in an active region outside the trench on the surface of the semiconductor substrate, and a depth lower than the top surface of the semiconductor substrate from the bottom surface of the trench. A first insulating film having a concave structure with a side surface orthogonal to the semiconductor substrate or a tapered shape in a part of a region not filled with the trench inner wall and being in contact with the trench inner wall; A gate oxide film formed on an upper surface of the diffusion region and an outer surface not covered with the first insulating film; an upper surface and an outer surface of the gate oxide film; and the recess structure and the gate acid. A first gate electrode formed on a surface of the first insulating film in a region sandwiched between the films, the concave structure on the upper surface and the outer surface of the first gate electrode, and the inner surface of the concave structure; A second insulating film formed with a film thickness that does not completely fill the second insulating film, and a second gate electrode formed by filling the concave structure on the upper surface and the outer surface of the second insulating film, A source / drain diffusion region of a second conductivity type different from the first conductivity type formed in a region sandwiched between the plurality of first gate electrodes of the active region, and the second gate electrode The lowermost surface of the first gate electrode is formed at a position lower than the lowermost surface of the first gate electrode.

  According to the above characteristic configuration of the semiconductor device according to the present invention, the second gate electrode is formed so as to fill the recess structure formed in the first insulating film. A first gate electrode is formed on the upper surface and the outer surface of the gate oxide film, and on the surface of the first insulating film related to the region sandwiched between the recessed structure and the gate oxide film. Thus, the first gate electrode and the second gate electrode are opposed to each other not only in the direction parallel to the substrate surface of the semiconductor substrate but also in the direction perpendicular to the substrate surface. As a result, the opposing area between both gate electrodes increases, and a large coupling ratio can be realized. As a result, high write / erase efficiency can be realized.

  The second gate electrode is formed so that the lowermost surface is positioned below the lowermost surface of the first gate electrode. Therefore, the second gate electrode is formed between the adjacent first gate electrodes. As a result, even when the interval between the adjacent first gate electrodes becomes narrow, the second gate electrode is shielded. Therefore, an increase in capacitance between the first gate electrodes can be suppressed. As a result, when the device of the present invention is used as a nonvolatile semiconductor memory device, it is possible to avoid errors such as erroneous reading caused by the potential being induced by the capacitance between the adjacent first gate electrodes. It becomes possible.

  According to the above configuration, the concave structure whose side surface is orthogonal or tapered with respect to the semiconductor substrate is formed in the first insulating film, and the first region relating to the region sandwiched between the concave structure and the gate oxide film is formed. A first gate electrode is formed on the surface of one insulating film and on the upper and outer surfaces of the gate oxide film. The second insulating film is formed on the inner surface of the concave structure with a film thickness within a range that does not completely fill the concave structure, and the second gate electrode is on the upper surface and the outer surface of the second insulating film. Is formed. Therefore, since the first gate electrode is not formed in the region above the second gate electrode, a part of the second gate electrode to be removed remains as a mask during processing, and this is left. Therefore, a situation in which the adjacent second gate electrodes are electrically connected to each other is not caused. Therefore, when the device of the present invention is used as a non-volatile semiconductor memory device, it is possible to apply a voltage to each second gate electrode, thereby realizing each operation of reading / writing / erasing without any trouble. Become.

  A method of manufacturing a semiconductor device according to the present invention for achieving the above object is a method of manufacturing a semiconductor device having the above-described characteristic configuration, and after the trench is formed on a semiconductor substrate, the trench is filled. And a first step of forming the first insulating film so that the upper surface position is higher than the uppermost surface of the active region outside the trench, and after the first step, the impurity ions of the first conductivity type are implanted. A second step of forming the first impurity diffusion region in the active region; and after the second step, an isotropic etching process is performed on the first insulating film, thereby A third step of retracting a part of the exposed surface of the film to a position below the uppermost surface of the active region; and after completion of the third step, the exposed surface of the semiconductor substrate is subjected to a thermal oxidation process to form the gate oxide film A fourth step of forming After the completion of the fourth step, after forming a conductive first gate electrode film on the entire surface, a fifth step of performing a planarization process until the upper surface of the first insulating film is exposed, and after the completion of the fifth step, Using the first gate electrode film as a mask, anisotropic etching is performed on the first insulating film until the exposed surface of the first insulating film is positioned below the lowermost surface of the first gate electrode film. A sixth step of forming an opening including the concave structure, and after the sixth step, the second insulating film is formed on the entire surface with a thickness within a range that does not completely fill the concave structure. A seventh step, an eighth step of forming a conductive second gate electrode film on the entire surface after completion of the seventh step, and a second gate electrode film and the second insulating film after completion of the eighth step. The first gate electrode film and the gate oxide film are stacked in this order. The film is patterned to form the second gate electrode extending in the first direction parallel to the first gate electrode and the semiconductor substrate, and the semiconductor substrate surface is exposed outside the second gate electrode. And a ninth step of implanting the second conductivity type impurity ions after the ninth step and forming the source / drain diffusion regions on the exposed surface of the semiconductor substrate. Is the first feature.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having the above-described characteristic configuration, wherein the first step of forming the trench on the semiconductor substrate of the first conductivity type, and the first After the step, the second step of filling the inside of the trench and forming the first insulating film so that the upper surface position is higher than the uppermost surface of the active region outside the trench, and after the end of the second step, Performing a isotropic etching process on the first insulating film to cause a part of the exposed surface of the first insulating film to recede to a position below the uppermost surface of the active region; After the third step, a fourth step of forming the gate oxide film by subjecting the exposed surface of the semiconductor substrate to thermal oxidation, and after the fourth step, a conductive first gate electrode film is formed on the entire surface. Then, the upper surface of the first insulating film is exposed. A fifth step of performing planarization until the exposed surface of the first insulating film is located below the lowermost surface of the first gate electrode with the first gate electrode film as a mask after completion of the fifth step. A sixth step of forming an opening including the concave structure by performing an anisotropic etching process on the first insulating film, and after the sixth step, the interior of the concave structure is completely completed. A seventh step of forming the second insulating film on the entire surface with a film thickness within a range not to be filled; an eighth step of forming a conductive second gate electrode film on the entire surface after the completion of the seventh step; After completion of the eight steps, a patterning process is performed on the stacked film in which the second gate electrode film, the second insulating film, the first gate electrode film, and the gate oxide film are stacked in this order, and the first gate electrode and The first extending in the first parallel direction of the semiconductor substrate. A gate electrode is formed and a semiconductor substrate surface is exposed outside the second gate electrode, and after the ninth step, the second conductivity type impurity ions are implanted and exposed. And a tenth step of forming the source / drain diffusion regions on the surface of the semiconductor substrate.

  According to the first or second feature of the method of manufacturing a semiconductor device according to the present invention, an isotropic etching process is performed on the first insulating film in the third step so that the first insulating film is formed. The surface area of the first gate electrode film is increased by forming a conductive first gate electrode film in the fifth step after retreating a part of the exposed surface to a position below the uppermost surface of the active region. Can be made. As a result, the area facing the second gate electrode film deposited in the subsequent eighth step is increased, so that a large coupling ratio can be realized, and as a result, high write / erase efficiency can be realized. It becomes.

  According to the first or second feature, in the sixth step, the first insulating film until the exposed surface of the first insulating film is located below the lowermost surface of the first gate electrode film. An opening including the concave structure is formed by performing an anisotropic etching process. For this reason, the etching process of the first insulating film does not proceed in the direction parallel to the semiconductor substrate surface, whereby the first insulating film located in the lower region of the first gate electrode film is not etched. As a result, the opening formed after the sixth step is not formed in the lower region of the first gate electrode film. Therefore, a situation in which a part of the second gate electrode film deposited in the subsequent eighth step is formed in the lower region of the first gate electrode film does not occur. As a result, even when the patterning process according to the ninth step is performed, a situation in which a part of the second gate electrode film to be removed remains using the first gate electrode film formed above as a mask is avoided. Therefore, the situation where the adjacent second gate electrodes are electrically connected to each other can be avoided. Therefore, when the semiconductor device manufactured by the method of the present invention is used as a non-volatile semiconductor memory device, it is possible to apply a voltage to each second gate electrode, and thereby read / write / erase without trouble. Operation can be realized.

  In the semiconductor device manufacturing method according to the present invention, in addition to the first or second feature, the sixth step is a step of forming the concave structure in a tapered shape in the first insulating film. This is the third feature.

  According to the third feature of the method of manufacturing a semiconductor device according to the present invention, it is possible to reliably avoid the situation where the opening formed in the sixth step is located in the lower region of the first gate electrode film. it can. For this reason, a situation in which a part of the second gate electrode film deposited in the subsequent eighth step is not formed in the lower region of the first gate electrode film is caused, and the patterning process according to the ninth step is executed. However, it is possible to avoid a situation in which a part of the second gate electrode film to be removed remains using the first gate electrode film formed above as a mask, and the adjacent second gate electrodes are electrically connected to each other. Connection situation is avoided.

  According to the configuration of the present invention, it is possible to provide a semiconductor device that avoids interference between adjacent cells while maintaining high write / erase efficiency, and a method for manufacturing the same.

  Hereinafter, embodiments of a semiconductor device according to the present invention (hereinafter referred to as “the present invention device” as appropriate) and a manufacturing method thereof (hereinafter referred to as “the present invention method” as appropriate) will be described with reference to the drawings.

  The method of the present invention differs from the manufacturing method according to the prior art described above with reference to the schematic cross-sectional structure diagrams according to FIGS. 7 to 10 and the flowchart according to FIG. In order to avoid duplication of description, the same components are denoted by the same reference numerals, the same steps are denoted by the same step numbers, and detailed description thereof is omitted.

  The schematic plan view of the device of the present invention is the same as the conventional schematic plan view shown in FIG. Each of the following schematic cross-sectional structure diagrams is shown by a cross-sectional structure diagram taken along the line A-A ′ and the line B-B ′ in FIG. 5 similarly to the schematic cross-sectional structure diagram of the conventional configuration.

  FIG. 1 is a schematic sectional view of the apparatus of the present invention. The device according to the present invention is formed so that the lowermost surface of the second gate electrode film 12 is located below the lowermost surface of the first gate electrode film 9 as compared with the conventional semiconductor device shown in FIG. (See region C in the figure). Compared with the semiconductor device shown in FIG. 13, the second gate electrode film 12 is not formed in the lower region of the first gate electrode film 9.

  By adopting such a configuration, a structure in which the second gate electrode 12 is embedded between the adjacent first gate electrodes 9 while sufficiently ensuring a facing area between the first gate electrode film 9 and the second gate electrode film 12 is provided. As a result, the capacitance between the adjacent first gate electrodes can be reduced, and interference between adjacent cells can be avoided.

  Further, unlike the structure of FIG. 13, the second gate electrode 12 does not wrap around the region below the first gate electrode 9. In other words, the first gate electrode 9 is formed above the second gate electrode 12. Therefore, there is no problem that a part of the second gate electrode 12 remains using the first gate electrode 9 as a mask during the patterning process for the second gate electrode 12. For this reason, the situation where the adjacent 2nd gate electrodes 12 formed after the patterning process are electrically connected can be avoided.

  Hereinafter, a method for manufacturing the device of the present invention having the structure shown in FIG. 1 will be described with reference to the drawings. 2 to 3 schematically show schematic cross-sectional structure diagrams in each process when the apparatus of the present invention is manufactured using the method of the present invention, and FIGS. 2 (a) to (c) are shown for each process. 3 (a) to 3 (c) (they are divided into two drawings for the sake of space). FIG. 4 is a flowchart showing the manufacturing process of the method of the present invention, and each step in the following sentence represents each step of the flowchart shown in FIG. As described above, in each step of FIG. 4, the same step number is assigned to a process common to each step of the conventional process in FIG. 10.

  First, the steps # 1 to # 9 in FIG. 11 described above are executed to form a structure as shown in FIG. The structure in FIG. 2A is the same as the structure in FIG. Moreover, the cross-sectional structure diagram after the completion of each process related to steps # 1 to # 8 is the same as each structural diagram shown in FIGS.

  More specifically, in step # 1, a silicon oxide film 2 having a thickness of about 15 nm and a silicon nitride film 3 having a thickness of about 150 nm are deposited, and in step # 3, a trench 5 having a depth of about 200 nm is formed. . In addition, after step # 1, the antireflection made of an organic BARC (Bottom Anti-Reflective Coating) material or a polysilicon material is formed on the silicon nitride film 3 in order to suppress the reflection of light irradiated in the photolithography process. A film may be deposited. Even in this case, since the deposited antireflection film can be removed after the photoresist film 4 is peeled off and before the etching process for the semiconductor substrate 1 is started, the subsequent processes are not affected. .

  In step # 4, the first insulating film 6 is formed to a thickness of about 500 nm. Thereafter, the element isolation region and the active region (first impurity diffusion region 7) formed through Step # 5 have, for example, an element isolation width of about 150 nm, an active region width of about 200 nm, and an element isolation layer thickness (substrate The film thickness of the first insulating film 6 in the region having a height position higher than the surface is about 350 nm (see FIG. 8B). In addition, after the formation process of the trench 5 according to step # 3, before filling the first insulating film 6, there may be a process of growing an oxide film of about 10 to 50 nm using a diffusion furnace. By performing such a process, the shape of the corner portion generated in the portion having a different height position by the etching process according to Step # 3 is rounded, and the electric field can be prevented from concentrating on the corner portion.

In step # 6, for example, B ions are implanted at a dose of about 5 × 10 ¹² / cm ² with an implantation energy of 30 keV and an implantation energy of 100 keV, and then activated by applying a heat treatment to activate the first impurity diffusion region 7. (Well region) is formed. Further, in step # 7, the surface of the first insulating film 6 is retreated by about 50 nm by performing a wet etching process on the first insulating film 6 using a diluted HF solution.

  In step # 8, a gate oxide film 8 having a thickness of about 10 nm is formed by thermal oxidation. The gate oxide film 8 takes electrons from the impurity diffusion region into the floating gate electrode (first gate electrode 9) formed in a later process, or electrons from the first gate electrode 9 to the impurity diffusion region. This will form a path for electrons when they are pulled out.

  In step # 9, a conductive first gate electrode film 9 made of, for example, a polysilicon film doped with P is deposited to a thickness of about 150 nm, and then planarized using a CMP method. Through the above steps, a structure as shown in FIG. 2A is formed.

After step # 9, instead of the above-described conventional step # 11, as shown in FIG. 2B, the first insulating film 6 buried between the first gate electrode films 9 is changed to the first step. Using the gate electrode film 9 as a mask, anisotropic etching is performed by RIE (Reactive Ion Etching) or the like (step # 10). At this time, the etching process is performed until the exposed surface of the first insulating film 6 is positioned below the lowermost surface of the first gate electrode film 9. Specifically, the first insulating film 6 has a thickness of about 150 nm under etching conditions in which the RF power is 600 W, the pressure is 75 mTorr, and the flow rate ratio is C ₄ F ₈ / Ar / CF ₄ = 5/150/5 sccm. Etch away.

  By this step # 10, the opening 33 is formed between the first gate electrode films 9, and the concave structure 34 is formed in a part of the first insulating film 6.

  Step # 11 according to the prior art is a process of performing a wet etching process (isotropic etching process), and therefore, in a direction parallel to the substrate surface as well as a direction perpendicular to the substrate surface of the semiconductor substrate 1. In addition, the etching of the first insulating film 6 proceeds. Therefore, the exposed surface of the first insulating film 6 is the first gate electrode film so as to bury the second gate electrode film 12 formed in a later step in order to enhance the shielding effect between the adjacent first gate electrode films 9. When the etching process is advanced to a position below the lowermost surface of 9, the shape of the opening 32 expands in the direction parallel to the substrate surface near the bottom surface, as shown in FIG. As a result, when the second gate electrode film 12 is subsequently deposited on the entire surface, a part of the second gate electrode film 12 is formed in a region below the first gate electrode film 9 as shown in FIG. . This causes a problem that the first gate electrode film 9 on which a part of the second gate electrode film 12 is formed remains as a mask during the subsequent patterning process.

  However, in step # 10 according to the present invention, unlike the step # 11 according to the prior art, since the anisotropic etching process is performed, the first insulating film 6 in the direction parallel to the substrate surface of the semiconductor substrate 1 is used. Thus, the first insulating film 6 located in the lower region of the first gate electrode film 9 is not etched. As a result, even if the second gate electrode film 12 is deposited on the entire surface in a later step, it is possible to avoid a situation in which a part of the second gate electrode film 12 is formed in a region below the first gate electrode film 9. it can.

  In order to prevent etching from proceeding with respect to the first insulating film 6 located in the lower region of the first gate electrode film 9, an anisotropic etching process is preferably performed under the condition that the concave structure 34 has a tapered shape. Good to run. For example, the concave structure 34 can be tapered by performing anisotropic etching under the conditions related to Step # 10 described above.

After the completion of Step # 10, as shown in FIG. 2C, the second insulating film 11 (ONO film) is formed with a film thickness that does not completely fill the opening 33 (Step S10). # 12) A conductive second gate electrode film 12 is formed immediately above (step # 13). More specifically, in step # 12, the surface is thermally oxidized to form a SiO ₂ film with a film thickness of about 6 nm, a SiN film is formed with a film thickness of about 5 nm by LPCVD or the like, and then HPD- A SiO ₂ film is formed to a thickness of about 7 nm. In step # 13, a conductive second gate electrode film 12 made of, for example, a polysilicon film doped with P is deposited to a thickness of about 200 nm. By this step # 13, the second gate electrode film 12 is embedded between the adjacent first gate electrode films 9, and the second gate electrode film 12 is formed below the lowermost surface of the first gate electrode film 9. Will be. As described above, since the opening 33 (recessed structure 34) is not formed below the first gate electrode film 9, the second gate electrode film 12 wraps around the region below the first gate electrode film 9. Are not formed.

  After step # 13, as in the prior art, the laminated film composed of the second gate electrode film 12, the second insulating film 11, the first gate electrode film 9, and the silicon oxide film 8 is patterned to form the first gate electrode ( A floating gate electrode) 9 and a second gate electrode (control gate electrode) 12 extending in a first direction parallel to the substrate surface of the semiconductor substrate 1 are simultaneously formed (step # 14). Since the first gate electrode film 9 is not formed above the second gate electrode film 12, a part of the second gate electrode film remains with the first gate electrode film 9 as a mask, and the A situation in which the two gate electrodes are electrically connected can be avoided.

Thereafter, in accordance with a conventional method for manufacturing a nonvolatile semiconductor memory device, As ions are implanted under the conditions of an implantation energy of ¹⁵ keV and a dose of 1 × 10 ¹⁵ / cm ² using these gate electrodes as a mask, and then heat treatment ( For example, after activating at 950 ° C. for 10 seconds to form the source / drain diffusion regions 13 (FIG. 3A), an interlayer insulating film 15 is deposited on the entire surface (FIG. 3B). After a contact hole is formed in a predetermined region on the source / drain diffusion region, a contact plug 16 is formed by filling the contact hole with a metal film such as tungsten (W), and the contact hole 16 is electrically connected to the source / drain region. A wiring layer (bit line) 17 for general connection is formed (FIG. 3C). If necessary, an interlayer insulating film forming step and a wiring layer forming step may be performed a plurality of times to form a multilayer wiring structure.

  At this time, as shown in FIG. 3B, after As ion implantation, after forming the sidewall insulating film 14 on the outer surface of the multilayer film, As ion implantation is performed again using the multilayer film and the sidewall insulating film 14 as a mask. It can be done.

  In the above-described embodiment, the first impurity diffusion region 7 is formed by performing B ion implantation in Step # 6. However, by using the P-type semiconductor substrate 1 in advance, the ion implantation process according to Step # 6 is performed. May be omitted. In the above-described embodiment, the case where the device of the present invention has an N-channel MOS transistor structure has been described as an example. However, the present invention can be similarly realized by having a P-channel MOS transistor structure by reversing the polarity. .

Part of schematic cross-sectional structure diagram of semiconductor device according to the present invention Schematic cross-sectional structure diagram (1) in each step of the method for manufacturing a semiconductor device according to the present invention Schematic cross-sectional structure diagram (2) in each step of the semiconductor device manufacturing method according to the present invention The flowchart which shows the manufacturing process of the manufacturing method of the semiconductor device based on this invention in order. Schematic plan view of a conventional flash memory cell array according to the present invention Part of schematic cross-sectional structure diagram of conventional flash memory cell array Schematic cross-sectional structure diagram in each step of a conventional flash memory cell array manufacturing method (1) Schematic cross-sectional structure diagram in each step of a conventional flash memory cell array manufacturing method (2) Schematic cross-sectional structure diagram in each step of a conventional flash memory cell array manufacturing method (3) Schematic cross-sectional structure diagram in each step of a conventional flash memory cell array manufacturing method (4) A flowchart sequentially showing the manufacturing steps of a conventional flash memory cell array manufacturing method Part of another schematic cross-sectional structure diagram of a conventional flash memory cell array Part of yet another schematic cross-sectional structure diagram of a conventional flash memory cell array Part of yet another schematic cross-sectional structure diagram of a conventional flash memory cell array

Explanation of symbols

1: Semiconductor substrate 2: Silicon oxide film 3: Silicon nitride film 4: Photoresist film 5: Trench 6: First insulating film 7: First impurity diffusion region (active region)
8: Gate oxide film 9: First gate electrode (floating gate electrode)
11: Second insulating film (ONO film)
12: Second gate electrode (control gate electrode)
13: Source / drain diffusion region 14: Side wall insulating film 15: Interlayer insulating film 16: Contact plug 17: Bit line (wiring layer)
20: Memory cell region 31, 32, 33: Opening 34: Concave structure

Claims (4)

A semiconductor device having a transistor structure in which two gate electrodes are stacked via an insulating film,
A trench recessed from the surface of the semiconductor substrate into the semiconductor substrate;
A first impurity diffusion region of a first conductivity type formed in an active region outside the trench on the semiconductor substrate surface;
Filled from the bottom surface of the trench to a depth position lower than the uppermost surface of the semiconductor substrate, and a recessed portion having a shape whose side surface is orthogonal to the semiconductor substrate or a tapered shape in a part of the region not in contact with the inner wall of the trench A first insulating film comprising:
A gate oxide film formed on an upper surface of the first impurity diffusion region and an outer surface not covered with the first insulating film;
A first gate electrode formed on an upper surface and an outer surface of the gate oxide film, and on the surface of the first insulating film according to a region sandwiched between the recessed structure and the gate oxide film;
A second insulating film formed on the upper surface and the outer surface of the first gate electrode and on the inner surface of the concave structure with a film thickness within a range that does not completely fill the concave structure;
A second gate electrode formed on the upper surface and the outer surface of the second insulating film by filling the recess structure;
A source / drain diffusion region of a second conductivity type different from the first conductivity type formed in the active region sandwiched between a plurality of the first gate electrodes,
2. The semiconductor device according to claim 1, wherein the lowermost surface of the second gate electrode is formed at a position below the lowermost surface of the first gate electrode. A method of manufacturing a semiconductor device according to claim 1,
A first step of forming the first insulating film so as to fill the inside of the trench and form a top surface higher than the uppermost surface of the active region outside the trench after forming the trench on the semiconductor substrate;
A second step of forming the first impurity diffusion region in the active region by implanting the first conductivity type impurity ions after the first step;
After the second step is completed, an isotropic etching process is performed on the first insulating film, so that a part of the exposed surface of the first insulating film recedes to a position below the uppermost surface of the active region. A third step of
A fourth step of forming the gate oxide film by subjecting the exposed surface of the semiconductor substrate to thermal oxidation after the third step;
A fifth step of forming a conductive first gate electrode film on the entire surface after completion of the fourth step, and then performing a planarization process until an upper surface of the first insulating film is exposed;
After the fifth step, with respect to the first insulating film until the exposed surface of the first insulating film is located below the lowermost surface of the first gate electrode film, using the first gate electrode film as a mask. A sixth step of forming an opening including the recess structure by performing an anisotropic etching process;
After the sixth step, a seventh step of forming the second insulating film on the entire surface with a film thickness within a range that does not completely fill the recess structure;
An eighth step of forming a conductive second gate electrode film on the entire surface after completion of the seventh step;
After completion of the eighth step, the second gate electrode film, the second insulating film, the first gate electrode film, and the gate oxide film are stacked in this order, and a patterning process is performed to form the first gate. A ninth step of forming the second gate electrode extending in a first direction parallel to the electrode and the substrate surface of the semiconductor substrate, and exposing the semiconductor substrate surface to the outside of the second gate electrode;
And a tenth step of implanting the second conductivity type impurity ions after the ninth step and forming the source / drain diffusion regions on the exposed surface of the semiconductor substrate. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 1,
A first step of forming the trench on the semiconductor substrate of the first conductivity type;
A second step of forming the first insulating film so as to fill the inside of the trench and to have an upper surface position higher than the uppermost surface of the active region outside the trench after the first step;
After the second step is completed, an isotropic etching process is performed on the first insulating film, so that a part of the exposed surface of the first insulating film recedes to a position below the uppermost surface of the active region. A third step of
A fourth step of forming the gate oxide film by subjecting the exposed surface of the semiconductor substrate to thermal oxidation after the third step;
A fifth step of forming a conductive first gate electrode film on the entire surface after completion of the fourth step, and then performing a planarization process until an upper surface of the first insulating film is exposed;
After the fifth step, using the first gate electrode film as a mask, the first insulating film differs from the first insulating film until the exposed surface of the first insulating film is located below the lowermost surface of the first gate electrode. A sixth step of forming an opening including the recess structure by performing an isotropic etching process;
After the sixth step, a seventh step of forming the second insulating film on the entire surface with a film thickness within a range that does not completely fill the recess structure;
An eighth step of forming a conductive second gate electrode film on the entire surface after completion of the seventh step;
After completion of the eighth step, the second gate electrode film, the second insulating film, the first gate electrode film, and the gate oxide film are stacked in this order, and a patterning process is performed to form the first gate. A ninth step of forming the second gate electrode extending in a first direction parallel to the electrode and the substrate surface of the semiconductor substrate, and exposing the semiconductor substrate surface to the outside of the second gate electrode;
And a tenth step of implanting the second conductivity type impurity ions after the ninth step and forming the source / drain diffusion regions on the exposed surface of the semiconductor substrate. Device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the sixth step is a step of forming the recess structure in a tapered shape in the first insulating film. 5.

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