JP2009165931A - Manufacturing method of capacitive ultrasonic transducer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a capacitive ultrasonic transducer by which mechanical characteristics of a membrane and yield are enhanced, and increase in parasitic capacity is suppressed. <P>SOLUTION: The manufacturing method of the capacitive ultrasonic transducer comprises processes of: preparing an SOI substrate having an active layer on a support substrate via an insulation layer; forming a through-hole on the active layer or support substrate; forming a cavity by introducing fluid for etching the insulation layer from the through-hole formed on the active layer or support substrate and etching the insulation layer; forming an insulation film inside the cavity formed by etching the insulation layer; and sealing the through-hole after forming the insulation film inside the cavity. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a capacitive ultrasonic transducer using micromachining.

An ultrasonic transducer (also referred to as an ultrasonic transducer) converts an electric signal into an ultrasonic wave or converts an ultrasonic signal into an electric signal. It is used as a probe for medical imaging and nondestructive inspection.
As one form of the ultrasonic transducer, there is a capacitive (also referred to as capacitive) ultrasonic transducer (CMUT) using micromachining (capacitive mirromachined ultrasonic transducer).
In the following description, this capacitive ultrasonic transducer is referred to as CMUT.
Such a CMUT generally includes a substrate having a lower electrode, a membrane supported by a support portion formed on the substrate, and an upper electrode.
One cavity includes a lower electrode, a membrane (also referred to as a vibrating membrane), and an upper electrode. The capacitive ultrasonic transducer emits sound waves by vibrating the membrane by a voltage applied between the lower electrode and the upper electrode.
Further, the membrane is vibrated by the received sound wave, and the sound wave is detected by the change in the capacity.

Conventionally, the CMUT has been manufactured using surface micromachining (see, for example, Patent Document 1).
Specifically, a silicon nitride film is formed as a membrane to form an etching hole.
The polysilicon layer is sacrificial-etched from this etching hole to form a cavity.
Finally, a vacuum cavity is formed by filling the etching hole with a silicon nitride film.

As another manufacturing method, there is a method using bulk micromachining in which a cavity structure is formed on a silicon substrate and an SOI (Silicon-on-Insulator) substrate is bonded (see, for example, Patent Document 2).
According to this method, it is possible to improve the mechanical characteristics of the membrane by using a silicon single crystal as the membrane.
As another manufacturing method, there is a method in which a buried oxide film layer of an SOI substrate is subjected to sacrificial layer etching to form a membrane and a cavity (see, for example, Patent Document 3).
This method is known as a method for manufacturing a capacitive pressure sensor, but according to this method, since a bonding process is not used for forming a membrane, it is possible to prevent a decrease in yield due to gas or particles. Become.
In addition, since the silicon single crystal film of the SOI substrate is used as a membrane, high mechanical characteristics can be obtained.
US Pat. No. 5,619,476 US Pat. No. 6,958,255 US Pat. No. 5,369,544

When surface micromachining is used as in the above-mentioned conventional patent document 1, the membrane characteristics become non-uniform due to the residual stress of the silicon nitride film, and there are also problems in improving the yield.
Further, when using bonding of an SOI substrate as in Patent Document 2 of the above conventional example, particles cannot be completely removed, gas is generated at the bonding interface, and the membrane characteristics in the wafer surface are not uniform. This has a problem in improving the yield.
In addition, if the manufacturing method for etching the insulating layer of the SOI substrate of the conventional example described above in the sacrificial layer etching is directly applied to the manufacturing method of the CMUT, the parasitic capacitance is increased.

  In view of the above problems, the present invention provides a method for manufacturing a capacitive ultrasonic transducer that can improve the mechanical characteristics of a membrane, improve the yield, and suppress an increase in parasitic capacitance. It is intended to do.

The present invention provides a method for manufacturing a capacitive ultrasonic transducer configured as follows.
The manufacturing method of the capacitive ultrasonic transducer of the present invention includes:
A step of preparing an SOI substrate having an active layer on a support substrate with an insulating layer interposed therebetween;
Forming a through hole in the active layer or the support substrate;
Introducing a fluid for etching the insulating layer from the through-hole formed in the active layer or the support substrate, and etching the insulating layer to form a cavity;
Forming an insulating film inside a cavity formed by etching the insulating layer;
After forming an insulating film inside the cavity, sealing the through hole;
It is characterized by including.
In addition, the method for manufacturing the capacitive ultrasonic transducer of the present invention includes:
Patterning an active layer and an insulating layer of the SOI substrate into the shape of a membrane;
Forming an insulating film from the active layer side of the SOI substrate, etching the insulating film in another region, leaving the outer periphery of the membrane and a partial region of the support substrate;
Is further included.
The method for manufacturing a capacitive ultrasonic transducer according to the present invention further includes a step of forming a low dielectric constant material from the active layer side.
The method of manufacturing a capacitive ultrasonic transducer of the present invention includes a step of etching a region on the back surface side of the support substrate, which corresponds to a region where a membrane is formed in the active layer, to a predetermined depth. , Further included.
The method for manufacturing a capacitive ultrasonic transducer according to the present invention is characterized in that cavities formed by etching the insulating layer are arranged in a honeycomb shape to form one element of the capacitive ultrasonic transducer. To do.

According to the present invention, since the silicon single crystal film is used for the membrane, the mechanical properties of the membrane can be improved, and the bonding process is not required, so that the influence of conventional particles and gas generated at the bonding interface is eliminated. And the yield can be improved.
Further, according to the present invention, it is possible to suppress an increase in parasitic capacitance.

  The best mode for carrying out the present invention will be described by the following examples.

[Example 1]
In the first embodiment, a CMUT manufacturing method in which through holes are formed in a support substrate of an SOI substrate, a fluid is introduced from the through holes, and an insulating layer is etched will be described.
1 to 4 are views for explaining a method of manufacturing a CMUT in this embodiment.
Among these, FIG. 1 is a top view for explaining the entire CMUT manufactured by using the CMUT manufacturing method according to the present embodiment.
FIG. 2 is a diagram for explaining one element of the CMUT manufactured by the CMUT manufacturing method according to the present embodiment. FIG. 2A is an enlarged top view of one element of FIG. FIG. 2B is a cross-sectional view taken along the line AA ′ in FIG.
3 and 4 are process diagrams for explaining a method of manufacturing a CMUT in this embodiment.

First, the CMUT of this embodiment will be described with reference to FIG.
In FIG. 1, reference numeral 100 denotes a CMUT (capacitive ultrasonic transducer), and 101 denotes a region of one element of the CMUT.
In this embodiment, the CMUT 100 is composed of 8 × 8 elements 101. In the present embodiment, the CMUT 100 is an 8 × 8 element as described above for the sake of simplicity, but the present invention is not limited to such a configuration.
Further, the element 101 in this embodiment means one unit that transmits and receives ultrasonic waves.
Further, one through wiring is disposed for each element 101.

Next, a specific configuration of one element constituting such a CMUT will be described.
FIG. 2 is a diagram for explaining one element constituting the CMUT in this embodiment.
2A is an enlarged top view of one element of FIG. 1, and FIG. 2B is a cross-sectional view taken along line AA ′ of FIG. 2A.
In FIG. 2, 201 is one element of CMUT, 203 is a membrane, 204 is a cavity, 205 is a through hole, 206 is an upper electrode, 207 is a lower electrode pad, 208 is a through wiring, 209 is a circuit board, and 210 is a lower electrode. is there.
In this embodiment, the element 201 includes a membrane 203, a cavity 204, a through hole 205, an upper electrode 206, a lower electrode 210, a lower electrode pad 207, and a through wiring 208.
For the lower electrode 210, silicon that is a supporting substrate of the SOI substrate is used. Further, the CMUT 100 is bonded to the circuit board 209.

Next, the operation principle of the CMUT will be described.
When receiving an ultrasonic wave, the membrane 203 is displaced and the gap between the upper electrode 206 and the lower electrode 210 changes. An ultrasonic image can be obtained by detecting the amount of change in capacitance and performing signal processing.
In the case of transmitting an ultrasonic wave, a voltage is applied from the circuit board 209 to the upper electrode 206 or the lower electrode 210 to vibrate the membrane and transmit the ultrasonic wave.

Here, the dimension of each part of the element in a present Example is demonstrated.
Membrane diameter [Phi _m 40 [mu] m, the thickness _{t m} is 340 nm. The diameter of the cavity is 40 μm and the depth t _c is 100 nm, similar to the diameter of the membrane.
The diameter Φ _{h1 of the} through hole is 10 μm, and the depth t _h1 is 350 μm. The upper electrode 206 has a diameter of 20 [mu] m, the thickness _{t e} is 330 nm.
The lower electrode pad 207 is 200 μm × 200 μm and has a thickness of 330 nm.
The through-hole wiring 208 has a diameter Φ _h2 of 20 μm and a depth t _h2 of 340 μm. However, these values are examples, and other values can be taken.

Next, a method for manufacturing the CMUT in this embodiment will be described.
FIG. 3 and FIG. 4 show process drawings for explaining a method of manufacturing a CMUT in this embodiment.
3 and 4 show a cross-sectional view of one element for the sake of explanation, other elements are produced in the same manner.
3 and 4, 301 and 304 are active layers, 302 is an insulating layer, 303 is a support substrate, 305 is a through hole, 306 is an oxide film, 307 is a Boron diffused Poly-Si film, and 308 and 310 are Poly. The -Si film and 311 are resists. In manufacturing the CMUT in this embodiment, first, an SOI substrate including an active layer 302 with an insulating layer 302 interposed therebetween is prepared over a supporting substrate 301 (FIG. 3A).
The active layer 301 is made of silicon and has a thickness of 340 nm, the insulating layer 302 is made of an oxide film and has a thickness of 400 nm, and the support substrate 303 is made of silicon and has a thickness of 350 μm.
Next, separation from other elements and through holes for through wires are formed as follows.
The active layer 301 is subjected to photolithography to dry-etch silicon.
As a result, the active layer 304 to be a membrane later is electrically insulated from other elements.
Similarly, the support substrate is formed with the through holes 305 by photolithography and silicon deep-RIE.
Finally, the insulating layer 302 other than the region of the active layer 304 is removed by etching (FIG. 3B).

Next, an oxide film is formed in the through hole 305 in the following manner in order to electrically insulate the through wiring from the support substrate as the lower electrode.
The substrate manufactured in FIG. 3B is heat-treated in a pyrogenic oxidation furnace to form an oxide film 306 (FIG. 3C).
Next, a through wiring is formed. Poly-Si is deposited on the substrate manufactured in FIG. 3C as follows.
For the deposition of Poly-Si, LPCVD (Low Pressure Chemical Vapor Deposition) is used. Further, Boron diffusion is performed in order to increase the conductivity of the deposited Poly-Si film (FIG. 3D). Reference numeral 307 denotes a Boron diffused Poly-Si film.

Next, the through hole formed for the through wiring is closed.
A Poly-Si film 308 is formed over the substrate manufactured in FIG. 3D (FIG. 3E).
Thereby, a resist can be uniformly applied in a later process.
Of the substrate manufactured in FIG. 3E, an unnecessary Poly-Si film 308 is removed by dry etching.
Further, unnecessary regions of the diffused Poly-Si film 307 are similarly removed by dry etching (FIG. 3F).

Next, in order to remove the insulating layer by etching, a through hole is formed in the support substrate as follows.
The oxide film 306 is patterned by wet etching from the support substrate side by photolithography.
Further, a through hole 205 is formed by Si Deep-RIE using the oxide film 306 as a mask (FIG. 3G).

Next, the cavity is formed as follows.
In the substrate manufactured in FIG. 3G, vapor phase HF obtained by vaporizing HF is introduced from the through hole 205.
Thus, the oxide film 302 which is an insulating layer is etched to form the cavity 204 (FIG. 4H).
The size of the cavity can be determined by controlling the etching time.
Note that etching using vapor phase HF is performed in a vacuum chamber, and the etching is stopped by replacing the inside of the chamber with nitrogen gas. Further, regions other than the through wiring 208 and the through hole 205 are protected with a resist 311 so that they are not etched.
Although not shown, the surface of the substrate is protected by a Teflon (registered trademark) jig so as not to be exposed to HF gas.
In the present embodiment, the cavities formed by etching the insulating layer as described above are arranged in a honeycomb shape as shown in FIG. 2A to form one element of the CMUT.

Next, an insulating film is formed in the cavity as follows.
The substrate manufactured in FIG. 4H is dry-oxidized in an O ₂ atmosphere at a temperature of 1000 ° C.
As a result, an oxide film 309 is formed (FIG. 4I).
Note that a silicon nitride film may be formed instead of the oxide film 309.
Next, the through hole formed in the support substrate is sealed.
The through hole must be sealed in a vacuum state. If the through hole is sealed under atmospheric pressure, air is confined in the cavity.
If there is air inside the cavity, the vibration of the membrane is hindered, so the performance as a transducer is degraded.
A Poly-Si film 310 is formed over the substrate manufactured in FIG.
Thus, the through hole 205 is sealed with Poly-Si (FIG. 4J).
Further, since the Poly-Si film is formed in a vacuum state, the cavity is held in a vacuum.

Next, a region other than the Poly-Si film necessary for sealing the through hole formed in the support substrate is removed by etching, and a lower electrode pad is formed as follows.
In the substrate manufactured in FIG. 4J, photolithography and dry etching of the oxide film layer 309 are performed to form a lower electrode pattern.
After removing the resist, a film of Al is formed by sputtering or vapor deposition. Finally, photolithography and Al wet etching are performed to form a lower electrode pattern.
Through the above steps, the lower electrode pad 207 is formed (FIG. 4K).

Next, the upper electrode is formed as follows.
In the substrate manufactured in FIG. 4K, the oxide film on the active layer side is removed by dry etching with a gas such as CHF ₃ .
Next, Al is formed into a film by sputtering or vapor deposition, and photolithography of the upper electrode and wet etching of Al are performed.
Through the above steps, the upper electrode 206 is formed, and the CMUT manufacturing process is completed (FIG. 4L).
Finally, the substrate manufactured in FIG. 4L and the circuit substrate 209 are bonded to each other.
Thereby, signal processing of transmission / reception of ultrasonic waves becomes possible (FIG. 4M).

In this embodiment, a mode is described in which a through hole is formed in a support substrate of an SOI substrate, a gas phase HF is introduced from the through hole, an oxide film that is an insulating layer is removed by etching, and a cavity is formed.
As another method different from the above, a cavity may be formed by forming a through hole in the active layer of the SOI substrate, introducing vapor phase HF from the through hole, and etching away the oxide film as the insulating layer.
In this case, processing time can be shortened as compared with a method of forming a through hole in the support substrate.
However, when processing a membrane, it is necessary to consider that the mechanical properties may be inferior to a membrane made of only a silicon single crystal.

According to the present embodiment, since the silicon single crystal film is used for the CMUT membrane, the mechanical properties of the membrane can be improved.
Further, since this embodiment does not require a substrate bonding step, the influence of conventional particles and gas generated at the bonding interface is eliminated, and the yield can be improved.

[Example 2]
In the second embodiment, a configuration example will be described in which a region on the back side of the support substrate located corresponding to a region where a membrane is formed in the active layer is etched to a predetermined depth.
Specifically, an example of a CMUT manufacturing method in which a support substrate of an SOI substrate is etched back, a through hole is formed in the region, a fluid is introduced from the through hole, and the insulating layer is etched will be described.
First, the CMUT of this embodiment will be described.
FIG. 5 is a diagram for explaining one element constituting the CMUT in this embodiment. FIG. 5A is an enlarged top view of one element, and FIG. 5B is a BB ′ cross-sectional view of FIG. 5A.
In FIG. 5, 401 is one element of CMUT, 403 is a membrane, 404 is a cavity, 405 is a through hole, and 406 is an upper electrode.
Reference numeral 407 denotes a lower electrode pad, 408 denotes a through wiring, 409 denotes a circuit board, 410 denotes a lower electrode, 411 denotes a groove, and 412 denotes a Poly-Si film.

Similar to the first embodiment, the CMUT of the present embodiment is composed of 8 × 8 elements. In the present embodiment, the CMUT 100 is an 8 × 8 element as described above for the sake of simplicity, but the present invention is not limited to such a configuration.
In this embodiment, the element 401 includes a membrane 403, a cavity 404, a through hole 405, a cavity sealing poly-Si 412, and an upper electrode 406.
Further, a lower electrode 410, a lower electrode pad 407, and a through wiring 408 are provided. The lower electrode 410 uses silicon which is a support substrate for the SOI substrate.
Further, the CMUT of this embodiment is also bonded to the circuit board 409 as in the first embodiment.

Here, the dimension of each part of the element in a present Example is demonstrated.
The membrane 403 has a diameter Φ _M of 10 μm and a thickness t _M of 340 nm.
The diameter of the cavity is 10 μm, the same as the diameter of the membrane, and the depth t _c is 100 nm.
The diameter Φ _{H1 of the} through hole is 1 μm, and the depth t _H1 is 40 μm. The depth t _H2 of the groove 411 is 310 μm.
The upper electrode 406 has a diameter of 5 μm and a thickness t _E of 330 nm. The lower electrode pad 407 is 200 μm × 200 μm and the thickness is 330 nm.
The diameter Φ _H2 of the through wiring 408 is 20 μm, and the depth t _H2 is 350 μm. However, these values are examples, and other values can be taken.

Next, a method for manufacturing the CMUT in this embodiment will be described.
The CMUT manufacturing method of this embodiment is basically the same as that of the first embodiment. The manufacturing method of this embodiment can be implemented by adding a step of forming a groove in the support substrate between the steps of FIGS. 3F and 3G described in the first embodiment.
The groove 411 is formed by back-etching the support substrate only in the region where a plurality of membranes 403 are arranged.
As a back etching method, silicon deep-RIE is used. In order to photolithography the through hole 405 at the bottom of the groove 411, a resist spray coating and a projection type exposure apparatus are used.

Generally, it is difficult to penetrate a silicon substrate having a thickness of 350 μm with a hole diameter of 10 μm or less.
When designing the diameter [Phi _M of the membrane with 10 [mu] m, the diameter [Phi _H1 of the through hole 405 can not be disposed lower electrode 410 in 10 [mu] m.
Therefore, the support substrate is back-etched only in the region where a plurality of membranes are arranged. Thereby, it is possible to form a through hole having a diameter of 1 μm.
As a result, a membrane having a diameter of 10 μm can be formed.

According to the present embodiment, since the silicon single crystal film is used for the CMUT membrane, the mechanical properties of the membrane can be improved.
Further, since this embodiment does not require a substrate bonding step, the influence of conventional particles and gas generated at the bonding interface is eliminated, and the yield can be improved.

[Example 3]
In Example 3, a CMUT manufacturing method in which an active layer of an SOI substrate is etched for each membrane, an insulating film is formed from the active layer side, and the insulating layer of the SOI substrate is etched will be described.
6 to 8 are views for explaining a method of manufacturing a CMUT in this embodiment.
Among these, FIG. 6 is a diagram for explaining one element of the CMUT manufactured by the CMUT manufacturing method in the present embodiment, and FIG. 6A is an enlarged top view of the one element of FIG. 6 (b) is a sectional view taken along the line CC 'of FIG. 6 (a).
7 and 8 are process diagrams for explaining a method of manufacturing a CMUT in this embodiment.

First, the CMUT of this embodiment will be described.
FIG. 6 is a diagram for explaining one element constituting the CMUT in this embodiment. 6A is an enlarged top view of one element, and FIG. 6B is a cross-sectional view taken along the line CC ′ of FIG. 6A.
In FIG. 6, reference numeral 501 denotes one element of a CMUT (capacitive ultrasonic transducer), 503 denotes a membrane, 504 denotes a cavity, 505 denotes a through hole, and 506 denotes an upper electrode.
Reference numeral 507 denotes a lower electrode pad, 508 denotes a through wiring, 509 denotes a circuit board, 510 denotes a lower electrode, and 511 denotes a wiring.

Similar to the first embodiment, the CMUT of the present embodiment is composed of 8 × 8 elements. In the present embodiment, the CMUT 100 is an 8 × 8 element as described above for the sake of simplicity, but the present invention is not limited to such a configuration.
The element 501 includes a membrane 503, a cavity 504, a through hole 505, an upper electrode 506, a wiring 511 between upper electrodes, a lower electrode 510, a lower electrode pad 507, and a through wiring 508.
The lower electrode 510 uses a silicon substrate itself. Further, the CMUT of this embodiment is also bonded to the circuit board 509 as in the first embodiment.

Here, the dimension of each part of the element in a present Example is demonstrated.
The membrane 503 has a diameter Φ _m ′ of 40 μm and a thickness t _m ′ of 340 nm.
The diameter of the cavity is 40 μm and the depth t _c ′ is 100 nm, similar to the diameter of the membrane. The diameter Φ _h1 ′ of the through hole is 10 μm, and the depth t _h1 ′ is 350 μm.
The upper electrode 506 has a diameter of 20 μm and a thickness t _e ′ of 330 nm. The lower electrode pad 507 has a thickness of 200 μm × 200 μm and a thickness of 330 nm.
The through-wiring 508 has a diameter Φ _h2 ′ of 20 μm and a depth t _h2 ′ of 340 μm. However, these values are examples, and other values can be taken.

Next, a method for manufacturing the CMUT in this embodiment will be described.
7 and 8 are process diagrams for explaining a method of manufacturing a CMUT in this embodiment.
The first step of the process flow of the present embodiment is the same as that of FIG. 3A to FIG. 3F of the first embodiment. Therefore, in FIG. 7, the process of FIG.
7 and 8 are cross-sectional views of one element for the sake of explanation, other elements are produced in the same manner.
7 and 8, 601 and 602 are silicon nitride films, 605 is an oxide film, 604 is a resist, 606 and 607 are Poly-Si films, and 608 is a region.

In the present embodiment, the first step of FIG. 7A is the same as the step of FIG.
Next, the active layer and the insulating layer of the SOI substrate are patterned into a membrane shape.
For patterning, photolithography and dry etching using CF ₄ as an etching gas are used.
Accordingly, a membrane 503 and a cavity 504 can be formed later (FIG. 7B).

Next, an insulating film is formed from the active layer side of the SOI substrate, and a silicon nitride film is formed to etch the insulating film in other regions while leaving the outer periphery of the membrane and a part of the support substrate. Filming and patterning are performed as follows.
A silicon nitride film is formed to a thickness of 200 nm by LPCVD on the substrate manufactured in FIG.
Further, the silicon nitride film is patterned so as to have the shapes 601 and 602 shown in FIG.
For patterning, photolithography and dry etching using CF ₄ as an etching gas are used.
The silicon nitride film 601 functions as an etching stop layer for an oxide film that is an insulating layer.
This is because the etching rate of the thermal oxide film by vapor phase HF is 66 nm / min, whereas the etching rate of the silicon nitride film by vapor phase HF is 1 to 2 nm / min.
The layer between the silicon nitride film 601 and the silicon nitride film 602 is removed by etching.
Next, in order to etch away the insulating layer, a through hole is formed in the support substrate as follows.
The oxide film is patterned by wet etching from the support substrate side by photolithography.
Further, through holes 505 are formed by Si Deep-RIE using the oxide film as a mask (FIG. 7D).

Next, the cavity is formed as follows.
In the substrate manufactured in FIG. 7D, vapor phase HF obtained by vaporizing HF is introduced from the through hole 505.
Thus, the oxide film which is an insulating layer is etched to form a cavity 504 (FIG. 7E).
Etching using vapor phase HF is performed in the same manner as in Example 1. In this embodiment, the size of the cavity can be determined by the silicon nitride films 601 and 602. As a result, even if the etching rate of the oxide film by the vapor phase HF varies within the SOI plane, the etching time may be set longer.
Note that regions other than the through wiring 508 and the through hole 505 are protected by a resist 604 so as not to be etched. Although not shown, the surface of the substrate is protected by a Teflon (registered trademark) jig so as not to be exposed to HF gas.
In the present embodiment, the cavities formed by etching the insulating layer as described above are arranged in a honeycomb shape as shown in FIG. 6A to form one element of the CMUT.

Next, an insulating film is formed inside the cavity and between the silicon nitride films 601 and 602. The substrate manufactured in FIG. 7E is dry-oxidized in an O ₂ atmosphere at a temperature of 1100 ° C. Thus, an oxide film 605 is formed (FIG. 7F).
Next, the through hole formed in the support substrate is sealed as follows.
The through hole must be sealed in a vacuum state.
If the through hole is sealed under atmospheric pressure, air is confined in the cavity. If there is air inside the cavity, the vibration of the membrane is hindered, so the performance as a transducer is degraded.
Poly-Si 606 is formed over the substrate manufactured in FIG. Thereby, the through-hole 505 is sealed with Poly-Si.
In addition, since the Poly-Si film is formed in a vacuum state, the cavity is held in a vacuum (FIG. 8G).

Next, the lower electrode pad is formed as follows.
First, regions other than the Poly-Si film necessary for sealing the through holes on the surface of the support substrate are removed by etching.
On the surface on the active layer side, the Poly-Si film is etched away except for the silicon nitride films 601 and 602 and the region 607 between them.
Next, in the substrate manufactured in FIG. 8G, photolithography and dry etching of the oxide film layer 605 are performed to form a lower electrode pattern.
After removing the resist, a film of Al is formed by sputtering or vapor deposition.
Finally, photolithography and Al wet etching are performed to form a lower electrode pattern. Through the above steps, the lower electrode pad 507 is formed (FIG. 8H).

Next, an upper electrode is formed. On the substrate manufactured in FIG. 8H, Al is formed by sputtering or vapor deposition, and photolithography of the upper electrode and wet etching of Al are performed.
Through the above steps, the upper electrode 506 is formed, and the CMUT manufacturing process is completed.
Finally, the substrate on which the upper electrode is formed and the circuit board 509 are bonded. Thereby, signal processing for transmission / reception of ultrasonic waves becomes possible (FIG. 8I).

In this embodiment, a mode is described in which a through hole is formed in a support substrate of an SOI substrate, a gas phase HF is introduced from the through hole, an oxide film that is an insulating layer is removed by etching, and a cavity is formed.
As another method different from the above, a cavity may be formed by forming a through hole in the active layer of the SOI substrate, introducing vapor phase HF from the through hole, and etching away the oxide film as the insulating layer.
In this case, processing time can be shortened as compared with a method of forming a through hole in the support substrate.
However, when processing the membrane, it is necessary to consider that the mechanical properties may be inferior to a membrane made of only a silicon single crystal.

In a region 608 shown in FIG. 8I, a capacitance is generated between the wiring 511 between the upper electrodes and the lower electrode 510.
This becomes part of the parasitic capacitance of the CMUT. In order to increase the sensitivity of CMUT, it is necessary to reduce the parasitic capacitance.
In order to reduce the capacitance between the wiring of the upper electrode and the lower electrode, it is preferable to use a material having a low dielectric constant as low as possible.
Therefore, in this embodiment, the silicon nitride film corresponding to the region 608 is removed by etching in the step of FIG.
Further, an oxide film 605 is formed to insulate the wiring from the lower electrode. This is because the relative dielectric constant of the silicon nitride film is 6.5 to 7.1, which is larger than the relative dielectric constant of SiO ₂ to 3.7 to 3.9.
If the silicon nitride film 610 is left to insulate the wiring and the lower electrode as shown in FIG. 8J, the capacitance of the region 608 becomes larger.

The material between the upper electrode wiring 511 and the lower electrode 510 is not limited to this embodiment.
In place of the Poly-Si 607 and the oxide film 605 surrounded by the region 608, there is a method in which Fluorinated Silica Glass (FSG) that is fluorine-added SiO ₂ or SiOF is formed by CVD and patterned by dry etching.
Since these materials have a relative dielectric constant lower than that of the silicon oxide film, they are effective in reducing the parasitic capacitance in the wiring portion.

According to the present embodiment, since the silicon single crystal film is used for the CMUT membrane, the mechanical properties of the membrane can be improved.
In addition, since the present invention does not require a substrate bonding step, the influence of conventional particles and gas generated at the bonding interface is eliminated, and the yield can be improved. In this embodiment, since a low dielectric constant material is formed between the wiring between the upper electrodes and the lower electrode, an increase in parasitic capacitance can be prevented.

According to the CMUT manufacturing method of each of the embodiments described above, it is possible to realize a CMUT manufacturing method that can improve the yield of CMUT using a silicon single crystal having good mechanical properties as a membrane.
Moreover, CMUT produced by these can be suitably applied to an ultrasonic probe in the construction / material / medical fields.

It is a top view for demonstrating the whole CMUT produced using the manufacturing method of CMUT (capacitive ultrasonic transducer) in Example 1 of this invention. It is a figure for demonstrating one element which comprises CMUT in Example 1 of this invention. 2A is an enlarged top view of one element of FIG. 1, and FIG. 2B is a cross-sectional view taken along line A-A ′ of FIG. It is a figure explaining the manufacturing method of CMUT (capacitive ultrasonic transducer) in Example 1 of the present invention, and Drawing 3 (A) to (G) is a figure explaining the manufacturing process. It is a figure explaining the manufacturing method of CMUT (capacitive ultrasonic transducer) in Example 1 of the present invention, and Drawing 4 (H) to (M) explains the manufacturing process following Drawing 3 (A) to (G). It is a figure to do. It is a figure for demonstrating one element which comprises CMUT in Example 2 of this invention. FIG. 5A is an enlarged top view of one element, and FIG. 5B is a cross-sectional view along B-B ′ of FIG. It is a figure for demonstrating one element which comprises CMUT in Example 3 of this invention. 6A is an enlarged top view of one element, and FIG. 6B is a cross-sectional view taken along the line C-C ′ of FIG. It is a figure explaining the manufacturing method of CMUT (capacitive ultrasonic transducer) in Example 3 of the present invention, and Drawing 7 (A) to (F) is a figure explaining the manufacturing process. It is a figure explaining the manufacturing method of CMUT (capacitive ultrasonic transducer) in Example 3 of the present invention, and Drawing 8 (G) to (J) explains the manufacturing process following Drawing 7 (A) to (F). It is a figure to do.

Explanation of symbols

100: CMUT
101, 201, 401, 501: One element 203, 403, 503 of CMUT: Membrane 204, 404, 504: Cavity 205, 305, 405, 505: Through hole 206, 406, 506: Upper electrode 207, 407, 507: Lower electrode pads 208, 408, 508: Through wirings 209, 409, 509: Circuit boards 210, 410, 510: Lower electrodes 301, 304: Active layer 302: Insulating layer 303: Support substrates 306, 309, 605: Oxide film 307 : Boron diffused Poly-Si films 308, 310, 412, 606, 607: Poly-Si films 311, 604: Resist 411: Groove 511: Wiring 601, 602: Silicon nitride film 608: Region

Claims (5)

A method for manufacturing a capacitive ultrasonic transducer, comprising:
A step of preparing an SOI substrate having an active layer on a support substrate with an insulating layer interposed therebetween;
Forming a through hole in the active layer or the support substrate;
Introducing a fluid for etching the insulating layer from the through-hole formed in the active layer or the support substrate, and etching the insulating layer to form a cavity;
Forming an insulating film inside a cavity formed by etching the insulating layer;
After forming an insulating film inside the cavity, sealing the through hole;
A method for manufacturing a capacitive ultrasonic transducer, comprising: Patterning an active layer and an insulating layer of the SOI substrate into the shape of a membrane;
Forming an insulating film from the active layer side of the SOI substrate, etching the insulating film in another region, leaving the outer periphery of the membrane and a partial region of the support substrate;
The method of manufacturing a capacitive ultrasonic transducer according to claim 1, further comprising: Forming a low dielectric constant material from the active layer side,
The method of manufacturing a capacitive ultrasonic transducer according to claim 2, further comprising: Etching the region on the back surface side of the support substrate corresponding to the region where the membrane is formed in the active layer to a predetermined depth;
The method of manufacturing a capacitive ultrasonic transducer according to any one of claims 1 to 3, further comprising:   5. The capacitor according to claim 1, wherein cavities formed by etching the insulating layer are arranged in a honeycomb shape to form one element of the capacitive ultrasonic transducer. 6. Method of manufacturing type ultrasonic transducer.

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