JP2009164302A - Image sensor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve an image sensor with multiple pixels for higher resolution by making a surface wiring easy to be formed for decreased number of bumps, with no degradation in, for example, heat-proof cycle characteristics and sensitivity, with occurrence of flash suppressed to the least. <P>SOLUTION: The image sensor includes a plurality of pixels 1 arranged in two dimension manner, a plurality of pixel division grooves 2 for dividing the plurality of pixels 1, and metal wirings 3 so formed on the surface side as to connect all of the plurality of pixels 1. The metal wirings 3 are formed only at a part of the bottom surface and side surface of the pixel division grooves 2 on the surface of the pixel division grooves 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image sensor in which a plurality of pixels are separated by a separation groove and arranged two-dimensionally, and a method for manufacturing the same.

As an image sensor in which a plurality of pixels are separated by a separation groove and arranged two-dimensionally, for example, there is an infrared image sensor in which each pixel is configured by a quantum well type infrared photo detector (QWIP).
In particular, infrared image sensors that can operate at a plurality of wavelengths are required, and an infrared image sensor in which each pixel is configured by two-wavelength QWIP having a structure having sensitivity in two wavelength bands has been proposed ( For example, see Patent Document 1).

As shown in FIG. 7, the two-wavelength QWIP constituting each pixel of such an infrared image sensor has a lower contact layer, a first multiple quantum well (MQW) having sensitivity to one wavelength band. A layer, a common contact layer, a second multiple quantum well (MQW) layer having sensitivity to other wavelength bands, and an upper contact layer are sequentially stacked.
Then, three bumps (metal bumps) are formed on one pixel so as to be connected to each of these three contact layers, and a bias is applied via the bumps connected to the common contact layer, A signal current from the first MQW layer is taken out from the bump connected to the lower contact layer, and a signal current from the second MQW layer is taken out from the bump connected to the upper contact layer.
JP 2000-323744 A

  However, when three bumps are formed for each pixel, as in the case of the infrared image sensor in which each pixel is configured by the above-described two-wavelength QWIP, it is difficult to narrow the pitch (miniaturization), and a demand for higher resolution by increasing the number of pixels is required. It is difficult to satisfy. This is because the bump is formed of a metal such as In, for example, and there is a limit to the miniaturization thereof, and if the bump height is reduced due to the miniaturization of the bump, the heat cycle resistance is deteriorated.

Therefore, in order to increase the resolution by increasing the number of pixels, instead of reducing the bump size, in order to reduce the number of bumps per pixel, instead of bumps, metal wiring (surface wiring) ).
For example, as shown in FIG. 8, it is conceivable to form a metal wiring so as to cross each pixel and a separation groove that separates each pixel.

However, the depth of the separation groove is, for example, about 5 μm, and since the unevenness of the separation groove portion is severe, it is difficult to form a metal wiring pattern.
In this case, for example, it is conceivable to form the metal wiring after thickening the passivation film formed on the surface to fill the separation groove and further planarizing the surface by polishing or the like.
However, in this case, a polishing step for flattening is required, and the process becomes complicated. In addition, in the case of an element that is cooled to about 70K and used, for example, QWIP, it is not preferable to fill the isolation groove because the heat cycle property is likely to deteriorate.

For example, as shown in FIG. 9, it is conceivable to form a surface wiring on the bottom surface of the separation groove that separates each pixel.
However, when patterning is actually performed on the bottom surface of the separation groove, the width of the separation groove needs to be considerably widened. For this reason, the area of each pixel is reduced, and as a result, the sensitivity is lowered, which is not practical. Further, in order to form the surface wiring on the bottom surface of the separation groove, a resist is formed so as to cover a part of the bottom surface of the separation groove as shown in FIG. After the resist is removed and the resist is removed, as shown in FIG. 11, it remains as burrs on the metal wiring formed on the bottom surface of the separation groove. If such burrs remain, it may be adversely affected by a process such as peeling off in a later manufacturing process, which is not preferable. Normally, the burrs generated along the resist pattern for forming the surface wiring on the bottom surface of the separation groove are linear and long, and peeling and reattaching may cause defects such as short circuit between pixels. It might be.

  Therefore, for example, surface wiring can be easily formed without causing burrs to occur as much as possible without degrading characteristics such as heat cycle characteristics and sensitivity, and the number of bumps is reduced, and high resolution is achieved by increasing the number of pixels. I want to realize.

For this reason, this image sensor is a metal formed on the surface side so as to connect a plurality of pixels arranged two-dimensionally, a plurality of pixel separation grooves that separate the plurality of pixels, and all of the plurality of pixels. The metal wiring is required to be formed only on a part of the side surface and the bottom surface of the pixel separation groove on the surface of the pixel separation groove.
In this image sensor manufacturing method, a semiconductor multilayer structure is formed on a substrate, and a plurality of pixel separation grooves are formed in the semiconductor multilayer structure so that a plurality of pixels arranged two-dimensionally are formed. In the pixel separation groove, a mask is formed so as to cover only a part of the wiring metal formed on the bottom surface of the pixel separation groove, so that the wiring metal formed on the side surface of the pixel separation groove remains. It is a requirement to form a metal wiring by removing the wiring metal by anisotropic etching.

  Therefore, according to the present image sensor and its manufacturing method, for example, surface wiring can be easily formed without causing burrs to occur as much as possible without deteriorating characteristics such as heat cycle characteristics and sensitivity. There is an advantage that the number of pixels can be reduced to achieve higher resolution by increasing the number of pixels.

Hereinafter, an image sensor and a manufacturing method thereof according to the present embodiment will be described with reference to FIGS.
Hereinafter, the present invention is an infrared image sensor in which, for example, a plurality of pixels are separated two-dimensionally by a separation groove and can generate a photocurrent according to an incident amount of infrared rays, and has different wavelength bands. Quantum Well Infrared Photodetector (QWIP; Two-Wave QWIP; Infrared Detector; Photosensor) Using Two Multi Quantum Well (MQW) Layers Sensitivity to A case where the present invention is applied to a quantum well infrared image sensor in which each pixel is configured will be described as an example.

A quantum well infrared image sensor (image sensor element) according to the present embodiment includes, for example, a plurality of pixels (elements) 1 arranged two-dimensionally and a plurality of pixels 1 that separate the plurality of pixels 1 as shown in FIG. Pixel isolation trench (element isolation trench) 2 and metal wiring (surface wiring; wiring metal; contact metal) 3 formed on the surface side so that all of the plurality of pixels 1 are connected.
As shown in FIG. 1, the metal wiring 3 has a side surface (a surface perpendicular to the substrate; a side surface of the pixel 1) and a plurality of pixels on the surface (side surface and bottom surface) of the pixel separation groove 2. It is formed only on the bottom surface of the intersection 4 where the pixel separation grooves 2 intersect.

Here, as shown in FIG. 1, the metal wiring 3 formed on the bottom surface of the intersecting portion 4 is formed so as to connect adjacent pixels 1 among the plurality of pixels 1. A specific configuration example of the metal wiring 3 formed on the bottom surface of the intersection 4 will be described later.
This quantum well type infrared image sensor comprises a semiconductor crystal having a structure in which two MQW layers having sensitivity to different wavelength bands are sandwiched between contact layers on a semiconductor substrate [see FIG. 2 (A)], A plurality of pixels 1 are formed by being separated by pixel separation grooves 2 extending vertically and horizontally (see FIG. 1).

In the present embodiment, each pixel 1 is configured by a two-wavelength QWIP having a structure having two sensitivity wavelengths.
Specifically, the structure of each pixel 1, that is, the structure (element structure) of two-wavelength QWIP is formed on a semiconductor substrate (for example, a GaAs substrate) 10 as shown in FIGS. 2 (A) and 2 (B). Contact layer (for example, GaAs contact layer) 11, first MQW layer (absorbing layer; photosensitive layer) 12 that absorbs light (in this case, infrared light) in one wavelength band, common contact layer (for example, GaAs contact layer) 13, and other wavelengths It has a structure (semiconductor laminated structure) in which a second MQW layer (absorbing layer; photosensitive layer) 14 that absorbs light in the band (here, infrared rays) and an upper contact layer (for example, a GaAs contact layer) 15 are sequentially laminated. 2A and 2B, a passivation film provided so as to cover the metal wiring 3 is not shown for easy understanding of the description.

The lower contact layer 11 is not separated for each pixel by the pixel separation groove 2 as shown in FIG. That is, the lower contact layer 11 is connected to all pixels.
In this embodiment, as shown in FIG. 2A, one contact groove 5 is formed in each pixel 1 so that the surface of the common contact layer 14 is exposed.
In this embodiment, as shown in FIGS. 2A and 2B, a passivation film (insulating film) is formed so as to cover the entire surface of the semiconductor laminated structure (semiconductor crystal) constituting the quantum well infrared image sensor. A SiN film or the like) 6 is formed.

In the present embodiment, as shown in FIGS. 2A and 2B, the first surface is formed so that the surface of the common contact layer 13 is exposed at the portion formed on the bottom surface of the contact groove 5 of the passivation film 6. A contact hole 7 is formed.
Further, in the present embodiment, as shown in FIGS. 2A and 2B, the surface of the upper contact layer 15 is exposed at the portion formed on the upper surface of each pixel 1 of the passivation film 6. One second contact hole 8 is formed in each pixel 1.

In this embodiment, as shown in FIGS. 2A and 2B, one bump is formed on each pixel 1 on the surface side of each pixel 1 via a passivation film 6 (metal bump; bump electrode). ; Here, In bumps) 9 are formed. That is, this two-wavelength QWIP is a two-wavelength QWIP of one pixel and one bump that can be driven by one bump per pixel.
Further, in the present quantum well infrared image sensor, as shown in FIGS. 2A and 2B, the side surface of the pixel separation groove 2 (side surface of the pixel 1) and the intersection 4 where the plurality of pixel separation grooves 2 intersect. And the surface of the common contact layer 13 are exposed from the bump formation region and the region from the side surface of the pixel separation groove 2 (side surface of the pixel 1) to the second contact hole 8 where the surface of the upper contact layer 15 is exposed. The metal wiring 3 is formed in a region up to the contact groove 5 (there is a contact hole 7 inside). That is, the metal wiring 3 connects the portion 3A formed on the side surface of the pixel separation groove 2 (side surface of the pixel 1), the portion 3B formed on the bottom surface of the intersecting portion 4, the bump 9 and the common contact layer 13. And a portion 3D for connecting the upper contact layer 15 and the portion 3A formed on the side surface of the pixel isolation trench 2.

A part 3C of the metal wiring 3 is composed of an extraction electrode and a bump base layer connected to the common contact layer 13, and is not formed so as to connect all the pixels 1. For this reason, in order to distinguish from the metal wirings 3A, 3B, and 3D formed so as to connect all the pixels 1, they are referred to as bump connection metal wirings.
2A and 2B, the bump 9 and the common contact layer 13 are connected through the first contact hole 7 by the metal wiring 3C. Here, the metal wiring 3 </ b> C connecting the bump 9 and the common contact layer 13 extends from the surface of the common contact layer 13 exposed through the first contact hole 7 of the passivation film 6 to the lower side of the bump 9. Further, it is formed on the surface of the passivation film 6.

  Further, as shown in FIGS. 2A and 2B, the metal wirings 3A and 3B and the upper contact layer formed so as to connect all the pixels 1 through the second contact holes 8 by the metal wiring 3D. 15 is connected. Here, the metal wirings 3A and 3B formed so as to connect all the pixels 1, that is, the side surface of the pixel separation groove 2 (side surface of the pixel 1) and the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect. The metal wiring 3D that connects the formed metal wirings 3A and 3B and the upper contact layer 15 is exposed from the surface of the upper contact layer 15 through the second contact hole 8 of the passivation film 6 to the pixel isolation trench 2. It is formed on the surface of the passivation film 6 so as to extend to the side surface (side surface of the pixel 1).

Here, the metal wiring 3B formed on the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect, that is, the metal wiring for connecting the metal wiring 3A formed on the side surface of each pixel 1 (connection metal) As shown in FIG. 2B, the wiring 3B is formed on a diagonal line of a quadrangular region formed between the four adjacent pixels 1.
In the present embodiment, the metal wirings 3A, 3B, 3D formed so as to connect all the pixels 1 and the lower contact layer 11 connected to all the pixels 1 are provided, for example, on the outer periphery of the element. The signal processing circuit chip is connected to the bias supply unit. That is, in this embodiment, since the signal processing circuit is provided in the outer periphery of the element, these metal wirings 3A, 3B, 3D and the lower contact layer 11 extend from each pixel 1 to the outer periphery of the element. Thereby, a bias voltage is applied to the second MQW layer 14 provided on the upper side of each pixel 1 via the metal wirings 3A, 3B, 3D, while the first MQW layer provided on the lower side of each pixel 1 is applied. A bias voltage is applied to 12 via the lower contact layer 11.

  Note that metal wirings formed so as to connect all the pixels 1 (that is, metal wirings 3A and 3B formed on the side surfaces of the pixel separation grooves 2 and the bottom surfaces of the intersections 3 where the plurality of pixel separation grooves 2 intersect, and The metal wiring 3D connecting the metal wiring 3A formed on the side surface of the pixel isolation trench 2 and the upper contact layer 15 is called a bias metal wiring, and the upper contact layer 15 and the lower contact layer 11 are used as the bias contact. Call a layer.

  On the other hand, the bumps 9 formed one by one in each pixel 1 and connected to the common contact layer 13 by the metal wiring 3C are formed in each signal processing circuit chip to which each pixel corresponds, for example, by flip chip bonding. Separately electrically connected to the cell. As a result, signal currents from the first MQW layer 12 and the second MQW layer 14 are taken out via the common contact layer 13, the metal wiring 3C, and the bumps 9, and are sent to each cell in the signal processing circuit chip. ing. In this case, two QWIPs constituted by the MQW layers 12 and 14 provided on the upper and lower sides cannot be driven simultaneously, but these two QWIPs may be operated in a time division manner.

The metal wiring 3C that connects the bump 9 and the common contact layer 13 is called a signal extraction metal wiring, and the common contact layer 13 is called a signal extraction contact layer.
Next, the manufacturing method of the image sensor (quantum well type | mold infrared image sensor; image sensor element) concerning this embodiment is demonstrated, referring FIG. 3, FIG.
The following description will focus on the formation process of one pixel (two-wavelength QWIP of one pixel and one bump; QWIP element) constituting the quantum well infrared image sensor and the metal wiring formed around the pixel.

  First, as shown in FIG. 3A, a lower contact layer (for example, a GaAs contact layer) 11 on a semiconductor substrate (for example, a GaAs substrate) 10 and a first MQW that absorbs light in one wavelength band (here, infrared rays). Layer (absorbing layer; photosensitive layer) 12, common contact layer (for example, GaAs contact layer) 13, second MQW layer (absorbing layer; photosensitive layer) 14 for absorbing light in other wavelength bands (infrared rays in this case), upper contact layer A semiconductor multilayer structure (wafer) in which (for example, GaAs contact layers) 15 are sequentially laminated is formed.

  Next, as shown in FIGS. 3A and 3A, the upper contact layer 15 and the second MQW layer 14 are removed to form the contact trench 5 reaching the common contact layer 13, and the lower contact layer 11 A plurality of pixel separation grooves 2 having a depth up to just above are formed. As a result, a plurality of pixels 1 arranged two-dimensionally are formed. One contact groove 5 is formed in each of the plurality of pixels 1.

Next, as shown in FIGS. 3A and 3A, a passivation film (insulating film) 6 is formed on the surface (entire surface) of the wafer.
Next, as shown in FIGS. 3A and 3A, contact holes 7 and 8 are formed at desired positions of the passivation film 6. That is, the first contact hole 7 is formed in the portion of the passivation film 6 formed on the bottom surface of the contact groove 5 so that the surface of the common contact layer 13 is exposed, and the passivation film 6 is formed on the upper surface of the pixel 1. A second contact hole 8 is formed in the exposed portion so that the surface of the upper contact layer 15 is exposed.

Thus, after forming the passivation film 6 on the entire surface of the wafer and opening the contact holes 7 and 8, as shown in FIGS. 3B and 3B, on the surface (the entire surface), For example, the wiring metal 3X is deposited and formed by sputtering or the like.
Subsequently, in order to form a desired metal wiring 3 [see FIGS. 3D and 3D], a desired pattern is formed on the wiring metal 3X as shown in FIGS. 3C and 3C. A mask 20 is formed. Here, a resist is applied on the surface (the entire surface) of the wiring metal 3X, and this is patterned into a desired shape to form a mask (resist mask; resist pattern) 20.

  In the present embodiment, as shown in FIGS. 3C and 3C, the surface of each of the plurality of pixels 1 is provided only on the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect in the pixel separation groove 2. Above, the region from the side surface of the pixel isolation trench 2 (side surface of the pixel 1) to the second contact hole 8 where the surface of the upper contact layer 15 is exposed, and the surface of the common contact layer 13 from the bump formation region are exposed. A resist pattern 20 is formed only in the region up to the first contact hole 7 (contact groove 5).

  In particular, as shown in FIGS. 3C and 3C, in the pixel separation groove 2, a resist is formed so as to cover only the wiring metal 3X formed on the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect. A pattern 20 is formed. Here, the resist pattern 20 formed so as to cover the wiring metal 3 </ b> X formed on the bottom surface of the intersecting portion 4 is a diagonal line of a rectangular region formed between four adjacent pixels 1 among the plurality of pixels 1. Form on top.

Using the resist pattern (mask) 20 thus formed, unnecessary portions of the wiring metal 3X are removed by ion milling to form desired metal wirings 3 (3A to 3D).
In this case, after the wiring metal 3X is removed by ion milling, the wiring metal 3X remains on the side surface of the pixel separation groove 2, that is, the side surface (periphery) of each pixel 1 in addition to the region where the resist pattern 20 is formed. Become. That is, as the desired metal wiring 3, from the side surface of the pixel separation groove 2 (side surface of the pixel 1), the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect, and the side surface of the pixel separation groove 2 (side surface of the pixel 1). In a region from the surface of the upper contact layer 15 to the second contact hole 8 and a region from the bump formation region to the first contact hole 7 (contact groove 5) from which the surface of the common contact layer 13 is exposed, The metal wiring 3 (3A to 3D) is formed in a lump.

In the present embodiment, the metal wiring 3 </ b> B formed on the bottom surface of the intersection 4 is formed on a diagonal line of a quadrangular region formed between the four adjacent pixels 1.
In this embodiment, ion milling is used as a removal method with high anisotropy. However, the present invention is not limited to this, and the method is anisotropic so that the wiring metal 3X formed on the side surface of the pixel isolation trench 2 remains. For example, dry etching such as reactive ion etching (RIE) can be used.

Thus, in this embodiment, when a highly anisotropic removal method such as ion milling is used, the wiring metal 3X that remains without being removed, that is, the side surface of the pixel isolation trench 2 (side surface of the pixel 1). The wiring metal 3X formed in (1) is used as the metal wiring 3 (3A).
That is, in the present embodiment, the metal wiring 3 is formed in the pixel isolation trench 2 excluding the intersecting portion 4 without forming the resist pattern (mask) 20, and the removal method having high anisotropy such as ion milling is vertical. By utilizing the property that the wiring metal 3X formed on the surface or a surface close thereto is not removed, the wiring metal 3X that remains without being removed on the side surface of the pixel isolation trench 2 (side surface of the pixel 1) is removed. The metal wiring 3 (3A) is used.

  For this reason, it is not necessary to increase the width of the pixel separation groove as in the case where metal wiring is formed at the bottom of the pixel separation groove (see FIGS. 9 and 10), and therefore the effective pixel area is reduced and the sensitivity is improved. There is no decline. On the contrary, since the metal wiring 3 (3A) is formed on the side surface of the pixel 1, this functions as a reflecting plate and can prevent incident infrared rays from escaping to the outside, which contributes to improvement in sensitivity. .

  However, in this case, since the metal wiring 3A is formed only on the peripheral portion of the pixel (side surface of the pixel 1), it is necessary to connect the metal wiring 3A formed on the side surface of each pixel 1 to each other. Therefore, as described above, the resist pattern 20 is formed on the bottom surface of the intersecting portion 4 where the plurality of pixel separation grooves 2 intersect, and the metal wiring 3B is formed on the bottom surface of the intersecting portion 4, so that the side surface of each pixel 1 is formed. The formed metal wiring 3A is connected to each other. Since the intersection 4 has a relatively large opening, patterning is easy.

Hereinafter, the reason why the metal wiring 3 is formed by such a method will be described.
First, when forming a metal wiring on the surface side, it is conceivable to form a metal wiring on the bottom surface of the pixel separation groove (see FIG. 9).
However, when the patterning is actually performed on the bottom surface of the pixel separation groove, the width of the pixel separation groove needs to be considerably widened, so that the area of each pixel is reduced, and as a result, the sensitivity is lowered, so that it is practically used. Not right.

Further, in order to form the surface wiring on the bottom surface of the pixel separation groove, a resist is formed so as to cover the bottom surface of the pixel separation groove (see FIG. 10), and when unnecessary wiring metal is removed, scraped metal residue is formed. After adhering to the surface of the resist and removing the resist, burrs remain on the surface wiring formed on the bottom surface of the pixel separation groove (see FIG. 11).
If such burrs remain, it may be adversely affected by a process such as peeling off in a later manufacturing process, which is not preferable. Normally, burrs generated along the resist pattern for forming the surface wiring on the bottom surface of the pixel isolation groove are linear and long, so if they peel off and reattach, the cause of defects such as short circuit between pixels, for example It can be.

In addition, as shown in FIGS. 5A and 5A, it is also conceivable to form metal wiring on the entire surface (side surface and bottom surface) in the pixel isolation trench.
In this case, as shown in FIGS. 5B and 5B, the resist pattern is formed with a width slightly larger than the width of the pixel separation groove. This is because the resist cannot be developed successfully unless a resist pattern is formed so as to avoid a region where the thickness of the resist in the pixel separation groove is very large. For this reason, the effective effective pixel area is reduced, the signal is lowered, and the sensitivity is lowered. Also in this case, it is necessary to form a resist pattern along the pixel separation groove as in the case where the metal wiring is formed on the bottom surface of the pixel separation groove (see FIG. 9), and the resist pattern is also large. For this reason, burrs may be generated and peeled off in a later manufacturing process, which may adversely affect the process. In addition, straight and long burrs may occur, which may cause defects such as a short circuit between pixels.

Further, as a countermeasure against burrs during ion milling, it is conceivable to form the resist in a round shape by baking as shown in FIGS.
This is because the metal residue scattered by the ion milling and adhering to the resist surface is removed by the subsequent ion milling.
That is, as shown in FIG. 6A, when the end face of the resist is vertical, the metal residue adhering to the vertical end face is not scraped by ion milling and remains until the end, resulting in burrs. . For this reason, as shown in FIG. 6B, the resist is baked at a high temperature to round the shape so that the end face does not become perpendicular to the wafer. It is conceivable that burrs are less likely to remain by scraping by ion milling.

However, since the width of the resist pattern is somewhat widened through the resist baking process, the effective effective pixel area is reduced, the signal is lowered, and the sensitivity is lowered, which is not preferable. Moreover, even if resist molding is performed by baking, burrs are not always eliminated.
Therefore, in the present embodiment, as described above, the pixel separation groove 2 is not formed with a resist pattern (mask) 20 except for the intersection 4, and a highly anisotropic removal method such as ion milling is used. In this case, the wiring metal 3X that remains without being removed on the side surface of the pixel separation groove 2 (the side surface of the pixel 1; the surface perpendicular to the substrate) is used as the metal wiring 3 (3A). Then, the resist pattern 20 is formed only on the bottom surface of the intersecting portion 4 where the plurality of pixel separation grooves 2 intersect, and the metal wiring 3B is formed on the bottom surface of the intersecting portion 4, thereby forming the metal formed on the side surface of each pixel 1 The wiring 3A is connected to each other.

  Thus, since no resist is used to form the metal wiring 3A on the side surface of the pixel separation groove 2, no burrs are generated at this portion. Further, since the intersecting portion 4 where the plurality of pixel separating grooves 2 intersect is relatively wide, the scraped metal residue is easy to escape (see FIG. 11), and burrs are hardly generated. However, a region from the bottom surface of the intersection 4 where the plurality of pixel separation grooves 2 intersect, the side surface of the pixel separation groove 2 (side surface of the pixel 1) to the second contact hole 8 where the surface of the upper contact layer 15 is exposed, and The resist is used to form the metal wirings 3B to 3D in the region from the bump formation region to the second contact hole 7 (contact groove 5) where the surface of the common contact layer 13 is exposed. There are burrs. However, burrs that cause adverse effects on the process, such as peeling off in a later manufacturing process, do not occur. In addition, since the resist pattern 20 formed in these regions is small and no long burrs are generated in a straight line unlike the burrs generated along the resist pattern formed along the pixel separation groove, the burrs are not generated. Even if it peels off, it does not cause a short circuit between pixels.

  By the way, after forming the metal wiring 3 (3A to 3D) as described above and removing the resist pattern 20, as shown in FIGS. 4A and 4A, the passivation is further performed on the surface (entire surface). A film 30 is formed, and as shown in FIGS. 4B and 4B, for example, a contact hole 31 for bump connection is formed in the center of the pixel. Then, as shown in FIGS. 4C and 4C, metal bumps 9 (here, In bumps) 9 are formed by vapor deposition, for example. Thereby, a quantum well type infrared image sensor element (QWIP element) is completed.

Therefore, according to the image sensor and the manufacturing method thereof according to the present embodiment, the surface metal wiring 3 can be easily formed while preventing burrs from occurring as much as possible without degrading characteristics such as heat cycle characteristics and sensitivity. Thus, there is an advantage that the number of bumps can be reduced and high resolution can be realized by increasing the number of pixels.
In the above-described embodiment, the metal wiring (connecting metal wiring) 3B formed on the bottom surface of the intersecting portion 4 where the plurality of pixel separation grooves 2 intersect is partially formed on the bottom surface of the intersecting portion 4. However, the present invention is not limited to this. For example, the metal wiring 3B is formed on the entire bottom surface of the intersection 4 so that the metal wirings 3A formed on the side surfaces of the four adjacent pixels 1 are connected to each other. You may make it form (refer FIG. 1).

  Further, in the above-described embodiment, the connection metal wiring 3B is formed at the intersecting portion 4. However, the present invention is not limited to this, and it is possible to apply a bias voltage to the upper contact layer 15 of all the pixels 1 so that the bias voltage can be applied. What is necessary is just to form so that the pixel 1 may be connected. For example, the connection metal wiring 3B may be formed on a part of the bottom surface of the pixel separation groove. In this case, the metal wiring 3 is formed only on a part of the side surface and the bottom surface of the pixel separation groove 2 on the surface of the pixel separation groove 2. In particular, the connection metal wiring 3B is preferably formed on a part of the bottom surface of the pixel separation groove 2 so as to connect adjacent pixels 1 among the plurality of pixels 1 to each other. In this case, the metal wiring 3 is formed on the side surface of the pixel separation groove 2 on the surface of the pixel separation groove 2 and on the bottom surface of the pixel separation groove 2 so as to connect adjacent pixels 1 among the plurality of pixels 1. It will be formed only in part.

As described above, when the position and shape of the connection metal wiring 3B are changed with respect to those of the above-described embodiment, the position and shape of the resist pattern (mask) may be changed accordingly.
For example, when the metal wiring 3B is formed on the entire bottom surface of the intersecting portion 4 (see FIG. 1), the wiring metal 3X formed on the side surface of the pixel isolation trench 2 that constitutes each side surface of the four adjacent pixels 1 is used. A resist pattern may be formed on the entire bottom surface of the intersecting portion 4 so as to be connected to each other.

For example, when the metal wiring 3 is formed only on a part of the side surface and the bottom surface of the pixel separation groove 2 on the surface of the pixel separation groove 2, a mask is formed on the bottom surface of the pixel separation groove 2 in the pixel separation groove 2. What is necessary is just to form so that only a part of formed wiring metal 3X may be covered.
Further, for example, the metal wiring 3 is arranged on the surface of the pixel separation groove 2 on the side surface of the pixel separation groove 2 and the bottom surface of the pixel separation groove 2 so as to connect adjacent pixels 1 among the plurality of pixels 1. In the pixel separation groove 2, the wiring metal 3 </ b> X formed on the side surface of the pixel separation groove 2 that forms the side surface of the adjacent pixel 1 in the pixel separation groove 2 is connected to each other. As described above, it may be formed so as to cover only a part of the wiring metal 3X formed on the bottom surface of the pixel separation groove 2.

  In the above-described embodiment, the case where the present invention is applied to a quantum well infrared image sensor in which each pixel is configured by two-wavelength QWIP is described as an example. However, the present invention is not limited to this. The present invention is an image sensor (array chip) in which a plurality of pixels (detecting elements) are separated two-dimensionally by separating grooves, and all the pixels are connected by metal wiring formed on the surface side. Can be widely applied to what is needed.

For example, the present invention can also be applied to an infrared image sensor using quantum dots or quantum wires for the absorption layer. For example, the present invention can be applied to an image sensor used for detection of visible light. For example, although an MQW layer is used as the absorption layer, other structures or semiconductor layers can be used.
In addition, the present invention is not limited to the configuration described in the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram which shows the outline of the image sensor concerning one Embodiment of this invention, Comprising: (A) is the top view, (B) is sectional drawing which follows the AA line of (A). It is a schematic diagram which shows the structure of the image sensor concerning one Embodiment of this invention, Comprising: (A) is sectional drawing which follows the BB line of (B), (B) is the top view. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram for demonstrating the manufacturing method of the image sensor concerning one Embodiment of this invention, Comprising: (A)-(D) is the top view, (a)-(d) is (A)-(D It is sectional drawing which follows the XX line. It is a schematic diagram for demonstrating the manufacturing method of the image sensor concerning one Embodiment of this invention, Comprising: (A)-(C) is the top view, (a)-(c) is (A)-(C It is sectional drawing which follows the XX line. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram for demonstrating the method considered in the creation process of the manufacturing method of the image sensor concerning one Embodiment of this invention, Comprising: (A), (B) is the top view, (a), (b) ) Is a cross-sectional view taken along line XX of (A) and (B). (A), (B) is typical sectional drawing for demonstrating the method considered in the creation process of the manufacturing method of the image sensor concerning one Embodiment of this invention. It is typical sectional drawing which shows the structure of the conventional infrared image sensor. It is a typical top view for explaining the method considered in the creation process of the manufacturing method of the image sensor concerning one embodiment of the present invention. It is a typical top view for explaining the method considered in the creation process of the manufacturing method of the image sensor concerning one embodiment of the present invention. It is typical sectional drawing for demonstrating the method considered in the creation process of the manufacturing method of the image sensor concerning one Embodiment of this invention. It is a drawing substitute photograph for demonstrating the subject of this invention.

Explanation of symbols

1 pixel 2 pixel separation groove 3, 3A-3D metal wiring (surface wiring)
3X wiring metal 4 intersection 5 contact groove 6 passivation film (insulating film)
7 First contact hole 8 Second contact hole 9 Bump 10 Semiconductor substrate 11 Lower contact layer 12 First MQW layer (absorption layer)
13 Common contact layer 14 Second MQW layer (absorption layer)
15 Upper contact layer 20 Mask (resist pattern)
30 Passivation film 31 Contact hole for bump connection

Claims (6)

A plurality of pixels arranged two-dimensionally;
A plurality of pixel separation grooves for separating the plurality of pixels;
A metal wiring formed on the surface side so as to connect all of the plurality of pixels,
The image sensor according to claim 1, wherein the metal wiring is formed only on a part of a side surface and a bottom surface of the pixel separation groove on a surface of the pixel separation groove.   The image sensor according to claim 1, wherein the metal wiring formed on a part of the bottom surface is formed so as to connect adjacent pixels among the plurality of pixels.   The image sensor according to claim 1, wherein a part of the bottom surface is an intersection where the plurality of pixel separation grooves intersect.   The pixel has a structure in which a lower contact layer, a first absorption layer that absorbs light in one wavelength band, a common contact layer, a second absorption layer that absorbs light in another wavelength band, and an upper contact layer are sequentially stacked. The image sensor according to claim 1, wherein the image sensor is an image sensor. A bump formed on the surface side of the plurality of pixels, one for each pixel;
Bump connection metal wiring for connecting the bump and the common contact layer,
The metal wiring connects a portion formed on the side surface of the pixel isolation trench, a portion formed on the bottom surface of the intersection, and a portion formed on the side surface of the pixel isolation trench. The image sensor according to claim 4, further comprising a portion. A semiconductor laminated structure is formed on the substrate,
Forming a plurality of pixel separation grooves in the semiconductor stacked structure so that a plurality of pixels arranged two-dimensionally are formed;
Forming wiring metal on the surface,
In the pixel separation groove, a mask is formed so as to cover only a part of the wiring metal formed on the bottom surface of the pixel separation groove,
A method of manufacturing an image sensor, comprising: forming a metal wiring by removing the wiring metal by anisotropic etching so that the wiring metal formed on a side surface of the pixel separation groove remains.