JP2009163338A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately control a waiting time when making a main operation part of a CPU (central processing unit) or the like wait execution of processing by an instruction. <P>SOLUTION: This information processor has: the main operation part performing the processing according to an instruction read from a memory; and an expansion operation part performing processing according to a prescribed instruction of the instructions read from the memory. The expansion operation part has a signal generation circuit counting a pulse of a clock signal, and outputting a signal showing that it has to wait when the instruction read from the memory is the wait instruction making the main operation part wait until a count corresponding to a wait count number designated in the wait instruction is completed. The main operation part stops the processing while the signal showing that it has to wait is output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus having a main calculation unit such as a CPU and an extended calculation unit that executes a predetermined calculation.

  In order to improve basic performance, an example of an information processing apparatus having an extended arithmetic unit that executes a predetermined calculation in addition to a CPU that mainly performs processing is disclosed in Patent Document 1. When the received instruction is executable, the extended arithmetic unit receives data related to the operation from the CPU, executes the operation, and outputs the result to the CPU. By having the extended arithmetic unit, a special instruction that cannot be executed by the CPU can be executed, and the code size of the program can be made smaller than when the extended arithmetic unit is not provided. Thereby, the capacity of the instruction memory can be reduced. Further, since the CPU can execute another instruction while the extended arithmetic unit is executing the calculation, the basic performance of the information processing apparatus is improved.

By using the extended arithmetic unit having a configuration according to the application, it becomes easy to improve the performance as the information processing apparatus without changing the physical configuration of the CPU. Further, since only the extended arithmetic unit needs to be modified depending on the application, there is an advantage that the time required for development can be shortened as compared with the case where a dedicated information processing apparatus is created from scratch.
JP-A-8-305568

  Even in such an information processing apparatus, when the CPU processing is to be waited for a certain period, the CPU is caused to execute a NOP instruction or a loop instruction. However, there is a problem that an error occurs between the scheduled waiting time and the actual waiting time due to competition in the bus at the time of instruction fetch by the CPU, and the program needs to be corrected.

  Also, since interrupts and control of external circuits cannot be performed directly from the CPU after a certain period of time has elapsed, it has been necessary to operate an external timer and control it according to its output signal. That is, it is necessary to operate in a complicated procedure, and there is a problem that the circuit area is increased by adding a function therefor.

  It is an object of the present invention to accurately control the waiting time when a main processing unit such as a CPU waits for processing according to an instruction.

  In order to solve the above problems, the means taken by the present invention includes an information processing device as a main operation unit that performs processing according to an instruction read from a memory, and a predetermined instruction among the instructions read from the memory. And an extended arithmetic unit that performs processing according to the above. The extended arithmetic unit counts pulses of a clock signal, and when the instruction read from the memory is a standby instruction that causes the main arithmetic unit to wait, a signal indicating that it should wait It has a signal generation circuit that outputs until the count corresponding to the standby count number specified in the standby instruction is completed. The main arithmetic unit stops the process while the signal indicating that the standby should be performed is output.

  According to this, the main arithmetic unit stops the processing by the signal generated by the extended arithmetic unit based on the standby count number specified in the predetermined instruction. Since it is not necessary to cause the main arithmetic unit to execute an instruction in order to wait for processing, there is no error between the predicted waiting time and the actual waiting time caused by using the external bus at the time of instruction fetch. In addition, since such processing is realized by one instruction, the code size of the program can be reduced, and the creation of the program can be facilitated.

  According to the present invention, when the CPU or the like is caused to wait for processing by an instruction, it is possible to accurately control the waiting time without being affected by the state of the bus. Since it is sufficient to use one instruction and specify the number of cycles of the clock signal, it is easy to create a program.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to the first embodiment of the present invention. The information processing apparatus 100 in FIG. 1 includes a central processing unit (CPU) 110 as a main arithmetic unit, an extended arithmetic unit 120 as an extended arithmetic unit, and a read-only memory (ROM) 130. The CPU 110 includes a CPU instruction decoder 111, a CPU control circuit 112, a general-purpose register 113, and an arithmetic unit 114. The extended arithmetic unit 120 includes an extended instruction decoder 121, an extended instruction control circuit 122, arithmetic units 123 and 124, a control signal generation circuit 125 as a signal generation circuit, a selector 126, and an OR circuit 127. ing.

  The CPU 110 and the extended arithmetic unit 120 operate in synchronization with the clock signal CLK. The CPU 110 has a function of executing various information processing, and outputs an instruction address to the ROM 130. The ROM 130 supplies an instruction corresponding to the received instruction address to the instruction decoder 111 and the extended instruction decoder 121 via the instruction bus 141.

  The CPU instruction decoder 111 decodes the instruction supplied from the instruction bus 141 and outputs a decoding result. The CPU control circuit 112 generates various control signals PCN based on the content of the decode signal CDC, which is the decoding result of the CPU instruction decoder 111, and the control signal ECP supplied from the extension arithmetic unit 120, and each circuit of the CPU 110 Output to.

  The general-purpose register 113 includes registers D0, D1, D2, and D3 that store data. The arithmetic unit 114 performs an operation on values input from the data input bus 143 and the data input bus 144 in accordance with a control signal supplied from the CPU control circuit 112 and outputs an operation processing result to the data output bus 145.

  The extended arithmetic unit 120 has a function of executing various information processing according to the extended instruction when the instruction supplied from the ROM 130 is an extended instruction. The extension instruction decoder 121 decodes the extension instruction supplied from the instruction bus 141 and outputs a decoding result. The extension instruction control circuit 122 generates and outputs the control signals IC1, IC2, IC3, and ICS according to the content of the decode signal EDC that is the decoding result of the extension instruction decoder 121.

  The arithmetic unit 123 performs arithmetic processing on the values input from the data input bus 143 and the data input bus 144 according to the control signal IC1, and outputs the obtained arithmetic processing result PO1 and the control signal EC1. The arithmetic unit 124 performs arithmetic processing on the values input from the data input bus 143 and the data input bus 144 according to the control signal IC2, and outputs the obtained arithmetic processing result PO2 and the control signal EC2. The control signal generation circuit 125 performs arithmetic processing based on the control signal IC3 and the value input from the data input bus 143, and outputs the control signal EC3.

  The selector 126 selects one of the arithmetic processing result PO1 of the arithmetic unit 123 and the arithmetic processing result PO2 of the arithmetic unit 124 in accordance with the control signal ICS, and outputs the selected value to the data output bus 145. The logical sum circuit 127 calculates the logical sum of the control signals EC1, EC2, and EC3 and outputs the logical sum as the control signal ECP.

  FIG. 2 is a block diagram showing a configuration example of the control signal generation circuit 125 of FIG. The control signal generation circuit 125 includes a control circuit 62, a comparison value holding circuit 64, a counter circuit 66, and a comparator 68.

  The control circuit 62 includes a control signal CH3 for controlling the comparison value holding circuit 64 and a counter circuit 66 in accordance with the control signal IC3, the value of the data input bus 143, and the coincidence signal CMR supplied from the comparator 68. A control signal CC for control and a control signal EC3 are generated and output. The comparison value holding circuit 64 outputs the input value from the data input bus 143 as the output data CMV, holds the input value from the data input bus 143, and outputs the held value as the output data CMV according to the control signal CH. Is output.

  The counter circuit 66 counts up and resets the pulses of the clock signal CLK and outputs the count value as output data CNT in accordance with the control signal CC. The comparator 68 compares the output data CMV of the comparison value holding circuit 64 with the output data CNT of the counter circuit 66, and outputs the comparison result to the control circuit 62 as a coincidence signal CMR.

  FIG. 3 is a timing chart showing an example of the operation of the information processing apparatus 100 of FIG. The wait command (standby command) is an extended command that waits for the processing of the CPU 110 for the time specified in the command, and the wait time is represented by, for example, a wait count number. The wait instruction is described, for example, as “WAIT Dm” (Dm indicates one of the registers D0 to D3). In this case, the processing of the CPU 110 is waited until the counter circuit 66 counts up by the value (standby count number) stored in the register Dm.

  In FIG. 3, the IF stage indicates a stage where a process for reading an instruction from the ROM 130 is being performed. The DEC stage refers to a stage in which the CPU instruction decoder 111 and the extended instruction decoder 121 decode the instruction read from the ROM 130 and output a control signal. The EX stage indicates a stage where the CPU 110 and the extended arithmetic unit 120 are performing processing based on a control signal obtained as a result of decoding. “W” in each stage indicates that a wait instruction is being processed, and “N” indicates that an instruction subsequent to the wait instruction is being processed.

  The CPU 110 reads a wait instruction from the ROM 130 via the instruction bus 141. From time T1, the CPU instruction decoder 111 decodes the wait instruction and outputs the obtained decode signal CDC. The CPU control circuit 112 generates various control signals PCN based on the decode signal CDC and outputs them to each circuit of the CPU 110.

  At substantially the same timing as the CPU instruction decoder 111, the extension instruction decoder 121 of the extension arithmetic unit 120 decodes the wait instruction and outputs the obtained decode signal EDC. The extended instruction control circuit 122 determines from the decode signal EDC that the wait instruction has been executed, and outputs “1” as the control signal IC3 between times T1 and T2. The extended instruction control circuit 122 outputs “0” as the control signals IC1, IC2, ICS so that instructions other than the wait instruction are not executed.

  From time T 2, CPU 110 reads a value from register Dm of general-purpose register 113 specified by the wait instruction in accordance with various control signals PCN obtained as a result of decoding the wait instruction, and outputs the value to data input bus 143. As an example, it is assumed that the value stored in the register Dm is 3. Since the control signal IC3 is “1”, the control circuit 62 in the control signal generation circuit 125 starts the wait command operation and outputs the control signals CH and CC.

  In accordance with the control signal CH, the comparison value holding circuit 64 holds the value of the data input bus 143 and outputs the value “3” as the output data CMV. In accordance with the control signal CC, the counter circuit 66 outputs “0” as the output data CNT and increments the count value by “1”. The comparator 68 compares the values of the output data CMV and the output data CNT, and outputs “0” as the match signal CMR because they do not match. Since the coincidence signal CMR is “0”, the control circuit 62 sets the control signal EC3 to “1” and outputs it as a signal indicating that it should wait.

  The OR circuit 127 outputs “1” as the control signal ECP. Since the control signal ECP is “1”, the CPU control circuit 112 outputs various control signals PCN and stops the pipeline operation of the CPU 110 from time T3.

  After time T3, the control signal generation circuit 125 continues to operate, counts up the counter circuit 66 every cycle, compares the output data CMV of the comparison value holding circuit 64 and the output data CNT of the counter circuit 66, and the values match. The operation continues until At time T5, the output data CMV of the comparison value holding circuit 64 and the output data CNT of the counter circuit 66 match, so the comparator 68 outputs “1” as the match signal CMR.

  Since the coincidence signal CMR is “1”, the control circuit 62 determines that the wait instruction operation is finished, and outputs “0” as the control signal EC3. Then, the OR circuit 127 outputs “0” as the control signal ECP. Since the control signal ECP is “0”, the CPU control circuit 112 outputs various control signals PCN and restarts the pipeline operation of the CPU 110 from time T6.

  As shown in FIG. 3, if the value of the register Dm specified in the wait instruction is set to 3, the CPU processing can be made to wait for a period of 4 cycles. The set value of the number of cycles in the register Dm may be “waiting time × operation frequency−1” and can be easily obtained.

  As described above, in the information processing apparatus 100, when it is necessary to wait for a certain period of time for CPU processing, a value may be set in the register Dm and a wait instruction may be executed. Since the extended arithmetic unit 120 performs the counting, the time for which the CPU or the like waits for processing can be accurately controlled without being affected by the state of the bus.

  In the first embodiment, it has been described that the count circuit 66 counts up. However, the function of the control signal generation circuit 125 can also be realized by performing countdown. Further, the logic of the signal may be opposite to the above.

  Although the case where the value stored in the register Dm described in the wait instruction is used as the wait count number has been described, the value may be directly described in the wait instruction and the value may be used as the wait count number.

  Further, a plurality of cycle number setting registers are provided in the extended arithmetic unit 120, one cycle number setting register is selected according to the value described as Dm in the wait instruction, and the value of the register is set as the wait count number. You may make it use.

(Second Embodiment)
According to the apparatus shown in FIG. 1, the control signal generation circuit 125 is necessary to make the CPU wait for processing, and the circuit scale increases. Therefore, in this embodiment, an increase in circuit scale is suppressed by using resources of an arithmetic unit that does not operate during execution of a wait instruction in the extended arithmetic unit 120.

  FIG. 4 is a block diagram showing the configuration of the information processing apparatus according to the second embodiment of the present invention. The information processing apparatus 200 in FIG. 4 is the same as the information processing apparatus 100 in FIG. 1 except that an extended arithmetic unit 220 is provided instead of the extended arithmetic unit 120. The extended arithmetic unit 220 is the same as the extended arithmetic unit 120 except that it includes an arithmetic unit 224 instead of the arithmetic unit 124 and does not include the control signal generation circuit 125. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 5 is a block diagram illustrating a configuration example of the arithmetic unit 224 of FIG. The arithmetic unit 224 includes a control circuit 262, a multiplier 263, selectors 264, 267, 269, registers 265, 266, and an adder 268. The multiplier 263, the selectors 264, 267, the registers 265, 266, and the adder 268 constitute an arithmetic circuit that performs a product-sum operation.

  The arithmetic unit 224 is a circuit that performs a product-sum operation. The arithmetic unit 224 performs multiplication or product-sum operation between the value input from the data input bus 143 and the value input from the data input bus 144 in accordance with the control signal IC2 supplied from the extension instruction control circuit 122. The obtained result is output as the operation processing result PO2, and the control signal EC2 is output for pipeline control. Further, the arithmetic unit 224 performs arithmetic processing based on the value input from the data input bus 143 according to the control signal IC3, performs processing similar to the control signal generation circuit 125 of FIG. Output as EC3.

  The multiplication instruction is an extension instruction for multiplication, and is described as, for example, “MUL Dm, Dn” (Dm and Dn indicate any of registers D0 to D3). The product-sum instruction is an extension instruction for product-sum, and is described as, for example, “MAC Dm, Dn” (Dm and Dn indicate any of registers D0 to D3). The product-sum result acquisition instruction is an extension instruction for acquiring the product-sum result, and is described as, for example, “GETMAC Dn” (Dm and Dn indicate any of registers D0 to D3).

  An operation of the information processing apparatus 200 when a multiplication instruction is executed will be described. As in the case of the wait instruction, the CPU 110 reads the multiplication instruction from the ROM 130, performs decoding, and outputs the obtained decode signal CDC. The CPU control circuit 112 generates various control signals PCN based on the decode signal CDC and outputs them to each circuit of the CPU 110.

  At substantially the same timing as the CPU instruction decoder 111, the extension instruction decoder 121 of the extension arithmetic unit 220 decodes the multiplication instruction and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the multiplication instruction has been executed, and outputs control signals IC2 and ICS. The extended instruction control circuit 122 outputs control signals IC1 and IC3 so that instructions other than multiplication instructions are not executed.

  The CPU 110 reads a value from the register Dm of the general-purpose register 113 and outputs it to the data input bus 143 according to various control signals PCN obtained as a result of decoding the multiplication instruction, and reads a value from the register Dn of the general-purpose register 113 to input data. Output to bus 144. The multiplier 263 multiplies the value of the data input bus 143 and the value of the data input bus 144 and outputs the multiplication result.

  The control circuit 262 of the arithmetic unit 224 starts multiplication processing according to the control signal IC2, and outputs a control signal SL3. The selector 269 selects the output of the multiplier 263 in accordance with the control signal SL3 and outputs it as the operation processing result PO2. The selector 126 selects the calculation processing result PO2 of the calculator 224 in accordance with the control signal ICS, and outputs the selected value to the data output bus 145. The CPU 110 stores the value of the data output bus 145 in the register Dn of the general-purpose register 113.

  Next, the operation of the information processing apparatus 200 when the product-sum instruction and the product-sum result acquisition instruction are executed will be described. In the case of the multiply-add instruction processing, as in the case of the multiply instruction, the instruction is read from the ROM 130 and decoded, and various control signals PCN are output.

  At substantially the same timing as the CPU instruction decoder 111, the extension instruction decoder 121 decodes the product-sum instruction and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the multiply-accumulate instruction has been executed, and outputs a control signal IC2. The extended instruction control circuit 122 outputs control signals IC1, IC3, and ICS so that instructions other than the product-sum instruction are not executed. The CPU 110 reads the value from the register Dm of the general-purpose register 113 and outputs the value to the data input bus 143 in accordance with various control signals PCN obtained as a result of decoding the multiply-accumulate instruction, and reads the value from the register Dn of the general-purpose register 113 Output to the input bus 144.

  The control circuit 262 starts product-sum processing according to the control signal IC2, generates and outputs control signals SL1, SL2, SL3, SR1, SR2, and EC2. The selector 264 selects and outputs the output of the multiplier 263 according to the control signal SL1. Register 265 stores and outputs the value output from selector 264 in accordance with control signal SR1. Register 266 outputs the held value in accordance with control signal SR2. The selector 267 selects and outputs the value output from the register 266 in accordance with the control signal SL2.

  In the next cycle, the adder 268 adds the value output from the register 265 and the value output from the selector 267, and outputs the obtained result. Register 266 stores the value output from adder 268 in accordance with control signal SR2.

  After execution of the product-sum instruction, the product-sum result acquisition instruction is executed. Also in the case of processing the product-sum result acquisition instruction, the instruction is read out from the ROM 130 and decoded, as in the case of the multiplication instruction, and various control signals PCN are output.

  At substantially the same timing as the CPU instruction decoder 111, the extension instruction decoder 121 decodes the product-sum result acquisition instruction and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the product-sum result acquisition instruction has been executed, and outputs control signals IC2 and ICS. Further, the extended instruction control circuit 122 outputs control signals IC1 and IC3 so that instructions other than the product-sum result acquisition instruction are not executed.

  The control circuit 262 starts the product-sum result acquisition process according to the control signal IC2, and generates and outputs the control signal SL3. The selector 269 selects and outputs the value output from the register 266 in accordance with the control signal SL3. The selector 126 selects the calculation processing result PO2 output from the calculator 224 according to the control signal ICS, and outputs it to the data output bus 145. The CPU 110 stores the value of the data output bus 145 in the register Dn of the general-purpose register 113.

  Next, the operation of the information processing apparatus 200 when a wait instruction is executed will be described. Here, only the operation of the arithmetic unit 224 will be described. The operation of other components is the same as that of the first embodiment. It is assumed that the value read from the register Dm of the general-purpose register 113 is output to the data input bus 143. The control circuit 262 starts wait processing according to the control signal IC3, and generates and outputs the control signals SL1, SR1, SL2, and EC3.

  The selector 264 selects and outputs the value of the data input bus 143 according to the control signal SL1. Register 265 stores and outputs the value output from selector 264 in accordance with control signal SR1. The selector 267 selects and outputs “−1” in accordance with the control signal SL2. The adder 268 adds the value output from the register 265 and the value output from the selector 267, outputs the obtained result to the selector 264 and the register 266, and outputs a carry-out to the control circuit 262.

  While the control signal SL1 is “1”, a wait instruction is executed. The control circuit 262 outputs “1” as the control signal EC3 while the carry-out of the adder 268 is “1”. At this time, “1” is output as the control signal ECP. Since the control signal ECP is “1”, the CPU control circuit 112 stops the pipeline operation of the CPU 110 by various control signals PCN.

  During the execution of the wait instruction, the selector 264 selects and outputs the value output from the adder 268 according to the control signal SL1, and the register 265 holds the value output from the selector 264 according to the control signal SR1. Output. The adder 268 repeats the addition of the value output from the register 265 and the value output from the selector 267 as described above for each cycle.

  When the carry-out of the adder 268 becomes “0”, the control circuit 262 determines that the wait process should be terminated, and outputs “0” as the control signal EC3. Since the control signal ECP becomes “0” by the control signal EC3, the CPU control circuit 112 restarts the pipeline operation of the CPU 110 by various control signals 146.

(Third embodiment)
According to the apparatus of FIG. 1, since the pipeline is stopped, the CPU 110 cannot accept an external interrupt when it is necessary to cancel the standby state. Therefore, in the present embodiment, an interrupt signal is also given to the control signal generation circuit 125 of the extended arithmetic unit 120 so that an interrupt can be performed even while a wait instruction is being executed.

  FIG. 6 is a block diagram showing the configuration of the information processing apparatus according to the third embodiment of the present invention. The information processing apparatus 200 in FIG. 6 is the same as the information processing apparatus 100 in FIG. 1 except that an extended arithmetic unit 320 is provided instead of the extended arithmetic unit 120. The extended arithmetic unit 320 is the same as the extended arithmetic unit 120 except that it has a control signal generation circuit 325 instead of the control signal generation circuit 125. The interrupt control circuit 302 interrupts the CPU 110 when the control signal INR for interrupt supplied from outside the information processing apparatus 200 becomes “0”. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 7 is a block diagram illustrating a configuration example of the control signal generation circuit 325 of FIG. The control signal generation circuit 325 is the same as the control signal generation circuit 125 in FIG. 2 except that the control signal generation circuit 325 further includes an OR circuit 369.

  FIG. 8 is a timing chart showing an example of the operation of the information processing apparatus 300 of FIG. As an example, the control signal INR is assumed to be negative logic. In this case, when the control signal INR becomes “0”, the interrupt process is started. As in the first embodiment, the case where the wait instruction “WAIT Dm” is executed will be described only with respect to differences from the case of FIG.

  Assume that the value stored in the register Dm is 5, and the control signal INR is “1”. The operation up to time T4 is the same as in FIG. However, the logical sum circuit 369 calculates the logical sum of the coincidence signal CMR output from the comparator 68 and the result of inverting the control signal INR, and uses the result as the signal CIN instead of the coincidence signal CMR. To give.

  Assume that an interrupt request occurs at times T4 to T5. At this time, the control signal INR becomes “0”. The interrupt control circuit 302 interrupts the CPU 110. However, the CPU 110 does not accept an interrupt because the wait instruction is being executed and the pipeline is stopped.

  The OR circuit 369 outputs “1” as the signal CIN when the control signal INR becomes “0”. When the signal CIN becomes “1”, the control circuit 62 determines the end of the wait instruction operation as in the case where the comparator 68 determines that they match in the first embodiment, and sets “0” as the control signal EC3. Output. Then, the OR circuit 127 outputs “0” as the control signal ECP.

  Since the control signal ECP is “0”, the CPU control circuit 112 outputs various control signals PCN and restarts the pipeline operation of the CPU 110 from time T5. Then, since an interrupt is being performed from the interrupt control circuit 302, the CPU 110 starts interrupt processing.

  As described above, according to the information processing apparatus of FIG. 6, even when a wait instruction is being executed, the CPU 110 can execute an interrupt process.

  Although the interrupt signal has been described as being negative logic, it may be positive logic. In this case, the configuration of the OR circuit 369 may be changed. If there are a plurality of interrupt signals, the logical sum of these signals may be supplied to the control signal generation circuit 325.

(Fourth embodiment)
According to the apparatus of FIG. 1, the CPU 110 consumes power while the CPU 110 is on standby. Therefore, in the present embodiment, the control signal ECP output from the extended arithmetic unit 120 is used to stop the supply of the clock signal to the CPU 110 during standby, thereby suppressing unnecessary power consumption.

  FIG. 9 is a block diagram showing the configuration of the information processing apparatus according to the fourth embodiment of the present invention. The information processing apparatus 400 in FIG. 9 is the same as the information processing apparatus 100 in FIG. 1 except that the information processing apparatus 400 further includes a clock control circuit 480. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 10 is a block diagram illustrating a configuration example of the clock control circuit 480 of FIG. The clock control circuit 480 includes an inverter 482, a flip-flop (FF) 484, and an AND circuit 486.

  The inverter 482 outputs the clock signal CLK supplied from the outside of the information processing apparatus 400 with its logic inverted. The FF 484 holds the value of the control signal ECP supplied from the extended arithmetic unit 120 in synchronization with the output of the inverter 482, and outputs the value as the control signal FEC. The logical product circuit 486 obtains a logical product of a value obtained by inverting the control signal FEC and the clock signal CLK, and outputs the logical product to the CPU 110 as the clock signal CKP. The CPU 110 operates according to the clock signal CKP.

  FIG. 11 is a timing chart showing an example of the operation of the information processing apparatus 400 of FIG. When the wait instruction is not being executed, since the control signal ECP is “0”, the clock signal CLK and the clock signal CKP have substantially the same waveform. As in the first embodiment, the case where the wait instruction “WAIT Dm” is executed will be described only with respect to differences from the case of FIG. It is assumed that the value stored in the register Dm is 5. The operation up to time T2 is the same as in the case of FIG.

  Since the control signal ECP becomes “1” at time T2, the FF 484 sets the control signal FEC to “1” at times T2 to T3. Since the control signal FEC is “1”, the AND circuit 486 outputs “0” as the clock signal CKP. This state continues until before time T8. Since the clock signal CKP supplied from the clock control circuit 480 remains “0”, the CPU 110 stops the entire operation.

  At time T7, since the output data CMV of the comparison value holding circuit 64 and the output data CNT of the counter circuit 66 match, the comparator 68 outputs “1” as the match signal CMR. Since the coincidence signal CMR is “1”, the control circuit 62 determines that the wait instruction operation is finished, and outputs “0” as the control signal EC3. Then, the OR circuit 127 outputs “0” as the control signal ECP.

  Since the control signal ECP is “0”, the FF 484 of the clock control circuit 480 outputs “0” as the control signal FEC. The AND circuit 486 outputs the clock signal CLK as it is as the clock signal CKP. Accordingly, the supply of the clock signal CKP to the CPU 110 is resumed from time T8, and the CPU 110 starts a normal pipeline operation.

  As described above, since the information processing apparatus of FIG. 9 includes the clock control circuit 480, it is not necessary to supply a useless clock signal to the CPU 110 during execution of a wait instruction, and power consumption can be suppressed.

  Note that when the arithmetic unit 123 or 124 waits for a plurality of cycles of the CPU 110 according to the extension instruction to perform the arithmetic processing, the supply of the clock signal CKP to the CPU 110 can be similarly controlled, and the power at the time of execution of the extension arithmetic is executed. Consumption can be suppressed.

(Fifth embodiment)
In this embodiment, an example in which an extended arithmetic unit controls an external circuit will be described.

  FIG. 12 is a block diagram showing the configuration of the information processing apparatus according to the fifth embodiment of the present invention. The information processing apparatus 500 in FIG. 12 is the same as the information processing apparatus 100 in FIG. 1 except that an extended arithmetic unit 520 is provided instead of the extended arithmetic unit 120. The extended arithmetic unit 520 is the same as the extended arithmetic unit 120 except that it has a control signal generation circuit 525 instead of the control signal generation circuit 125. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 13 is a block diagram illustrating a configuration example of the control signal generation circuit 525 of FIG. The control signal generation circuit 525 is the same as the control signal generation circuit 125 in FIG. 2 except that a control circuit 562 is provided instead of the control circuit 62.

  FIG. 14 is a timing chart showing an example of the operation of the information processing apparatus 500 of FIG. The external signal output command A (signal generation command) is an extended command for causing the extended arithmetic unit 520 to output a control signal to the outside of the information processing apparatus 500 after the time set by the CPU has elapsed. The external signal output command B (signal generation command) is an extended command for causing the extended arithmetic unit 520 to repeatedly output a control signal to the outside of the information processing apparatus 500 at time intervals set by the CPU. The signal generation end instruction is an extension instruction for ending the operation for the external signal output instruction B.

  Hereinafter, as an example, a case will be described in which the control signal output by the external signal output command A and the external signal output command B is a control signal for an interrupt request, and the interrupt end command is used as the signal generation end command. The external signal output command A, the external signal output command B, and the interrupt end command are described as, for example, “SWIO Dm”, “SWII Dm”, and “SWIE” (Dm indicates one of the registers D0 to D3). .

  In FIG. 14, “IO” of each stage indicates that the external signal output instruction A is being processed, “II” indicates that the external signal output instruction B is being processed, and “IE” Indicates that an interrupt end instruction is being processed.

  The operation of the information processing apparatus 500 when the external signal output command A is executed will be described. As in the case of the wait instruction, the CPU 110 reads the external signal output instruction A from the ROM 130, performs decoding, and outputs the obtained decode signal CDC. The CPU control circuit 112 generates various control signals PCN based on the decode signal CDC and outputs them to each circuit of the CPU 110.

  The extension instruction decoder 121 of the extension arithmetic unit 520 decodes the external signal output instruction A and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the external signal output instruction A has been executed, and outputs a control signal IC3 at times T1 to T2.

  At time T2, the CPU 110 reads a value from the register Dm of the general-purpose register 113 and outputs it to the data input bus 143 according to various control signals PCN obtained as a result of decoding the external signal output instruction A. Control circuit 562 of control signal generation circuit 525 starts processing of external signal output command A in accordance with control signal IC3. The control circuit 562 controls the comparison value holding circuit 64 and the counter circuit 66 in the same manner as the control circuit 62 in FIG. The comparator 68 compares the output data CMV of the comparison value holding circuit 64 with the output data CNT of the counter circuit 66 and outputs “0” as the match signal CMR because they do not match.

  During execution of the external signal output instruction A, the control circuit 562 always outputs “0” as the control signal EC3, and does not stop the pipeline operation of the CPU 110. Since the coincidence signal CMR is “0”, the control circuit 562 outputs “1” as the control signal INR. During execution of the external signal output instruction A, the comparison value holding circuit 64 holds the value, and the counter circuit 66 continues to count up. Since the comparator 68 outputs “0” as the coincidence signal CMR until the output data CMV and the output data CNT coincide with each other, the control circuit 562 continues to output “1” as the control signal INR.

  At time T5, since the output data CMV and the output data CNT match, the comparator 68 outputs “1” as the match signal CMR. Since the match signal CMR is “1”, the control circuit 562 outputs “0” as the control signal INR, and ends the operation for the external signal output command A at time T6. The interrupt control circuit 302 outputs an interrupt signal to the CPU 110 because the control signal INR supplied from the extended arithmetic unit 520 becomes “0”, and the CPU 110 starts interrupt processing.

  As described above, since the extended arithmetic unit 520 outputs the control signal INR to the outside, the CPU 110 is interrupted after the number of cycles set in the register Dm by executing the external signal output instruction A. be able to.

  An operation of the information processing apparatus 500 when the external signal output command B is executed will be described. At times T6 and T7, the CPU 110 reads the external signal output command B from the ROM 130 and decodes it. The CPU control circuit 112 outputs various control signals PCN to each circuit inside the CPU 110.

  The extension instruction decoder 121 of the extension arithmetic unit 520 decodes the external signal output instruction B and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the external signal output instruction B has been executed, and outputs a control signal to each circuit in the extension arithmetic unit 520.

  At time T8, the control circuit 562 of the control signal generation circuit 525 starts processing the external signal output command B according to the control signal IC3. The control circuit 562 controls the comparison value holding circuit 64 and the counter circuit 66 in the same manner as the control circuit 62 in FIG. The control circuit 562 holds information that the external signal output command B is being executed.

  The comparator 68 compares the output data CMV of the comparison value holding circuit 64 with the output data CNT of the counter circuit 66. At times T8 to T10, since they do not match, the comparator 68 outputs “0” as the match signal CMR, and the control circuit 562 outputs “1” as the control signal INR.

  At time T10, since the output data CMV and the output data CNT match, the comparator 68 outputs “1” as the match signal CMR, and the control circuit 562 outputs “0” as the control signal INR. Since the control circuit 562 holds information that the external signal output command B is being executed, even if the coincidence signal CMR becomes “1”, the value of the output data CNT of the counter circuit 66 is set to “0”. Only resetting does not end the operation, and the same operation is repeated after time T11.

  When a new external signal output command B is executed while the external signal output command B is being executed, the output data CMV of the comparison value holding circuit 64 is rewritten as shown at time T19 in FIG. Processing of output instruction B is continued. In this case, from the time when the output data CMV is rewritten, the control circuit 562 repeats the operation of repeatedly outputting an interrupt request for each number of cycles set in the new external signal output command B.

  Further, as shown at time T26 in FIG. 14, when the interrupt end instruction is executed, the control circuit 562 of the control signal generation circuit 525 ends the operation and resets the counter circuit 66.

  As described above, by executing the external signal output instruction B, an interrupt request can be output for each number of cycles set in the register Dm, and by executing the interrupt end instruction, The operation can be terminated.

  Note that the control signal INR output from the extended arithmetic unit 520 is given to an interrupt control circuit 302 that controls an interrupt to the CPU 110, but a circuit outside the information processing apparatus 500, such as a processor, a timer, and A You may make it give to / D converter etc. Then, these circuits can be controlled by the control signal INR.

  As described above, the extension computing unit 520 outputs the control signal INR of the control signal generation circuit 525 to a circuit outside the information processing apparatus 500, so that the information processing apparatus 500 executes one extension instruction. Thus, a circuit outside the information processing apparatus 500 can be directly controlled.

(Sixth embodiment)
Although the external circuit can be controlled with the apparatus shown in FIG. 12, a control signal having a specific waveform is often required to control the external circuit. Therefore, in this embodiment, the length of the period in which the control signal is “0” and the length of the period in which “1” is set are set using two pieces of data supplied to the extended arithmetic unit 120. It is possible to output a control signal having a waveform.

  FIG. 15 is a block diagram showing the configuration of the information processing apparatus according to the sixth embodiment of the present invention. The information processing apparatus 600 in FIG. 15 is the same as the information processing apparatus 100 in FIG. 1 except that an extended arithmetic unit 620 is provided instead of the extended arithmetic unit 120. The extended arithmetic unit 620 is the same as the extended arithmetic unit 120 except that it has a control signal generation circuit 625 instead of the control signal generation circuit 125. The A / D converter 602 is external to the information processing apparatus 600 and performs A / D conversion processing according to the control signal CAD supplied from the control signal generation circuit 625 of the extended arithmetic unit 620. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 16 is a block diagram showing a configuration example of the control signal generation circuit 625 of FIG. The control signal generation circuit 625 includes a control circuit 662 instead of the control circuit 62, and is similar to the control signal generation circuit 125 of FIG. 2 except that it further includes a comparison value holding circuit 665 and a selector 667. It is.

  FIG. 17 is a timing chart showing an example of the operation of the information processing apparatus 600 of FIG. The signal generation command is an extension for generating a control signal in which the length of a period whose value is “0” and the length of a period whose value is “1” are specified using the number of cycles set by the CPU. It is an instruction. The signal generation instruction is described, for example, as “SWSG Dm, Dn” (Dm, Dn indicates one of the registers D0 to D3). In FIG. 17, “SG” in each stage indicates that a signal generation instruction is being processed.

  An operation of the information processing apparatus 600 when the signal generation instruction is executed will be described. As in the case of the wait instruction, the CPU 110 reads the signal generation instruction from the ROM 130, performs decoding, and outputs the obtained decoded signal CDC. The CPU control circuit 112 generates various control signals PCN based on the decode signal CDC and outputs them to each circuit of the CPU 110.

  The extension instruction decoder 121 of the extension arithmetic unit 620 decodes the signal generation instruction and outputs the obtained decode signal EDC. The extension instruction control circuit 122 determines from the decode signal EDC that the signal generation instruction has been executed, and outputs a control signal IC3 at times T1 to T2.

  At time T2, the CPU 110 reads a value from the register Dm of the general-purpose register 113 according to various control signals PCN obtained as a result of decoding the signal generation instruction, outputs the value to the data input bus 143, and outputs a value from the register Dn of the general-purpose register 113. Is output to the data input bus 144. The control circuit 662 in the control signal generation circuit 625 starts processing of a signal generation command according to the control signal IC3, and generates and outputs the control signals CH, CC, CS.

  The comparison value holding circuit 64 holds the value of the data input bus 143 according to the control signal CH, and outputs it as output data CM1. The comparison value holding circuit 665 holds the value of the data input bus 144 in accordance with the control signal CH and outputs it as output data CM2. The selector 667 selects and outputs the output data CM1 according to the control signal CS. The counter circuit 66 starts counting up according to the control signal CC and outputs the count value as output data CNT.

  The comparator 68 compares the output data of the selector 667 with the output data CNT and outputs “0” as the match signal CMR because they do not match. While the signal generation instruction is being executed, the control circuit 662 always outputs “0” as the control signal EC3 and does not stop the pipeline operation of the CPU 110. Since the coincidence signal CMR is “0”, the control circuit 662 outputs “1” as the control signal CAD.

  During the execution of the signal generation instruction, the comparison value holding circuits 64 and 665 hold the value, and the counter circuit 66 continues to count up. Since the comparator 68 outputs “0” as the coincidence signal CMR until the output data of the selector 667 coincides with the output data CNT, the control circuit 662 continues to output “1” as the control signal CAD.

  At time T5, the output data of the selector 667 matches the output data CNT, so the comparator 68 outputs “1” as the match signal CMR. Since the match signal CMR is “1”, the control circuit 662 outputs “0” as the control signal CAD at time T6, switches the control signal to the selector 667, resets the counter circuit 66, and holds the counter circuit 66. Set the value to “0”.

  The selector 667 selects and outputs the output data CM2 according to the control signal from the control circuit 662. The counter circuit 66 starts counting up again in accordance with the control signal from the control circuit 662, and outputs the count value as output data CNT. The comparator 68 compares the output data of the selector 667 with the output data CNT and outputs “0” as the match signal CMR because they do not match.

  Under the control of the control circuit 662, the comparison value holding circuits 64 and 665 hold values, and the counter circuit 66 continues to count up. Since the comparator 68 outputs “0” as the coincidence signal CMR until the output data of the selector 667 coincides with the output data CNT, the control circuit 662 continues to output “1” as the control signal CAD.

  At time T8, the output data of the selector 667 matches the output data CNT, so the comparator 68 outputs “1” as the match signal CMR. Since the coincidence signal CMR is “1”, the control circuit 662 outputs “0” as the control signal CAD, and ends the operation for the signal generation instruction at time T9. The A / D converter 602 executes A / D conversion processing based on the waveform of the control signal CAD supplied from the extended arithmetic unit 620.

  As described above, the extended arithmetic unit 620 executes the signal generation instruction, thereby using the two data read from the general-purpose register 113 of the CPU 110, the length of the period in which the value is “0”, the value A control signal in which the length of the period in which “1” is “1” is designated can be generated.

  Note that it is possible to easily implement an instruction for repeatedly executing the operation of the signal generation instruction, such as the external signal output instruction B described in the fifth embodiment, by using the control circuit 662. In this embodiment, the case has been described in which the number of cycles in the period in which the register Dm is “1” and the period in which the register Dn is “0” is specified.

(Seventh embodiment)
In the above embodiment, the length of the period related to the extension instruction is designated by the number of cycles of the clock signal. However, when the frequency of the clock signal is changed, the number of designated cycles needs to be changed. Therefore, in this embodiment, even if the frequency of the clock signal is changed, it is not necessary to change the software program.

  FIG. 18 is a block diagram showing the configuration of the information processing apparatus according to the seventh embodiment of the present invention. The information processing apparatus 700 in FIG. 18 is the same as the information processing apparatus 100 in FIG. 1 except that an extended arithmetic unit 720 is provided instead of the extended arithmetic unit 120. The extended arithmetic unit 720 is the same as the extended arithmetic unit 120 except that it has a control signal generation circuit 725 instead of the control signal generation circuit 125. The same components as those of the information processing apparatus 100 are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 19 is a block diagram showing a configuration example of the control signal generation circuit 725 of FIG. The control signal generation circuit 725 includes a control circuit 762 and a counter circuit 766 instead of the control circuit 62 and the counter circuit 66, and includes a reference cycle holding circuit 774, a counter circuit 776, a comparator 778, and an AND circuit 769. 2 is the same as the control signal generation circuit 125 of FIG. The counter circuit 766 counts pulses of the clock signal CLK when the control signal CMR2 output from the comparator 778 is “1”. The other points are the same as those of the counter circuit 66.

  FIG. 20 is a timing chart showing an example of the operation of the information processing apparatus 700 of FIG. The reference cycle setting instruction is an extension instruction that causes the reference cycle holding circuit 774 of the control signal generation circuit 725 to hold the number of cycles set by the CPU. The reference cycle setting instruction is described, for example, as “PUTD Dm” (Dm indicates one of the registers D0 to D3). In FIG. 20, “PD” in each stage indicates that a reference cycle setting instruction is being processed.

  An operation of the information processing apparatus 700 when the reference cycle setting instruction is executed will be described. As in the case of the wait instruction, the CPU 110 reads the reference cycle setting instruction from the ROM 130, performs decoding, and outputs the obtained decode signal CDC. The CPU control circuit 112 generates various control signals PCN based on the decode signal CDC and outputs them to each circuit of the CPU 110.

  The extended instruction decoder 121 of the extended arithmetic unit 720 decodes the reference cycle setting instruction and outputs the obtained decode signal EDC. The extended instruction control circuit 122 determines from the decode signal EDC that the reference cycle setting instruction has been executed, and outputs a control signal IC3 at times T1 to T2.

  At time T <b> 2, the CPU 110 reads a value from the register Dm of the general-purpose register 113 specified by the reference cycle setting instruction and outputs it to the data input bus 143. The control circuit 762 in the control signal generation circuit 725 outputs the control signal CSH according to the control signal IC3, and ends the operation for the reference cycle setting command. In accordance with the control signal CSH, the reference cycle holding circuit 774 holds the value of the data input bus 143 read from the register Dm as the reference cycle number, and outputs this as output data RC.

  As in the case of the reference cycle setting instruction, the CPU 110 reads and decodes the next wait instruction, and the CPU control circuit 112 generates various control signals PCN. The extension instruction decoder 121 decodes the wait instruction and outputs the obtained decode signal EDC. The extended instruction control circuit 122 determines from the decode signal EDC that the wait instruction has been executed, and outputs a control signal IC3 at times T2 to T3.

  At time T3, the CPU 110 reads a value from the register Dm of the general-purpose register 113 and outputs it to the data input bus 143 in accordance with various control signals PCN obtained as a result of decoding the wait instruction. The control circuit 762 starts the wait instruction processing according to the control signal IC3, and generates and outputs the control signals CH, CC, CSH, and CC2.

  Reference cycle holding circuit 774 outputs the held value as output data RC in accordance with control signal CSH. The counter circuit 776 performs a count-up operation of the pulse of the clock signal CLK according to the control signal CC2, and outputs the count value as output data CNT2. The comparator 778 compares the output data RC and the output data CNT2, and outputs “0” as the control signal CMR2 because they do not match.

  The comparison value holding circuit 64 holds the value of the data input bus 143 read from the register Dm as the number of wait cycles in accordance with the control signal CH, and outputs this as output data CMV. Since the control signal CMR2 is “0”, the counter circuit 766 does not perform the count-up operation and outputs the held value as the output data CNT. The comparator 68 compares the output data CMV and the output data CNT, and outputs “0” as the control signal CMR because they do not match.

  The logical product circuit 769 calculates a logical product between the control signal CMR and the control signal CMR2, and outputs the obtained “0” as the control signal CMP. Since the control signal CMP is “0”, the control circuit 762 outputs “1” as the control signal EC3. At this time, the OR circuit 127 outputs “1” as the control signal ECP. Since the control signal ECP is “1”, the CPU control circuit 112 outputs various control signals PCN and stops the pipeline operation of the CPU 110 from time T3.

  At time T4, since the control signal CMR2 is “0”, the counter circuit 766 does not perform the count-up operation and outputs the held value as the output data CNT. Since the output data CMV and the output data CNT do not match, the comparator 68 outputs “0” as the control signal CMR. Although the counter circuit 776 performs a count-up operation, since the output data RC and the output data CNT2 do not match, the control signals CMR2 and CMP are “0”, and the control signal EC3 output from the control circuit 762 does not change.

  At time T5, since the control signal CMR2 is “0”, the counter circuit 766 does not perform the count-up operation and outputs the held value as the output data CNT. Since the output data CMV and the output data CNT do not match, the comparator 68 outputs “0” as the control signal CMR. Since the counter circuit 776 performs a count-up operation and the output data RC and the output data CNT2 match, the comparator 778 outputs “1” as the control signal CMR2. The logical product circuit 769 calculates a logical product between the control signal CMR and the control signal CMR2, and outputs the obtained “0” as the control signal CMP. For this reason, the control signal EC3 does not change.

  Since the control signal CMR2 is “1” at time T6, the counter circuit 766 performs a count-up operation and outputs the count value as output data CNT. Since the output data CMV and the output data CNT do not match, the comparator 68 outputs “0” as the control signal CMR. The counter circuit 776 is reset by the control signal CMR2, and the count value becomes “0”. Since the output data RC and the output data CNT2 do not coincide again, the comparator 778 outputs “0” as the control signal CMR2. Since the control signal CMP is “0”, the control signal EC3 does not change. A similar operation is repeated until time T14.

  At time T14, since the control signal CMR2 is “0”, the counter circuit 766 does not perform the count-up operation and outputs the held value as the output data CNT. Since the output data CMV and the output data CNT match, the comparator 68 outputs “1” as the control signal CMR. Since the counter circuit 776 performs a count-up operation and the output data RC and the output data CNT2 match, the comparator 778 outputs “1” as the control signal CMR2. The logical product circuit 769 calculates a logical product between the control signal CMR and the control signal CMR2, and outputs the obtained “1” as the control signal CMP.

  Since the control signal CMP is “1”, the control circuit 762 determines that the wait command operation is finished, and outputs “0” as the control signal EC3. At this time, the OR circuit 127 outputs “0” as the control signal ECP. Since the control signal ECP is “0”, the CPU control circuit 112 outputs various control signals PCN and restarts the pipeline operation of the CPU 110 from time T15.

  As shown in FIG. 20, when the wait instruction is executed after the value of the register Dm is set in the reference cycle holding circuit 774 by the reference cycle setting instruction, “(reference cycle number + 1) × (wait cycle number + 1)” The processing of the CPU 110 can be made to wait for the period of the cycle. Therefore, if the setting of the reference cycle number is changed according to the frequency of the clock signal CLK, the waiting time of the CPU 110 can be kept constant without changing the setting of the wait cycle number. Therefore, it is not necessary to change the software program even if the frequency of the clock signal CLK is changed.

  For example, when the clock signal CLK is 10 MHz, 9 is set in the general-purpose register 113 so that the reference cycle number is 9. When the clock signal CLK is 15 MHz, 14 is set in the general-purpose register 113 and the reference cycle number is 14 may be set. When 9 is set in the general-purpose register 113 and a wait instruction is executed, the processing of the CPU 110 can be kept waiting for 10 microseconds in any case.

  As described above, according to the information processing apparatus of FIG. 18, even when the operating frequency of the CPU 110 is changed by changing the frequency of the clock signal, the CPU 110 is allowed to wait for a certain time without changing the software program. be able to.

  The control signal generation circuit 725 may be used in the first to sixth embodiments.

  FIG. 21 is a block diagram showing a modification of the control signal generation circuit 725 in FIG. A control signal generation circuit 825 in FIG. 21 may be used instead of the control signal generation circuit 725 in FIG. The control signal generation circuit 825 includes a control circuit 862, a counter circuit 866, and a comparator 868 instead of the control circuit 62, the counter circuit 66, and the comparator 68, and further includes a reference cycle holding circuit 774. This is the same as the control signal generation circuit 125 of FIG.

  In accordance with the control signal CSH, the reference cycle holding circuit 774 holds the value of the data input bus 143 read from the register Dm as the reference cycle number, and outputs this as output data RC. The counter circuit 866 adds the value of the output data RC supplied from the reference cycle holding circuit 774 for each pulse of the clock signal CLK according to the control signal CC, and outputs the obtained count value as output data CNT. The comparator 868 compares the output data CMV of the comparison value holding circuit 64 with the output data CNT of the counter circuit 866. When the value of the output data CNT becomes equal to or greater than the value of the output data CMV, “1” is output. The control signal CMR is output to the control circuit 862.

  According to the control signal generation circuit 825, when a wait instruction is executed after setting the reference cycle number in the reference cycle holding circuit 774 by a reference cycle setting instruction, the number of cycles obtained by “number of wait cycles / reference cycle number” is obtained. , CPU 110 can be made to wait.

  For example, when the clock signal CLK is 10 MHz, the reference cycle number is set to 2 by the reference cycle setting command, and when the clock signal CLK is 20 MHz, the reference cycle number is set to 1 by the reference cycle setting command. In any case, when the wait instruction is executed with the number of cycles set to 100, the processing of the CPU 110 can be kept waiting for 5 microseconds. Therefore, it is not necessary to change the software program even if the frequency of the clock signal CLK is changed.

  In addition, the circuit scale can be reduced by using the control signal generation circuit 825 than when the control signal generation circuit 725 is used.

  As described above, the present invention is useful for an information processing apparatus and the like because it can accurately control the waiting time when a main processing unit such as a CPU waits for processing.

It is a block diagram which shows the structure of the information processing apparatus which concerns on the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration example of a control signal generation circuit in FIG. 1. 3 is a timing chart illustrating an example of the operation of the information processing apparatus in FIG. 1. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 2nd Embodiment of this invention. FIG. 5 is a block diagram illustrating a configuration example of a calculator 224 in FIG. 4. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 3rd Embodiment of this invention. FIG. 7 is a block diagram illustrating a configuration example of a control signal generation circuit in FIG. 6. 7 is a timing chart illustrating an example of the operation of the information processing apparatus in FIG. 6. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 4th Embodiment of this invention. FIG. 10 is a block diagram illustrating a configuration example of a clock control circuit in FIG. 9. 10 is a timing chart showing an example of the operation of the information processing apparatus of FIG. 9. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 5th Embodiment of this invention. FIG. 13 is a block diagram illustrating a configuration example of a control signal generation circuit in FIG. 12. 13 is a timing chart showing an example of the operation of the information processing apparatus of FIG. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 6th Embodiment of this invention. 16 is a timing chart showing an example of the operation of the information processing apparatus of FIG. 16 is a timing chart showing an example of the operation of the information processing apparatus of FIG. It is a block diagram which shows the structure of the information processing apparatus which concerns on the 7th Embodiment of this invention. FIG. 19 is a block diagram illustrating a configuration example of a control signal generation circuit in FIG. 18. 19 is a timing chart illustrating an example of the operation of the information processing apparatus in FIG. 18. FIG. 20 is a block diagram illustrating a modification of the control signal generation circuit of FIG. 19.

Explanation of symbols

62, 262, 562, 662, 762, 862 Control circuit 64 Comparison value holding circuit 66, 766, 776, 866 Counter circuit 68, 778, 868 Comparator 110 CPU (main arithmetic unit)
120, 220, 320, 520, 620, 720 extended arithmetic unit (extended arithmetic unit)
113 General-purpose registers 125, 325, 525, 625, 725, 825 Control signal generation circuit (signal generation circuit)
224 arithmetic unit (signal generation circuit)
480 Clock control circuit 762 Reference cycle holding circuit

Claims (15)

A main arithmetic unit that performs processing in accordance with an instruction read from the memory;
An extended arithmetic unit that performs processing according to a predetermined instruction among the instructions read from the memory,
The extended arithmetic unit is:
When the instruction read from the memory is a standby instruction that waits for the main arithmetic unit to count pulses of the clock signal, a signal indicating that the instruction should be waited is designated in the standby instruction. It has a signal generation circuit that outputs until the count corresponding to the standby count is completed,
The main arithmetic unit is
The information processing apparatus is characterized in that the processing is stopped while the signal indicating that the standby should be performed. The information processing apparatus according to claim 1,
The main arithmetic unit is
Has a register to store the value,
The signal generation circuit includes:
When the register is specified in the standby instruction, the information stored in the register is used as the standby count number. The information processing apparatus according to claim 1,
The signal generation circuit includes:
An information processing apparatus using a value described in the standby instruction as the standby count number. The information processing apparatus according to claim 1,
The extended arithmetic unit is:
Has a register to store the value,
The signal generation circuit includes:
When the register is specified in the standby instruction, the information stored in the register is used as the standby count number. The information processing apparatus according to claim 1,
The signal generation circuit includes:
A comparison value holding circuit for holding the standby count number;
A counter for counting pulses of the clock signal;
A comparator that compares the count value of the counter with the standby count number held in the comparison value holding circuit and outputs a comparison result;
An information processing apparatus comprising: a control circuit that outputs a signal indicating that the standby should be performed until the comparison result indicates a match result. The information processing apparatus according to claim 1,
The signal generation circuit includes:
If the instruction read from the memory is an operation instruction, perform the operation indicated by the operation instruction,
When the instruction read from the memory is the standby instruction, the clock signal pulses are counted, and a signal indicating that the instruction should be waited is set to the standby count number specified in the standby instruction. An information processing apparatus that outputs until a corresponding count is completed. The information processing apparatus according to claim 1,
The signal generation circuit includes:
When the arithmetic circuit that performs the predetermined arithmetic operation and the instruction read from the memory is the standby instruction, the arithmetic circuit uses a count corresponding to the standby count number specified in the standby instruction. An information processing apparatus characterized by being performed. The information processing apparatus according to claim 1,
The signal generation circuit includes:
When an interrupt request signal is given to the main arithmetic unit, the information processing apparatus ends output of a signal indicating that it should wait. The information processing apparatus according to claim 1,
A clock control circuit for supplying the clock signal to the main arithmetic unit;
The clock control circuit includes:
An information processing apparatus that stops supply of the clock signal to the main arithmetic unit when a signal indicating that the standby should be performed is output from the signal generation circuit. The information processing apparatus according to claim 1,
The signal generation circuit includes:
When the instruction read from the memory is a first signal generation instruction for generating a control signal, when the count corresponding to the count number specified in the first signal generation instruction is completed,
An information processing apparatus that outputs the control signal to the outside of the information processing apparatus. The information processing apparatus according to claim 10,
The signal generation circuit includes:
When the instruction read from the memory is a second signal generation instruction that repeatedly generates the control signal, every time a count corresponding to the count number specified in the second signal generation instruction is performed,
Outputting the control signal to the outside of the information processing apparatus;
The information processing apparatus, wherein the output of the control signal is ended when the instruction read from the memory is a signal generation end instruction for ending generation of the control signal. The information processing apparatus according to claim 10,
The signal generation circuit includes:
When the first signal generation instruction is an interrupt instruction, the information processing apparatus outputs an interrupt request signal for interrupting the main arithmetic unit as the control signal. The information processing apparatus according to claim 1,
The signal generation circuit includes:
When the instruction read from the memory is a signal generation instruction for generating a control signal,
Until the count corresponding to the first count number specified in the signal generation instruction is completed,
Outputting a first value as the control signal to the outside of the information processing apparatus;
Until the count corresponding to the second count number specified in the signal generation instruction is completed,
An information processing apparatus that outputs a second value as the control signal to the outside of the information processing apparatus. The information processing apparatus according to claim 1,
The signal generation circuit includes:
An information processing apparatus that counts pulses of the clock signal for each set reference cycle number of the clock signal. The information processing apparatus according to claim 14,
The signal generation circuit includes:
A comparison value holding circuit for holding the standby count number;
A first counter for counting pulses of the clock signal;
A first comparator that compares the count value of the first counter with the standby count number held in the comparison value holding circuit and outputs the result as a first comparison result;
A reference cycle holding circuit for holding the reference cycle number;
A second counter that counts pulses of the clock signal and is reset according to a second comparison result;
A second comparator that compares the count value of the second counter with the reference cycle number held in the reference cycle holding circuit and outputs the result as the second comparison result;
A control circuit that outputs a signal indicating that the standby should be performed until the first comparison result indicates that the count value of the second counter is equal to or greater than the reference cycle number;
The information processing apparatus according to claim 1, wherein the first counter counts only when the second comparison result indicates a match result.

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