JP2009152690A - Mute circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a timing when a mute signal for stopping the operation of power amplifier turns off from being drifted by temperature in a mute circuit. <P>SOLUTION: The mute circuit generates the first muting signal Mute1 for muting an input signal to the power amplifier for a prescribed period from the power supply to the power amplifier, and the second muting signal Mute2 for stopping the operation of the power amplifier for a prescribed period from the power supply. The mute circuit includes: the first switching element Tr1 interposed in the output route of the first muting signal and interrupting the output route of the first muting signal at a prescribed timing after the power supply; and the second switching element Tr3 for stopping the output of the second muting signal after the power supply, based on a voltage on the output side of the first switching element, which is changed in response to the interruption of the output route by the first switching element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention provides a first mute signal for muting a signal input to the power amplifier for a predetermined period in order to turn on / off the music signal when the power amplifier is turned on, and a shock when the power amplifier is turned on. The present invention relates to a mute circuit that generates a second mute signal for stopping the operation of the power amplifier for a predetermined period in order to prevent noise.

  FIG. 2 is a circuit diagram showing a mute circuit in a conventional power amplifier. The mute circuit generates a mute signal Mute 21 for muting the input signal to the power amplifier for a predetermined period and a mute signal Mute 22 for stopping the operation of the power amplifier for a predetermined period when the power amplifier is turned on. To do. The mute circuit includes a PNP transistor Tr21 for performing on / off control of the mute signal Mute 21, an NPN transistor Tr23 for performing on / off control of the mute signal Mute 22, and an NPN transistor for performing on / off control of the transistor Tr23. Tr22 is provided.

  The emitter of the transistor Tr21 is connected to a power supply of +10 [V], and the collector is connected to the output terminal 21 of the mute signal Mute21. The base of the transistor Tr21 is connected to the power supply of +10 [V] through the resistor R21, and is connected to the ground through a series circuit of the resistor R22 and the electric field capacitor 21. The collector of the transistor Tr22 is connected to a power supply of +10 [V], and the emitter is connected to the base of the transistor Tr23 via a resistor R23. The base of the transistor Tr22 is connected to a connection point between the resistor R22 and the electric field capacitor C21.

  The collector of the transistor Tr23 is connected to the battery power source (+ B) via the resistor R25 and also connected to the output terminal 22 of the mute signal Mute22. The emitter is grounded and the base is connected to ground through a resistor R24. A series circuit of resistors R26 and R27 is provided between the power supplies of +15 [V] and −15 [V], and a collector of the transistor Tr21 is connected to a connection point between the resistors R26 and R27. An electric field capacitor C22 is provided in parallel with the resistor R27.

  FIG. 3 is a timing chart of main signals in the mute circuit of FIG. 3A shows the timing of the power supply (+10 V, + B), FIG. 3B shows the timing of the mute signal Mute 21, and FIG. 3C shows the timing of the mute signal Mute 22. When the power is turned on as shown in FIG. 9A, a voltage of +10 [V] is supplied through the transistor Tr21 in the on state, and the mute signal Mute21 rises as shown in FIG. At the same time, a voltage is applied from the power source (+ B) to the output terminal 22 via the resistor R25, and the mute signal Mute22 rises as shown in FIG. At this time, the transistor Tr22 is off.

  When 1.5 seconds determined by the resistance value of the resistor R22 and the capacitance of the electric field capacitor C21 have elapsed since the power is turned on, the charging of the electric field capacitor C21 is completed, the base voltage of the transistor Tr21 exceeds a predetermined value, and the transistor Tr21 is turned off. It becomes a state. Thereafter, the level of the mute signal Mute 21 decreases due to the discharge of the electric field capacitor C22, reaches 0 [V] 0.5 seconds later determined by the discharge speed of the electric field capacitor C22, and the mute signal Mute 21 is turned off.

  During this time, the transistor 22 supplies a voltage corresponding to a voltage that changes according to the charge amount of the electric field capacitor C21 to the base of the transistor Tr23, and this supply voltage rises gradually. When this supply voltage exceeds a predetermined threshold level, the transistor Tr23 is turned on. As a result, the output terminal 22 is grounded, and the mute signal Mute 22 is turned off as shown in FIG. Note that the timing at which the mute signal Mute22 is turned off is adjusted by changing the threshold level according to the resistance values of the resistors R23 and R24.

  In addition, as a mute circuit in a conventional power amplifier, there is known a circuit that performs a mute operation for protecting the power amplifier by an output of an operational amplifier as disclosed in Patent Document 1. In this mute circuit, the output voltage of the operational amplifier is changed by changing the input voltage applied to one input terminal of the operational amplifier when the temperature is higher than a predetermined level or when a load higher than a predetermined level is applied. .

Japanese Utility Model Publication No. 4-38119

  However, the mute circuit shown in FIG. 2 has a problem that the timing at which the mute signal Mute 22 is turned off drifts (changes) depending on the temperature, as indicated by the arrow 32 in FIG. This drift occurs when the timing at which the mute signal Mute22 is turned off is determined by the voltage of the electric field capacitor C21 that slowly changes according to the change in the charge amount.

  That is, the base-emitter voltage of the transistor Tr23 varies with temperature. Along with this, the threshold level of the voltage supplied by the transistor 22 for turning on the transistor Tr23 also changes. This threshold level is determined by the ratio of resistors R24 and R23. For example, when the resistance values of the resistors R23 and R24 are the same, and the base-emitter voltage of the transistor Tr23 changes from 0.6 [V] to 0.7 [V], the threshold level is 1.2 [V]. ] To 1.4 [V]. Such a change in the threshold level appears as a large change in the timing when the transistor Tr23 is turned on due to a slow voltage change in the electric field capacitor C21, and greatly affects the timing when the mute signal Mute22 is turned off. .

  The object of the present invention is to prevent the timing at which the mute signal for turning off the operation of the power amplifier from drifting in the mute circuit from drifting due to temperature in view of the problems of the prior art. It is in.

  In order to achieve this object, a mute circuit according to a first aspect of the present invention includes a first mute signal for muting an input signal to the power amplifier for a predetermined period after the power amplifier is turned on, and a predetermined time from the power on. A mute circuit for generating a second mute signal for stopping the operation of the power amplifier during a period, interposed in an output path of the first mute signal, at a predetermined timing after the power is turned on A first switching element that cuts off the output path of the first mute signal, and a voltage on the output side of the first switching element that changes according to the interruption of the output path by the first switching element after the power is turned on And a second switching element for stopping the output of the second mute signal.

  In this configuration, when the power amplifier is turned on, output of the first mute signal and the second mute signal is started. Thereby, the input signal to the power amplifier is muted and the operation of the power amplifier is stopped. Thereafter, at a predetermined timing, the output path of the first mute signal is blocked by the first switching element. As a result, the voltage on the output side of the first switching element decreases, and the first mute signal attenuates. The second switching element stops the output of the second mute signal based on the change in the voltage on the output side of the first switching element.

  A mute circuit according to a second invention is the mute circuit according to the first invention, wherein a parallel circuit of a capacitor and a resistor for attenuating the first mute signal after a predetermined period after the output path is cut off by the first switching element, It has between the output side of the said 1st switching element, and a predetermined voltage source, It is characterized by the above-mentioned.

  The mute circuit according to a third aspect of the present invention is based on the output side voltage of the first switching element so that the output of the second mute signal is stopped by the second switching element in the first or second aspect of the invention. An element for generating a voltage for controlling the second switching element is provided.

  In the mute circuit according to a fourth aspect of the present invention, in any one of the first to third aspects, the second switching element stops the output of the second mute signal and grounds the output of the second mute signal. It is what is performed by.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the predetermined timing at which the output path is blocked by the first switching element is determined by a charging time for a predetermined capacitor. It is characterized by that.

  According to the present invention, after the output path of the first mute signal is cut off, the output of the second mute signal is stopped based on the change in the voltage on the output side of the first switching element due to the cut off. The relationship between the timings at which the first mute signal and the second mute signal with different values are turned off can be maintained constant without depending on the environmental temperature. Therefore, when the timing for cutting off the output path of the first mute signal is independent of the environmental temperature, the timing for stopping the output of the second mute signal can also be independent of the environmental temperature.

  FIG. 1 is a circuit diagram showing a configuration of a mute circuit of a power amplifier according to an embodiment of the present invention. The mute circuit outputs a mute signal Mute 1 for muting the input signal to the power amplifier and a mute signal Mute 2 for stopping the operation of the power amplifier circuit from the terminals 1 and 2 as mute signals, respectively. The mute signal Mute2 is for stopping the operation of the power amplifier for a predetermined period in order to reduce a shock sound when the power of the power amplifier is turned on. As shown in the figure, the mute circuit includes a PNP transistor Tr1 that performs on / off control of the mute signal Mute1, an NPN transistor Tr3 that performs on / off control of the mute signal Mute2, and an on / off control of the transistor Tr3. A PNP transistor Tr2 is provided.

  The emitter of the transistor Tr1 is connected to a power supply of +10 [V], and the collector is connected to the output terminal 1 of the mute signal Mute1. The base of the transistor Tr1 is connected to the power supply of +10 [V] through the resistor R1, and is connected to the ground through a series circuit of the resistor R2 and the electric capacitor 1. The emitter of the transistor Tr2 is connected to a power supply of +10 [V]. The collector is connected to the base of the transistor Tr3 via the resistor R3. The base is connected to a power supply of +10 [V] through a resistor R4, and is connected to the collector of the transistor Tr1 through a resistor R5.

  The collector of the transistor Tr3 is connected to the battery power supply (+ B) via the resistor R6, and is connected to the output terminal 2 of the mute signal Mute2. The emitter of the transistor Tr3 is grounded, and the base is connected to the ground via a resistor R7. The collector of the transistor Tr1 is also connected to a power supply of −15 [V] through a parallel circuit of the resistor R8 and the electric field capacitor C2.

  FIG. 3 is a timing chart of main signals in the mute circuit of FIG. 3A shows the timing of the power supply (+ 10V, + B), FIG. 3B shows the timing of the mute signal Mute1, and FIG. 3D shows the timing of the mute signal Mute2. When the power is turned on as shown in FIG. 6A, a voltage of +10 [V] is supplied through the transistor Tr1 which is in the ON state, and the mute signal Mute1 rises as shown in FIG. The charging of the electric field capacitor C2 starts. At the same time, the mute signal Mute2 rises by the voltage applied to the output terminal 2 from the power source (+ B) via the resistor R6 as shown in FIG. At this time, since the voltage on the collector side of the transistor Tr1 is high and the transistor Tr2 does not supply a voltage for turning on the transistor Tr3, the transistor Tr3 is in the off state.

  When 1.5 seconds determined by the resistance value of the resistor R2 and the capacitance of the electric field capacitor C1 elapses after the power is turned on, the charging of the electric field capacitor C1 is completed and the base voltage of the transistor Tr1 exceeds a predetermined value. Turns off. At the same time, attenuation of the mute signal Mute1 due to the discharge of the electric field capacitor C2 starts as shown in FIG. Thereafter, when 0.5 seconds determined by the capacitance of the electric field capacitor C2 elapses, the waveform of the mute signal Mute1 crosses 0 [V]. At this cross point 31, the mute state of the input signal to the power amplifier is released.

  When the voltage supplied from the transistor Tr2 to the transistor Tr3 reaches a predetermined threshold level due to this attenuation, the transistor Tr3 is turned on. This threshold level is determined by the base-emitter voltage of the transistor Tr3 and the ratio of the resistors R7 and R3. For example, if the base-emitter voltage of the transistor Tr3 is 0.6 [V] and the resistance values of the resistors R7 and R3 are the same, the voltage is 1.2 [V]. When the transistor Tr3 is turned on, the output terminal 2 is grounded, and the mute signal Mute2 is turned off as shown in FIG.

  That is, the fact that the transistor Tr1 is turned off is detected by the transistor Tr2 based on the switching waveform of the mute signal Mute1 as shown in FIG. 3B, and the timing at which the transistor Tr3 is turned on based on the detection result ( The timing at which the mute signal Mute2 is turned off) is controlled.

  According to the present embodiment, the fact that the transistor Tr1 is turned off is detected by the transistor Tr2 based on the switching waveform of the mute signal Mute1 determined by the charging time of the electrolytic capacitor C1 and the discharge speed of the electrolytic capacitor C2, Since the timing at which the transistor Tr3 is turned on is controlled based on this, the timing at which the mute signal Mute2 is turned off can be prevented from drifting due to the influence of temperature. Therefore, the timing at which the mute signal Mute2 is turned off can be made as designed.

  Further, the relationship between the timings at which the mute signal Mute 1 and the mute signal Mute 2 having different uses are turned off can be maintained constant without depending on the environmental temperature.

  Note that the present invention is not limited to the above-described embodiment, and can be implemented with appropriate modifications. For example, in the above-described embodiment, a circuit is configured using a bipolar transistor as a switching element, but instead, a circuit may be configured using a field effect transistor as a switching element.

1 is a circuit diagram illustrating a configuration of a mute circuit of a power amplifier according to an embodiment of the present invention. FIG. It is a circuit diagram which shows the structure of the mute circuit in the conventional power amplifier. 3 is a timing chart of main signals in the mute circuit of FIGS. 1 and 2.

Explanation of symbols

  1, 2, 21, 22: output terminals, C1, C2, C21, C22: electric field capacitors, R1, R2, R3, R4, R5, R6, R7, R8, R21, R22, R23, R24, R25, R26, R27: resistor, Tr1, Tr2, Tr3, Tr21, Tr22, Tr23: transistors.

Claims (5)

A first mute signal for muting the input signal to the power amplifier for a predetermined period from the power-on of the power amplifier, and a second for stopping the operation of the power amplifier for a predetermined period after the power-on A mute circuit for generating a mute signal,
A first switching element interposed in the output path of the first mute signal and blocking the output path of the first mute signal at a predetermined timing after the power is turned on;
A second switching element that stops the output of the second mute signal based on a voltage on the output side of the first switching element that changes in response to interruption of an output path by the first switching element after the power is turned on; A mute circuit comprising:   After the output path is cut off by the first switching element, a parallel circuit of a capacitor and a resistor for attenuating the first mute signal after a predetermined period includes an output side of the first switching element, a predetermined voltage source, The mute circuit according to claim 1, further comprising:   An element for generating a voltage for controlling the second switching element based on the voltage on the output side of the first switching element so that the output of the second mute signal is stopped by the second switching element; The mute circuit according to claim 1, wherein:   The said 2nd switching element performs the output stop of a said 2nd mute signal by grounding the output of a said 2nd mute signal, The any one of Claims 1-3 characterized by the above-mentioned. Mute circuit.   5. The mute circuit according to claim 1, wherein the predetermined timing at which the output path is blocked by the first switching element is determined by a charging time for a predetermined capacitor.

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