JP2009152573A - Multi-tier capacitor structure, method for manufacturing the same, and substrate using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor whose noise processing capability is high. <P>SOLUTION: A multi-tier capacitor structure 500 has at least one multi-tier conductive layers 511, 512, 513, 521, 522, and 523. At least one conductive via passes through the multi-tier conductive layers. When currents flow through the conductive via, different current paths are presented in the conductive via in response to different current frequencies; in other words, different inductor is induced. A multi-tier capacitor structure thereby has a function of hierarchical decoupling capacitor effect. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

This application claims the priority of Taiwan Patent Application No. 96144117 filed on Nov. 21, 2007. The entirety of this patent application is hereby incorporated by reference and made a part hereof.
The present invention relates to a multistage capacitor structure, a manufacturing method thereof, and a substrate using the same.

  Today's electronic circuits such as computers have powerful functions and increased processing speed. Along with the increasing operating frequency of electronic circuits, the noise at its power and ground terminals is becoming an increasingly important issue. In order to reduce this noise, a so-called decoupling capacitor is introduced and disposed between the power supply and the circuit.

  In addition, the transient current required by the chip during operation may be higher than the available current supplied by the chip built-in capacitor, which may lead to degradation of chip processing performance. To solve this problem, external capacitors are placed outside the chip or at a suitable location on the chip surface, but some of the chip circuit area that can draw a large amount of transient current is referred to below as a “hot spot”. Called.

  In general, for the purpose of improving performance, the position where the decoupling capacitor is disposed is preferably as close as possible to the die load or hot spot. In particular, the decoupling capacitors are usually arranged on the die side or land side of the chip. FIG. 1 is a cross-sectional view of an integrated circuit (IC) 104 having a die side capacitor 106 and a land side capacitor 108 in the prior art. As shown in FIG. 1, the IC 104 is disposed on the substrate 102. The die side capacitor 106 is disposed on the same surface as the IC 104, and the land side capacitor 108 is disposed on the surface facing the IC 104.

  FIG. 2 is an equivalent circuit diagram of FIG. The die load 202 in this figure represents some portion of the integrated circuit (IC) 104 that requires the current supplied by the capacitor. The current may be supplied by the chip built-in capacitor 204 of the IC 104 or may be supplied by the external capacitor 206 (for example, the die side capacitor 106 and the land side capacitor 108 in FIG. 1). However, due to the chip package, the capacitor 206 needs to be separated from the die load 202, which causes the inductance effect represented by the inductor 208. As the inductance (or impedance) of the inductor 208 increases, the response speed of the capacitor 206 decreases, and the noise processing capability of the capacitor 206 decreases accordingly. That is, as the inductance (or impedance) of the inductor 208 increases, the noise processing capability of the capacitor 206 decreases. As a result, the circuit efficiency is significantly affected.

  In order to overcome the above-mentioned problems, a hierarchical capacitor structure has already been developed. 3 is a cross-sectional view of a conventional hierarchical capacitor structure, and FIG. 4 is an equivalent circuit diagram of FIG.

  Referring to FIGS. 3 and 4, the conventional hierarchical capacitor structure 300 includes three capacitor structures 302, 304, and 306. Capacitor structure 302 is defined by layers 311-315 (including both dielectric and conductive layers), capacitor structure 304 is defined by layers 316-320 (including both dielectric and conductive layers), and capacitor structure 306 is defined as Defined by layers 321-325 (including both dielectric and conductive layers). Capacitor structures 302, 304, and 306 are electrically connected to layers 311-325 through conductive vias 330, 332, and 334, the coupling of which is shown in FIG.

  Capacitor structures 302, 304, and 306 are electrically connected to external circuitry by conductive vias 330, 332, 334, upper connector 340, and lower connector 342.

  The amount of conductive vias 330, 332, and 334 through the capacitor structure can affect the effective capacitance and effective inductance of the capacitor structure. Specifically, as the conductive vias 330, 332, and 334 increase, the effective capacitance and effective inductance of the capacitor structure decreases, and as the conductive vias 330, 332, and 334 increase, the effective inductance of the capacitor structure increases. Furthermore, connecting the conductive vias 330, 332, and 334 in parallel can reduce the effective inductance of the capacitor structure.

  The equivalent circuit of the capacitor structure 302 includes a capacitor 408 and an inductor 420 as shown in FIG. 4, and the equivalent circuit of the capacitor structure 304 includes a capacitor 410 and an inductor 422 as shown in FIG. Includes a capacitor 412 and an inductor 424 as shown in FIG. 4, where the capacitance of these three capacitors is 412> 410> 408 and the inductance of these three inductors is 424> 422> 420. Since the current rate of the capacitors is affected by the current path (ie, inductor), the current rates of these three capacitors are 408> 410> 412. FIG. 4 is an equivalent circuit diagram of the conventional hierarchical capacitor structure of FIG. 3, in which the capacitor 404 represents a chip built-in capacitor.

  By the combination of the capacitor 408 and the inductor 420, the capacitor 408 having a function of suppressing high frequency noise is achieved. Since the capacitor 408 has a small capacitance, the available transient current (high frequency) supplied by the capacitor 408 is not large.

  Since the current rate of the capacitor 410 is slower than that of the capacitor 408, the capacitor 410 is suitable for suppressing medium wave noise, and the current rate of the capacitor 412 is the slowest, so that the capacitor 412 is suitable for suppressing only low frequency noise. ing.

  When a die load draws current, typically the die load draws different currents from different conductive vias. For example, a die load draws a large current from nearby conductive vias and a small current from distant conductive vias. Thus, assuming that some conductive vias are disposed around a small capacitor structure (eg, 302 in FIG. 3), some of the current draw points may reduce the expected effect of decreasing inductance. May still not contribute to (because conductive vias are not efficiently connected in parallel). Therefore, the combination of the inductor and capacitor in FIG. 3 (a large capacitor in pairs with a large inductor and a small capacitor in pairs with a small inductor) does not function as expected. In addition, although the capacitor structure 304 is designed to pair with an equivalent medium inductor 422, the current path between the current-draw point and the capacitor structure 304 is still too long, which causes the capacitor structure 304 to 3 is larger than the intermediate inductor 422, and the architecture of FIG.

  That is, in the architecture of FIG. 3, only effective parallel connected conductive vias can effectively reduce inductance, but this does not guarantee an effective parallel connected conductive via, which is This is an actual obstacle to functioning as a hierarchical decoupling capacitor structure.

  The present invention relates to a multi-stage capacitor structure and a substrate using the capacitor structure, and the current-drawing point of the die load is paired with a current path having a minimum impedance (that is, a minimum inductance) for efficient parallel connection. May be achieved.

  The present invention also relates to a method of manufacturing a multilayer multi-stage capacitor structure that can improve the manufacturing yield and change the capacitance as required.

  The present invention also relates to a method for manufacturing a single-layer multi-stage capacitor structure in which the manufacturing yield can be improved and the capacitance can be changed as necessary.

  The present invention relates to a multistage capacitor structure and a substrate having the capacitor structure. In one embodiment, the multi-stage capacitor structure includes an upper conductive layer, a lower conductive layer, and a dielectric layer disposed between the upper conductive layer and the lower conductive layer. The upper conductive layer, the intermediate dielectric layer, and the lower conductive layer form a multi-stage capacitor structure. At least one of the conductive layers described above has a multi-step cross section.

  In one embodiment, the present invention provides a method for manufacturing a multi-stage capacitor structure including a lower conductive layer. The lower conductive layer has a first conductive layer and a second conductive layer, and the lower conductive layer has a multistage cross section. The method further provides an upper conductive layer and a first dielectric layer, and the multi-stage lower conductive layer is combined with the first dielectric layer and the upper conductive layer to form a multi-stage capacitor structure.

  It should be understood that both the foregoing general description and the following detailed description are exemplary, and the intent is to provide further examples of the claimed invention.

  In order to facilitate further understanding of the present invention, it is incorporated into and constitutes a part of this specification including the attached drawings. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1 is a cross-sectional view of an IC 104 having a die-side capacitor 106 and a land-side capacitor 108 in the prior art.

FIG. 2 is an equivalent circuit diagram of FIG. 1.

It is sectional drawing of the conventional hierarchical capacitor structure.

FIG. 4 is an equivalent circuit diagram of FIG. 3.

1 is a cross-sectional view of a multi-stage capacitor structure according to an embodiment of the present invention. 1 is a cross-sectional view of a multi-stage capacitor structure according to an embodiment of the present invention.

2 shows a two-stage conductive layer structure.

A three-stage conductive layer structure is shown.

An actual two-stage conductive layer structure is shown.

An actual three-stage conductive layer structure is shown.

6 shows a current path corresponding to a high frequency of the capacitor structure of FIG. 5 and its equivalent circuit. 6 shows a current path corresponding to the medium wave of the capacitor structure of FIG. 5 and its equivalent circuit. 6 shows a current path corresponding to the low frequency of the capacitor structure of FIG. 5 and its equivalent circuit.

The modification of the capacitor | condenser structure of embodiment is shown. The modification of the capacitor | condenser structure of embodiment is shown. The modification of the capacitor | condenser structure of embodiment is shown. The modification of the capacitor | condenser structure of embodiment is shown. The modification of the capacitor | condenser structure of embodiment is shown. The modification of the capacitor | condenser structure of embodiment is shown.

6 illustrates a multilayer multi-stage capacitor structure 800 according to another embodiment of the present invention.

6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention.

6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention. 6 illustrates a manufacturing process for a multi-stage capacitor structure in accordance with another embodiment of the present invention.

FIG. 10 shows a capacitor structure 1100 according to another embodiment of the invention.

FIG. 10 shows a capacitor structure 1200 according to yet another embodiment of the present invention. FIG.

6 illustrates a multilayer multi-stage capacitor structure 1300 according to yet another embodiment of the invention.

A conventional single plate capacitor structure is shown.

A conventional three-plate capacitor structure is shown.

6 shows a multi-stage capacitor structure 1400C according to yet another embodiment of the invention.

The impedance characteristic curves of the capacitor structure of the above-described embodiment and the conventional capacitor structure are shown.

2 is a cross-sectional view of an IC package 1604, a silicon interposer 1606, a socket 1608, and a PC board (printed circuit board, PCB) 1610. FIG.

Fig. 4 shows the melt flow during the manufacture of a single-tier plate capacitor according to a conventional process.

FIG. 3 shows a melt flow during manufacturing of a single layer multi-stage capacitor according to the process of one embodiment of the present invention.

Fig. 3 shows melt flow during the manufacture of a multi-tier plate capacitor according to a conventional process.

FIG. 4 illustrates melt flow during multi-layer multi-stage capacitor manufacture according to the process of one embodiment of the present invention. FIG.

  Preferred embodiments of the invention will now be described, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used between the drawings and the description indicates the same or similar parts.

  The present invention provides a multi-stage capacitor structure and a substrate using the capacitor structure, and the current drawing point of the die load is paired with a current path having a minimum impedance (that is, a minimum inductance), and an effective parallel connection is provided. May be achieved. In addition, the present invention also provides a method for manufacturing a multilayer multi-stage capacitor structure that can improve manufacturing yield and change capacitance based on requirements.

  In one embodiment, the present invention provides a multi-stage capacitor structure and a substrate having a multi-stage capacitor structure. In one embodiment, the multi-stage capacitor structure includes a lower conductive layer, an intermediate dielectric layer, and an upper conductive layer, at least one of the two conductive layers having a multi-tier cross section.

  In one embodiment, the present invention provides a method for manufacturing a multi-stage capacitor structure including a lower conductive layer. The lower conductive layer has a first conductive layer and a second conductive layer, and has a multistage cross section. The method further provides an upper conductive layer and a first dielectric layer, and the multi-stage lower conductive layer, the dielectric layer, and the upper conductive layer are combined to form a multi-stage capacitor structure.

The cross section of the lower conductive layer of the multistage capacitor structure of the present invention will be described as an example. The term “multi-stage” is defined as the lower conductive layer having at least a first stage and a second stage.
The first stage has a first top surface, and the second stage has a second top surface that is higher than the first top surface. In one embodiment, the second stage may be disposed on the surface of the first stage. In another embodiment, a plurality of second stages may be disposed on the first top surface of the first stage at a distance next to each other.

  For example, the plurality of second stages may be arranged by being grouped according to height (the stages having the same height are divided into the same group). There may be multiple groups of varying heights. This is an example of an embodiment. Different configurations are conceivable for different designs (e.g. the second stage pattern), which are also within the scope of the present invention.

  In yet another embodiment, the “multi-stage” further includes a third stage disposed on the first upper surface of the first stage and having a third upper surface. The third stage is adjacent to the second stage. The third upper surface is higher than the second upper surface. In one embodiment, the third stage is disposed at a distance next to the second stage. In another embodiment, the third stage may be disposed on the second top surface of the second stage.

  The cross section of the upper conductive layer of the multi-stage capacitor structure of the present invention may be an inverse multi-tier. In one embodiment, the reverse multi-stage may include at least a first reverse stage and a second reverse stage. The first reverse stage has a first lower surface and the second reverse stage has a second lower surface. The second lower surface is lower than the first lower surface.

  The second lower surface of the second opposite stage of the upper conductive layer of the multistage capacitor structure of the present invention is disposed opposite the second upper surface of the second stage of the lower conductive layer, and the upper conductive layer and The capacitance generated by the capacitor structure of the lower conductive layer may be adjusted as necessary.

  The second lower surface of the second opposite stage of the upper conductive layer of the multistage capacitor structure of the present invention is disposed at a position displaced from the second upper surface of the second stage of the lower conductive layer. The capacitance may be adjusted as necessary.

  The height of the second lower surface of the second opposite step of the upper conductive layer may be designed to be lower than the height of the second upper surface of the second step of the lower conductive layer. In one embodiment, the second opposite step of the plurality of upper conductive layers and the second step of the plurality of lower conductive layers are disposed opposite each other to complement each other's height.

  The “reverse multi-stage” of one embodiment further includes a third reverse stage having a third lower surface. The third reverse step may be disposed on a first lower surface of the first reverse step and adjacent to the second reverse step. In one embodiment, the height of the third lower surface is lower than the height of the second lower surface of the second opposite stage. In one embodiment, the third reverse stage and the second reverse stage are spaced apart next to each other. Alternatively, in another embodiment, the third reverse stage is disposed on the second lower surface of the second reverse stage. That is, the second reverse stage and the third reverse stage form a laminated structure.

  In the multistage capacitor structure of the present invention, the capacitance generated from the upper conductive layer and the lower conductive layer may be adjusted as necessary in the design of the structure of the upper conductive layer and the lower conductive layer. In another embodiment, multiple regions or layers with various dielectric coefficients may be disposed between the upper and lower conductive layers to form different capacitance values, which are designed as needed. It's okay.

  Specific examples of a multilayer multi-stage capacitor structure, a substrate using the capacitor structure, and a manufacturing method thereof will be described below through various embodiments.

  5A and 5B show cross-sectional views of a multi-stage capacitor structure according to one embodiment of the present invention. As shown in FIG. 5A, the multi-stage capacitor structure 500 includes a dielectric layer 540 and conductive layers 511, 512, 513, 521, 522, and 523. Here, the conductive layers 511, 512, and 513 function as lower conductive layers, and the conductive layers 521, 522, and 523 function as upper conductive layers. The three upper conductive layers and the three lower conductive layers are each referred to as a three-stage conductive layer structure.

  The conductive layers 511, 512, and 513 form multiple stages. The conductive layers 521, 522, and 523 also form multiple stages. For example, in a multi-stage embodiment, the effective cross section area of the conductive layer 511 may be the same as or different from the effective cross sectional area of the conductive layers 512 and 513 depending on design requirements. The effective area of the conductive layer 512 may be the same as or different from the effective area of the conductive layer 513 depending on design requirements. Of course, not all embodiments of the present invention are limited to the above relationships.

  The plate capacitor 510 is defined by a dielectric layer 540 and conductive layers 513 and 523. The plate capacitor 520 is defined by a dielectric layer 540 and conductive layers 512 and 522. The plate capacitor 530 is defined by a dielectric layer 540 and conductive layers 511 and 521. As can be seen from FIG. 5A, one skilled in the art will understand that the capacitance can be changed by changing the effective area or effective distance between the conductive layers of the capacitor structure. With different distances and different multi-stage structures, a co-plane hierarchical capacitor structure is formed to meet the requirements of a hierarchical decoupling capacitor structure.

  Referring to FIG. 5B, 551 and 550 represent patterned conductive layers, and TC and BC represent an upper connector and a lower connector, respectively. The conductive via 560 and the lower conductive layer 511-533 are electrically connected to one of the ground terminal VSS and the power terminal VCC, and the conductive via 561 and the upper conductive layer 521-523 are electrically connected to the other of the ground terminal VSS and the power terminal VCC. Is done. Conductive vias 560 and 561 may be electrically connected to other signal terminals of the circuit (not shown). As shown in FIG. 5B, the upper conductive layer 521-523 may have a through hole through which the conductive via 560 or 561 passes, and the lower conductive layer 511-513 may also have a through hole through which the conductive via 560 or 561 passes. . In the present embodiment, the upper conductive layers 521-523 are electrically connected to the conductive vias 561 instead of being electrically connected to the conductive vias 560, and the lower conductive layers 511-513 are electrically connected to the conductive vias 561. In addition, the conductive via 560 is electrically connected.

  5B passes through three conductive layers 511-513 and conductive via 561 passes through three conductive layers 521-523, but those skilled in the art will understand that conductive via 560 or 561 is at least one of multiple conductive layers. It will be appreciated that only conductive vias 560 or 561 need not pass through all conductive layers.

  The dielectric layer 541 is disposed between the conductive layer 550 and the conductive layer 521, and the dielectric layer 542 is disposed between the conductive layer 551 and the conductive layer 511.

  The so-called “multilevel conductive layer” in the above description is defined in FIGS. 5C and 5D. FIG. 5C shows a two-stage conductive layer structure 580. The multi-stage capacitor structure of this embodiment includes a lower conductive layer formed by a two-stage conductive layer structure 580, an intermediate dielectric layer 582, and an upper conductive layer 584. FIG. 5D shows a three-stage conductive layer structure 590. The multi-stage capacitor structure of this embodiment includes a lower conductive layer formed of a three-stage conductive layer structure 590, an intermediate dielectric layer 592, and an upper conductive layer 594.

  Referring to FIGS. 5E and 5F, cross-sectional schematic views of a “multi-stage conductive layer” formed by an actual manufacturing process are shown. FIG. 5E shows an actual two-stage conductive layer structure 580 ′. The multi-stage capacitor structure of this embodiment includes a lower conductive layer formed of a two-stage conductive layer structure 580 ′, an intermediate dielectric layer 582 ′, and an upper conductive layer 584 ′. FIG. 5F shows an actual three-stage conductive layer structure 590 ′. The multi-stage capacitor structure of this embodiment includes a lower conductive layer formed by a three-stage conductive layer structure 590 ′, an intermediate dielectric layer 592 ′, and an upper conductive layer 594 ′.

  Therefore, in this specification, the “multistage capacitor structure” refers to a capacitor structure including at least a multistage conductive layer structure.

  6A-6C show current paths corresponding to high frequency, medium wave, and low frequency, respectively, and their equivalent circuits of the capacitor structure of FIG. Here, the member 62 represents a chip built-in capacitor of the chip (not shown). Each current path through each of capacitors 510-530 is represented by an inductor 631-633. As can be seen from FIGS. 6A-6C, the inductors 631-633 have 633> 632> 631.

  As shown in FIG. 6A, when the die load 61 needs to draw a high frequency current, the capacitor 510 can supply the high frequency current, and the high frequency noise can be suppressed by the capacitor 510 and the small inductor 631. As shown in FIG. 6B, when the die load 61 needs to draw a medium wave current, the capacitors 510 and 520 can supply the medium wave current, and the medium wave noise includes the capacitor 510, the small inductor 631, the capacitor 520. , And the intermediate inductor 632. As shown in FIG. 6C, when the die load 61 needs to draw a low frequency current, the capacitors 510-530 can supply the low frequency current, and the low frequency noise includes the capacitor 510, the small inductor 631, the capacitor 520. , Intermediate inductor 632, capacitor 530, and large inductor 633.

  That is, the multistage capacitor structure of FIG. 5 can achieve the effect of suppressing the wideband frequency by effectively suppressing the high frequency noise, the medium frequency noise, and the low frequency noise.

  7A-7F show a modification of the capacitor structure of the embodiment. 710-723c represents a patterned conductive layer, 730 represents a dielectric layer, and 741a-746f represents a capacitor. Taking FIG. 7A as an example, conductive layers 710 and 720 define a plate capacitor 741a, and conductive layers 711 and 720 define another plate capacitor 741b. The conductive layer 710 may be a lower conductive layer of the multistage capacitor structure of the present invention, and the conductive layer 720 may be an upper conductive layer of the multistage capacitor structure of the present invention. The cross section of the conductive layer 710 may be multistage and the cross section of the conductive layer 720 may be reversed, or the cross sections of the conductive layers 710 and 720 may be multistage and reverse multistage, respectively. Depending on the design requirements, various multi-stage structures on the conductive layer 710 or the inverse multi-stage structure of the conductive layer 720 may be disposed at opposite positions, displaced positions, or opposite positions that complement the height. It is not limited to. In addition, the conductive layers 712a and 712b may be arranged in groups. For example, conductive layers having the same height may be the same group, and there may be a plurality of groups having various heights. It will be appreciated that this is only one exemplary embodiment. Various arrangements based on different designs (for example, arrangement of a plurality of conductive layers 712a and 712b depending on the pattern) are possible and are within the scope of the present invention. In addition, the positions of the conductive layers are not necessarily symmetrical with respect to the dielectric layer 730, and the thicknesses of the conductive layers are not necessarily the same. For example, in FIG. 7D, the positions of the conductive layers 714 and 721 are not symmetrical with each other, the thickness of the conductive layers 713a to 713c is not the same in FIG. 7C, and the thickness of the conductive layers 715 and 722 is the same in FIG. Not necessarily the same.

  In addition, by alternately arranging the upper and lower hierarchical conductive layers, the sidewalls of the upper / lower hierarchical conductive layers can form a capacitor (eg, capacitor 742d in FIG. 7B, 745d in FIG. 7E, And 746g in FIG. 7F), which increases the total capacitance. In any of the above-described embodiments, when the sidewalls of the upper / lower conductive layers are used for capacitance formation, it is necessary to isolate the corresponding conductive layers in a later process to generate a capacitance effect. is there. For example, in FIG. 7E, the conductive layer 715 can be separated from the lower conductive layer 710 by etching or other removal method in a later step. In addition, the conductive layer 722 may be separated from the upper conductive layer 720 by etching or other removal method in a later step. The two conductive layers can thus produce the illustrated capacitance effect 745d. When the upper / lower hierarchical conductive layers are alternately arranged, the polarities of these hierarchical conductive layers are also alternately changed. This produces very little inductance because the magnetic fields cancel each other, thereby contributing significantly to improving the high frequency performance of the capacitor element.

  FIG. 8 illustrates a multilayer stacked multi-stage capacitor structure 800 according to another embodiment of the present invention. Capacitor structure 800 includes conductive layers 801-815, dielectric layers 821, 823, and 831-835, and conductive vias 841, 842, 841 ′, 842 ′, 841 ″, and 842 ″. Capacitor structure 800 includes a multi-capacitor structure, namely 851, 852, 853, 854, and 855. Capacitor 851 is defined by conductive layers 801, 803, and 805, and dielectric layer 831, as is capacitor structure 852-855. In addition, dielectric layer 821 can be further used to bond capacitor structure 851 to 852 and dielectric layer 823 can be further used to bond capacitor structure 852 to 853. To function as a dielectric in a MIM (metal-insulator-metal) capacitor structure, the dielectric layers 821 and 823 may be formed from a material having a dielectric coefficient (high Dk).

  In FIG. 8, both capacitor structures 851 and 853 disposed on the surface layer of the capacitor structure 800 are counted as a multi-stage capacitor structure, and the capacitor structure 852 disposed in the inner layer of the capacitor structure 800 is counted as a multi-stage capacitor structure. Nonetheless, those skilled in the art will appreciate that the overall capacitor structure has at least one multi-stage capacitor structure, which is within the scope of the claims of the present invention.

  9A-9H illustrate a manufacturing process for a multi-stage capacitor structure according to another embodiment of the present invention. As shown in FIG. 9A, first, the barrier film 903 is combined with the copper foil 901 (conductive layer), and then the barrier film 903 is patterned by, for example, dry film press bounding. In another embodiment, the barrier film 903 may be formed on the copper foil 901 (conductive layer) by dipping such as but not limited to a wet film. Next, in FIG. 9B, another conductive layer 905 is combined with the conductive layer 901, and the conductive layers 901 and 905 form a multistage structure. Next, in FIG. 9C, the barrier film 903 is peeled off, thereby completing a two-stage conductive layer structure including two conductive layers 901 and 905. Thereafter, in FIG. 9D, barrier film 907 is combined with dielectric layers 901 and 905, and then barrier film 907 is patterned. In FIG. 9E, another conductive layer 909 is combined with the conductive layer 905, and the conductive layers 901, 905, and 909 form a multistage structure. In FIG. 9F, the barrier film 907 is further peeled off, thereby completing a three-stage conductive layer structure including the conductive layers 901, 905, and 909. Similarly, conductive layers 901 ′, 905 ′, and 909 ′ may be formed by the processing steps shown in FIGS. 9A-9F. Finally, as shown in FIG. 9G, the conductive layer 901-909 and the conductive layers 901′-909 ′ may be combined using the dielectric layer 911 to form the capacitor structure 900 shown in FIG. 9H.

  FIGS. 9A-9G described above illustrate a method of manufacturing a multi-stage structure of conductive layers 901-909 and 901′-909 ′, which is one method of implementing this embodiment, but is intended to limit the present invention. There is no waste. The multistage conductive layer may be formed by printing, coating, injection, or sputtering. In another embodiment, the multi-stage conductive layer structure may be directly press bound using a calendering process, or the multi-stage conductive layer structure may be molded using a molding process, Although included within the scope of the present invention, it is not limited thereto.

  10A-10H illustrate a manufacturing process for a multi-stage capacitor structure according to yet another embodiment of the present invention. As shown first in FIG. 10A, a substrate 1001 is provided, which includes conductive layers 1001a and 1001c, and a dielectric layer 1001b. The dielectric layer 100b has an adhesive property and can adhere the conductive layer 100a to 1001c. The substrate 1001 is formed by bonding the conductive layers 1001a and 1001c using the dielectric layer 1001b. Next, in FIG. 10B, each barrier film 1003 is combined with the upper and lower surfaces of the substrate 1001, and then the barrier film 1003 is patterned. Next, in FIG. 10C, the conductive layers 1005 are combined with the upper surface and the lower surface of the substrate 1001, respectively, to form a multistage structure in which the conductive layers 1005 each include conductive layers 1001a and 1001c. 10D, the barrier film 1003 is peeled off, thereby completing a two-stage multi-stage conductive layer structure including the conductive layers 1001a / 1005 and 1001c / 1005.

  Further, in FIG. 10E, the barrier film 1007 is integrally combined with the upper and lower surfaces of the substrate 1001, and then the barrier film 1007 is patterned. Further, in FIG. 10F, the conductive layer 1009 is combined with the upper conductive layer and the lower conductive layer 1005, respectively, and the conductive layer 1009 and the conductive layer 1005 form a multistage structure. Further, as shown in FIG. 10G, the barrier film 1007 is peeled off, thereby completing a three-stage multi-stage conductive layer structure including conductive layers 1001a, 1005, and 1009 and conductive layers 1001c, 1005, and 1009, respectively. The processing steps for manufacturing another three-stage conductive layer structure including 1001 ′, 1005 ′, and 1009 ′ may be the same as FIGS. 10A-10G. Finally, as shown in FIG. 10H, the capacitor structure 1000 is formed by combining the conductive layers 1001-1009 and the conductive layers 1001′-1009 ′ using the dielectric layer 1011.

  FIG. 11 illustrates a capacitor structure 1100 according to another embodiment of the present invention. First, for example, the capacitor structure 900 obtained in FIG. 9H is used as the substrate of FIG. 10A. Next, the process of FIGS. 10B-10H is performed on the capacitor substrate 900 to obtain the capacitor structure 1100 shown in FIG. In the capacitor structure 1100, a desired hierarchical decoupling capacitor structure can be obtained by changing the design of the multistage structure formed in each multistage conductive layer. Furthermore, the desired hierarchical decoupling capacitor structure can also be obtained by changing the effective distance between the upper and lower multi-level conductive layers, or by changing the dielectric coefficient of the dielectric layers or the number of dielectric layers. Can do.

  FIG. 12 illustrates a capacitor structure 1200 according to yet another embodiment of the present invention. Here, the dielectric coefficients of the dielectric layers 1201 to 1212 are basically different from those of the dielectric layers 911, 1001 b, and 1011. For example, after completing the conductive layer 905 and / or the conductive layer 909 shown in FIGS. 9A-9H, the dielectric layers 1201-1210 are formed at regular positions, or the conductive layers 1005, 1009, 1009, shown in FIGS. After completing 1005 'and 1009', dielectric layers 1211 and 1212 are formed in the proper positions. In this embodiment, the technique for forming the dielectric layer is, for example, ion implantation, but is not limited thereto, and ink jet printing, screen printing, sputtering, coating, press bounding, etc. may be employed. Not limited to.

  In the capacitor structure 1200, the multistage structure of each multistage conductive layer is changed, the effective distance between the upper multistage conductive layer and the lower multistage conductive layer is changed, the dielectric coefficient of the dielectric layer or the number of dielectric layers is changed. Thus, the desired capacitance of the hierarchical decoupling capacitor structure can be obtained. For example, the dielectric layers 1201-1212 of FIG. 12 may be utilized between the upper and lower multi-level conductive layers using various dielectric coefficients on different regions or layers on or near the multi-level conductive layers. The dielectric constant is changed and the desired capacitance of the hierarchical decoupling capacitor structure is designed.

  In the process of FIG. 9 or FIG. 10, dielectric layers having different dielectric coefficients are arranged on or near the multi-stage conductive layer by ion implantation, and the dielectric coefficients between the upper multi-stage conductive layer and the lower multi-stage conductive layer To obtain a desired hierarchical decoupling capacitor structure in design.

  Those skilled in the art will appreciate that the process of FIGS. 9-12 can be applied to the fabrication of the multi-stage capacitor structure of FIGS. 5 or 7A-7F. The process of FIGS. 9-12 can also be applied to the manufacture of multilayer multi-stage capacitor structures.

  FIG. 13 shows a multilayer multi-stage capacitor structure 1300 according to yet another embodiment of the invention. Capacitor structure 1300 includes conductive layers 1311-1317, dielectric layers 1331-1336, and conductive vias 1341-1347. Capacitor structure 1300 includes six layers of capacitor structures 1351-1356, which are defined by conductive layers 1311 and 1312 and dielectric layer 1311, as well as the remaining capacitor structures 1352-1356. In addition, the conductive layer 1312 is shared by the capacitor structures 1351 and 1352, as is the rest of FIG.

  Each of the conductive layers 1311 to 1317 in FIG. 13 is counted as a multistage conductive structure. However, those skilled in the art will not be limited to this, and it is sufficient that at least one of the conductive layers has a multistage conductive structure. Let's understand that. The method for manufacturing the conductive layer has been described in the above embodiment. Although the conductive vias 1341-1347 in FIG. 13 are through vias, those skilled in the art can use other types of conductive vias (eg, blind vias or buried vias) in the present invention, and conductive vias 1341, 1343, 1345. , And 1347 may be electrically connected to conductive layers 1311, 1313, 1315, and 1317, and conductive vias 1342, 1344, and 1346 may be electrically connected to conductive layers 1312, 1314, and 1316.

  The dielectric layer 1337 of FIG. 13 that is similar to FIG. 12 is disposed on or near the at least one conductive layer, and the dielectric coefficient of the conductive layer 1337 is that of the dielectric layers 1331-1336. And substantially different. As described above, the desired layer reduction is achieved by changing the effective conductivity coefficient between the upper and lower multi-level conductive layers (for example, between 1311 and 1312 in FIG. 13) using the dielectric layer 1337 having different dielectric coefficients. Get a coupling capacitor design.

  In addition, the conductive layers 1311-1317 are divided into a first conductive layer group and a second conductive layer group, and the first conductive layer group includes the conductive layers 1311, 1313, 1315, and 1317, and the second conductive layer The layer group includes conductive layers 1312, 1314, and 1316, and the conductive layers 1311, 1313, 1315, and 1317 of the first conductive layer group and the conductive layers 1312, 1314, and 1316 of the second conductive layer group are alternately arranged. It may be arranged.

  According to this embodiment, various desirable combinations of capacitors and inductors can be obtained by utilizing a multilayer multi-stage capacitor structure. In addition, utilizing a multi-layer multi-stage capacitor structure in conjunction with regular conductive vias, a hierarchical decoupling capacitor structure can be implemented in the previous embodiment, which reduces broadband noise depending on requirements.

  On each layer of the capacitor structure, each conductive via has a different current path and is connected in parallel to a different capacitance. In this way, a hierarchical decoupling capacitor structure is constructed between each conductive via and a reference voltage (eg, ground terminal). In practice, the conductive via corresponds to the pin of the power terminal or the pin of the ground terminal of the electronic circuit, so that a hierarchical decoupling capacitor structure can be constructed between the power terminal and the ground terminal of the circuit.

  In fact, the path from each conductive via to the ground or power terminal can be treated as a capacitor structure with different capacitances and different inductances, so that electronic circuits can be connected to appropriate conductive vias at different locations as needed. can do.

  14A-14C and 15 are shown to compare the capacitor structure of the present invention with a conventional capacitor structure. In FIG. 15, the relationship curves AC respectively correspond to the capacitor structures of FIGS. 14A-14C.

  FIG. 14A shows a conventional single plate capacitor structure 1400A, the capacitor structure having conductive vias. When the distance between the upper layer of the conductive layer structure and the lower layer of the conductive layer structure is required to be less than 10 μm, the current press bounding process is similar to an ultra-thin capacitor structure. Is difficult to manufacture.

  FIG. 14B shows a conventional three-plate capacitor structure 1400B, the capacitor structure having conductive vias, and the three-plate capacitor structure 1400B stacks three single-plate capacitor structures 1400A so that the distance is less than 10 μm. It is formed by that. Such an ultra-thin capacitor structure cannot be easily obtained.

  FIG. 14C illustrates a multi-stage capacitor structure 1400C according to yet another embodiment of the present invention, the capacitor structure having conductive vias. As can be seen from the above embodiment, the press bounding process of the multi-stage capacitor structure 1400C employs a dielectric layer having a thickness of more than 10 μm, and achieves a thickness of less than 10 μm by using an embedding technique. According to this, an ultra-thin capacitor structure can be manufactured more easily.

  Curves A and B in FIG. 15 show that the inductance cannot be changed even if the capacitance is increased by the parallel multilayer. However, from the curve C in FIG. 15, the capacitor structure provided by the embodiment of the present invention reduces the inductance and flows a high-frequency current path that flows through a small inductance, a medium-wave current path that flows through an intermediate inductance, and a large inductance. It will be appreciated that a hierarchical capacitor having a low frequency current path is achieved.

  The substrate having the multi-stage capacitor structure provided by the embodiment of the present invention may be a capacitor element, for example, embedded in another substrate, disposed on another substrate, or combined with an integrated circuit package substrate. Thus, it may be used in connection with systems having various configurations. That is, capacitors that employ different system package structures may connect signals with a multi-stage capacitor structure based on requirements. An example of this embodiment will be described in detail in connection with FIG.

  FIG. 16 is a cross-sectional view of an IC package 1604, a silicon interposer 1606, a socket 1608, and a PC board (printed circuit board, PCB) 1610. For the IC package 1604, silicon interposer 1606, socket 1608, or PC board 1610, one or more multi-stage capacitor structures provided by the above-described embodiments of the present invention are disposed, implanted, or integrated on the surface. Good. The multi-stage capacitor structure may be part of the overall structure of the substrate (eg, IC package 1604, silicon interposer 1606, or PC board 1610). One or more multi-stage capacitor structures provided by the above-described embodiments of the present invention may be disposed on the surface of the IC package 1604, the silicon interposer 1606, the socket 1608, or the PC board 1610. “1602” represents an IC. The silicon interposer 1606 may be referred to as a chip carrier, and the PCB and the chip carrier are counted as one type of substrate. That is, the one or more multi-stage capacitor structures of the present embodiment may be employed in one silicon substrate, chip carrier, ceramic substrate, glass substrate, flexible substrate, or printed circuit board.

  Capacitor 1603 (bold box) may be disposed on the surface of IC package 1604 (capacitor 1603 is accounted for as a discrete capacitor), disposed in the form of a member or an entire layer, or member of IC package 1604. Or it may be embedded in the form of an entire layer. Capacitors 1607, 1609 and 1611 (bold box) may be disposed on the surface of silicon interposer 1606 and / or socket 1608 and / or PC board 1610 (capacitors are counted as discrete capacitors) or silicon The interposer 1606 and / or the socket 1608 and / or the PC board 1610 may be embedded as an entire member or layer. In FIG. 16, the position of the bold box represents the position where the capacitor according to the above-described embodiment of the present invention can be disposed or embedded. That is, as shown in the example of FIG. 16, the multistage capacitor structure provided by the above-described embodiment of the present invention may be embedded in the form of a member, or may be integrated into the structure in the form of an entire layer.

  FIG. 17A shows the melt flow during manufacture of a single stage plate capacitor according to a conventional process, and FIG. 17B shows the melt flow during manufacture of a single stage plate capacitor according to the above-described embodiment of the present invention.

  As shown in FIG. 17A, in the prior art, in the border of the substrate 1700, the multi-stage conductive layer does not function as an obstacle during bonding, and therefore the melt flow in the prior art cannot be controlled. In contrast, in FIG. 17B, a multi-stage capacitor structure is provided in the board 1700 border and functions as an obstacle 1770 during bonding (ie, the multi-stage conductive layer shown in FIGS. 5A and 5B). Can be controlled. That is, in the embodiment of the present invention, the multi-stage capacitor structure functions as an adhesion obstacle in the border, so that the melt flow generated during the press bounding process can be controlled. Therefore, the uniformity of the thickness between the upper conductive layer and the lower conductive layer located in the circuit region is improved, and further, the distance between the upper conductive layer and the lower conductive layer is further reduced.

  FIG. 18A shows the melt flow during multi-stage plate capacitor manufacturing according to the conventional process, and FIG. 18B shows the melt flow during multi-stage plate capacitor manufacturing according to an embodiment of the present invention, where the substrates 1801 and 1851 are good. Thickness uniformity.

  As shown in FIG. 18A, in the prior art, the thickness of the adhesion failure needs to be equal to the thickness of the conductive layer in the circuit region so that the conventional structure does not function to hinder melt flow. Therefore, it is not easy to control the melt flow 1810, and the conventional capacitor structure 1800 is inferior in terms of thickness uniformity. When a conventional capacitor is formed on a thin substrate, the problem that the thickness uniformity is not good becomes more serious.

  As shown in FIG. 18B, in the steps provided by the above-described embodiment of the present invention, the thickness of the adhesion failure may not necessarily be equal to the thickness of the circuit region. Furthermore, the capacitor structure according to the above-described embodiment of the present invention can function as an adhesion barrier having different thicknesses, so that the melt flow 1860 can be controlled to make the thickness uniformity of the capacitor structure 1850 better. Even when the multi-stage capacitor structure according to the embodiment of the present invention is formed on a thin substrate, the thickness uniformity is still good.

  In the capacitor structure according to the above-described embodiment of the present invention, the material of the dielectric layer is not limited. For example, the dielectric layer may be formed of ceramic, and the capacitor structure according to the above-described embodiment of the present invention is referred to as a “ceramic capacitor”.

  In a MIM (metal-insulator-metal) capacitor structure, parallel connection of different capacitances can be achieved by a multi-stage capacitor structure having multi-stage conductive layers according to the above-described embodiments of the present invention.

  In addition, large inductances, intermediate inductances, and small inductances may be implemented by multi-level conductive layers with different step thicknesses, with large inductance paths corresponding to low frequency current paths and intermediate inductance paths Corresponding to the medium wave current path, a small inductance path is a further advantage in achieving a hierarchical capacitor structure corresponding to the high frequency current path. In contrast, the prior art requires multiple conductive vias connected in parallel to achieve large, intermediate, and small inductances, thus achieving a hierarchical capacitor structure with different frequency currents flowing through the appropriate inductances Can not do it.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In light of the above description, the present invention is intended to include various modifications and variations that are within the scope of the following claims and their equivalents.

Claims (53)

A multi-stage capacitor structure,
Comprising an upper conductive layer, an intermediate dielectric layer, and a lower conductive layer;
A multistage capacitor structure, wherein at least one of the upper conductive layer and the lower conductive layer has a multistage cross section.   The multistage capacitor structure according to claim 1, wherein a cross section of the lower conductive layer is multistage.   The multi-stage capacitor structure according to claim 2, wherein the multi-stage includes at least a first stage having a first upper surface and a second stage having a second upper surface higher than the first upper surface.   The multi-stage capacitor structure according to claim 3, wherein the second stage is disposed on the first stage.   5. The multi-stage capacitor structure according to claim 4, wherein the second stage includes one or more groups disposed on the first stage at a distance next to each other.   The multi-stage further includes a third stage having a third upper surface, wherein the third stage is disposed adjacent to the second stage on the first upper surface of the first stage, and the third stage The multi-stage capacitor structure according to claim 4, wherein an upper surface is higher than the second upper surface.   The multi-stage capacitor structure of claim 6, wherein the third stage is disposed at a distance next to the second stage.   The multi-stage capacitor structure according to claim 4, wherein the multi-stage further includes a third stage disposed on the second upper surface of the second stage.   The multistage capacitor structure according to claim 3, wherein a cross section of the upper conductive layer is reverse multistage.   10. The reverse multi-stage includes at least a first reverse stage having a first lower surface and a second reverse stage having a second lower surface that is lower than the first lower surface. Multi-stage capacitor structure.   The multistage capacitor structure according to claim 10, wherein the second lower surface is disposed to face the second upper surface.   The multistage capacitor structure according to claim 10, wherein the second lower surface is disposed at a position displaced with respect to the second upper surface.   The multi-stage capacitor structure according to claim 10, wherein a height of the second lower surface is lower than a height of the second upper surface.   The reverse multi-stage further includes a third reverse stage having a third lower surface, wherein the third reverse stage includes the second reverse stage on the lower surface of the first reverse stage. The multi-stage capacitor structure according to claim 10, wherein the multi-stage capacitor structure is disposed adjacent to each other, and the third lower surface is lower than the second lower surface.   11. The multi-stage capacitor structure according to claim 10, wherein the reverse multi-stage further includes a third reverse stage disposed on the second lower surface of the second reverse stage.   The multi-stage capacitor structure of claim 10, wherein the third reverse stage is disposed at a distance next to the second reverse stage.   The multi-stage capacitor structure according to claim 13, wherein the second reverse stage and the third reverse stage are disposed to face each other and complement each other.   The multi-stage according to claim 1, wherein the dielectric layer disposed between the upper conductive layer and the lower conductive layer has a plurality of regions or layers having various dielectric coefficients to form different capacitances. Capacitor structure. Forming a lower conductive layer having a first conductive layer and a second conductive layer and having a multi-stage cross section;
Providing an upper conductive layer and a first dielectric layer;
Combining the lower conductive layer, the first dielectric layer, and the upper conductive layer to obtain a multi-stage capacitor structure. Forming the lower conductive layer includes:
Providing the first conductive layer;
Forming a first barrier layer on the first conductive layer and patterning the first barrier layer;
Forming the second conductive layer on the first conductive layer;
20. The method includes at least removing the first barrier layer and combining the first conductive layer and a patterned second conductive layer to form the multi-stage lower conductive layer. The manufacturing method as described in. Forming the lower conductive layer includes:
Forming a second barrier layer on the first conductive layer and the second conductive layer, and patterning the second barrier layer;
Forming a third conductive layer on the second conductive layer;
Removing the second barrier layer and combining the first conductive layer, the second conductive layer, and the patterned third conductive layer to form the multi-stage lower conductive layer; and The manufacturing method according to claim 20, comprising at least.   The manufacturing method according to claim 20, wherein the barrier layer is formed on the conductive layer by press bounding or dipping.   The manufacturing method according to claim 19, wherein the multistage lower conductive layer is formed by printing.   The manufacturing method according to claim 19, wherein the multistage lower conductive layer is formed by coating.   The manufacturing method according to claim 19, wherein the multistage lower conductive layer is formed by injection.   The manufacturing method according to claim 19, wherein the multistage lower conductive layer is formed by sputtering.   The manufacturing method according to claim 19, wherein the multistage lower conductive layer is formed by calendering.   The manufacturing method according to claim 19, wherein the multi-stage lower conductive layer is formed by molding.   21. The first dielectric layer disposed between the upper conductive layer and the lower conductive layer has a plurality of regions or layers having different dielectric coefficients to form different capacitances. The manufacturing method as described. A substrate,
Comprising at least a multi-stage capacitor structure disposed on the substrate;
The multi-stage capacitor structure includes an upper conductive layer, an intermediate dielectric layer, and a lower conductive layer,
The substrate, wherein at least one of the upper conductive layer and the lower conductive layer has a multi-step cross section.   The substrate according to claim 30, wherein the lower conductive layer has a multi-stage cross section.   32. The substrate of claim 31, wherein the multi-stage includes at least a first stage having a first upper surface and a second stage having a second upper surface higher than the first upper surface.   The substrate of claim 32, wherein the second stage is disposed on the first stage.   34. The substrate of claim 33, wherein the second stage includes one or more groups disposed on the first stage at a distance next to each other.   The multi-stage further includes a third stage having a third upper surface, wherein the third stage is disposed adjacent to the second stage on the first upper surface of the first stage, and the third stage 34. The substrate of claim 33, wherein a top surface is higher than the second top surface.   36. The substrate of claim 35, wherein the third stage is disposed at a distance next to the second stage.   34. The substrate of claim 33, wherein the multi-stage further includes a third stage disposed on the second upper surface of the second stage.   The substrate according to claim 32, wherein the upper conductive layer has a reverse multi-stage cross section.   39. The reverse multi-stage includes at least a first reverse stage having a first lower surface and a second reverse stage having a second lower surface lower than the first lower surface. substrate.   40. The substrate of claim 39, wherein the second lower surface is disposed opposite the second upper surface.   40. The substrate of claim 39, wherein the second lower surface is disposed at a position displaced with respect to the second upper surface.   40. The substrate of claim 39, wherein a height of the second lower surface is lower than a height of the second upper surface.   The reverse multi-stage further includes a third reverse stage having a third lower surface, wherein the third reverse stage includes the second reverse stage on the lower surface of the first reverse stage. 40. The substrate of claim 39, wherein the substrate is disposed adjacently and the third lower surface is lower than the second lower surface.   40. The substrate of claim 39, wherein the reverse multi-stage further comprises a third reverse stage disposed on the second lower surface of the second reverse stage.   40. The substrate of claim 39, wherein the third reverse stage is disposed at a distance next to the second reverse stage.   43. The substrate of claim 42, wherein the second reverse stage and the third reverse stage are disposed opposite each other to complement each other's height.   32. The substrate of claim 30, wherein the dielectric layer disposed between the upper conductive layer and the lower conductive layer has a plurality of regions or layers having different dielectric coefficients to form different capacitances. .   32. The substrate of claim 30, further comprising a plurality of conductive vias each connected to the upper conductive layer and the lower conductive layer.   The substrate according to claim 30, wherein the upper conductive layer or the lower conductive layer is embedded in the substrate.   The substrate according to claim 30, wherein the upper conductive layer or the lower conductive layer is embedded in the substrate in the form of an entire layer.   The substrate according to claim 30, wherein the substrate is a silicon substrate, a chip carrier, a ceramic substrate, a glass substrate, a flexible substrate, or a printed circuit board.   32. The substrate of claim 30, wherein the substrate including the multi-stage conductive layer is incorporated into an integrated circuit package structure.   31. The substrate of claim 30, embedded in another substrate and connecting the another substrate to a multi-stage capacitor structure of the substrate.

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