JP2009147056A5 - - Google Patents
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- JP2009147056A5 JP2009147056A5 JP2007321779A JP2007321779A JP2009147056A5 JP 2009147056 A5 JP2009147056 A5 JP 2009147056A5 JP 2007321779 A JP2007321779 A JP 2007321779A JP 2007321779 A JP2007321779 A JP 2007321779A JP 2009147056 A5 JP2009147056 A5 JP 2009147056A5
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- JP
- Japan
- Prior art keywords
- mos transistor
- semiconductor layer
- forming
- semiconductor
- photodiode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 28
- 239000000758 substrate Substances 0.000 claims 5
- 238000005530 etching Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 3
- 238000000034 method Methods 0.000 claims 2
- 230000003287 optical effect Effects 0.000 claims 2
- 239000000969 carrier Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
Claims (6)
半導体基板に形成されたフォトダイオードと、
前記フォトダイオードのカソード上に絶縁膜を介して形成された半導体層と、
前記半導体層に形成された第1MOSトランジスタと、を一画素内に有し、
前記第1MOSトランジスタのソース又はドレインの一方は一の方向に向かって延びる電源線に接続され、前記第1MOSトランジスタのソース又はドレインの他方は前記一の方向に向かって延びる第1信号線に接続され、且つ、前記第1MOSトランジスタのゲート電極は前記一の方向と交差する他の方向に向かって延びる第2信号線に接続されていることを特徴とする半導体装置。 A semiconductor device comprising a plurality of pixels for converting an optical signal into an electrical signal,
A photodiode formed on a semiconductor substrate;
A semiconductor layer formed on the cathode of the photodiode via an insulating film;
A first MOS transistor formed in the semiconductor layer, in one pixel;
One of the source and drain of the first MOS transistor is connected to a power supply line extending in one direction, and the other of the source and drain of the first MOS transistor is connected to a first signal line extending in the one direction. The gate electrode of the first MOS transistor is connected to a second signal line extending in another direction intersecting the one direction.
前記第2MOSトランジスタのソース又はドレインの一方は前記カソードに接続され、前記第2MOSトランジスタのソース又はドレインの他方は前記電源線に接続され、且つ、前記第2MOSトランジスタのゲート電極は前記他の方向に向かって延びる第3信号線に接続されていることを特徴とする請求項1に記載の半導体装置。 A second MOS transistor formed on the semiconductor substrate is included in the one pixel,
One of the source and drain of the second MOS transistor is connected to the cathode, the other of the source and drain of the second MOS transistor is connected to the power supply line, and the gate electrode of the second MOS transistor is in the other direction. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a third signal line extending toward the first side.
前記画素となる領域の半導体基板にフォトダイオードを形成する工程と、
前記フォトダイオードのカソード上に第1半導体層を形成する工程と、
前記第1半導体層上に第2半導体層を形成する工程と、
前記第2半導体層及び前記第1半導体層をエッチングして、前記第2半導体層及び前記第1半導体層を貫く第1溝を形成する工程と、
前記第1溝に支持体を形成する工程と、
前記第2半導体層をエッチングして、前記第1半導体層を露出させる第2溝を形成する工程と、
前記第2溝を介して前記第1半導体層をエッチングすることにより、前記第2半導体層と前記カソードとの間に空洞部を形成する工程と、
前記空洞部内に絶縁膜を形成して埋め込む工程と、
前記第2半導体層に第1MOSトランジスタを形成する工程と、を含むことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device comprising a plurality of pixels for converting an optical signal into an electrical signal,
Forming a photodiode on a semiconductor substrate in a region to be the pixel;
Forming a first semiconductor layer on a cathode of the photodiode;
Forming a second semiconductor layer on the first semiconductor layer;
Etching the second semiconductor layer and the first semiconductor layer to form a first groove penetrating the second semiconductor layer and the first semiconductor layer;
Forming a support in the first groove;
Etching the second semiconductor layer to form a second groove exposing the first semiconductor layer;
Forming a cavity between the second semiconductor layer and the cathode by etching the first semiconductor layer through the second groove;
Forming and filling an insulating film in the cavity,
Forming a first MOS transistor in the second semiconductor layer. A method for manufacturing a semiconductor device, comprising:
前記第2MOSトランジスタを形成する工程では、当該第2MOSトランジスタのソース又はドレインの一方を前記カソードの一部と重なるように形成することを特徴とする請求項3に記載の半導体装置の製造方法。 Forming a second MOS transistor on the semiconductor substrate in the region to be the pixel,
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the second MOS transistor, one of a source and a drain of the second MOS transistor is formed so as to overlap a part of the cathode.
前記フォトダイオードの上に絶縁膜を介して配置された半導体層を含む第1MOSトランジスタと、を含み、A first MOS transistor including a semiconductor layer disposed on the photodiode via an insulating film,
前記フォトダイオードが発生するキャリアにより前記第1MOSトランジスタの閾値が制御されることを特徴とする半導体装置。A semiconductor device, wherein a threshold value of the first MOS transistor is controlled by carriers generated by the photodiode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007321779A JP2009147056A (en) | 2007-12-13 | 2007-12-13 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007321779A JP2009147056A (en) | 2007-12-13 | 2007-12-13 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009147056A JP2009147056A (en) | 2009-07-02 |
JP2009147056A5 true JP2009147056A5 (en) | 2010-07-08 |
Family
ID=40917347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007321779A Withdrawn JP2009147056A (en) | 2007-12-13 | 2007-12-13 | Semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
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JP (1) | JP2009147056A (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101830196B1 (en) * | 2010-02-12 | 2018-02-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and driving method thereof |
DE102013110695A1 (en) | 2012-10-02 | 2014-04-03 | Samsung Electronics Co., Ltd. | Image sensor, method for operating the same and image processing system with the same |
KR20140047494A (en) | 2012-10-12 | 2014-04-22 | 삼성전자주식회사 | Subpixel, image sensor having the same and image sensing system |
JP2015023192A (en) * | 2013-07-19 | 2015-02-02 | 日本放送協会 | Solid state image sensor |
JP2015162604A (en) | 2014-02-27 | 2015-09-07 | 株式会社東芝 | CMOS image sensor |
JP6892577B2 (en) | 2017-04-28 | 2021-06-23 | 天馬微電子有限公司 | Image sensor and sensor device |
CN111063702B (en) * | 2019-11-13 | 2022-10-04 | 北京大学 | UTBB photoelectric detector pixel unit, UTBB photoelectric detector pixel array and UTBB photoelectric detector pixel method |
-
2007
- 2007-12-13 JP JP2007321779A patent/JP2009147056A/en not_active Withdrawn
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