JP2009147020A - Multilayer circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a multilayer circuit board which aligns an upper layer with a lower layer without requiring transparency of a material for forming a layer. <P>SOLUTION: In a method for producing a multilayer circuit board, a product substrate 10 having an alignment mark 14 on the surface, and a substrate 100 only for alignment having an alignment mark which is in mirror image relation with the alignment mark 14 on the surface are prepared, an alignment mark of the substrate only for product is imaged by means of a first camera K1, an alignment mark of the substrate only for alignment is imaged by means of a second camera K2, and based on a composite image of an alignment mark image of a substrate for product and an alignment mark image of a substrate only for alignment, the substrate for product and the substrate only for alignment are aligned and stuck back to back, and in a process for forming a multilayer wiring structure, a lower layer pattern formed already is aligned with an upper layer pattern to be formed anew thereon by using the alignment mark of the substrate only for alignment. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer circuit board, and more particularly, to a method for manufacturing a multilayer circuit board in which an alignment method between layers constituting a multilayer wiring structure is improved.

  A manufacturing method of a multilayer circuit board including a multilayer wiring structure in which wiring layers and insulating layers are alternately laminated on the surface of a product substrate has been performed. At that time, in order to align (align) the upper layer pattern newly formed on the already formed lower layer pattern with high accuracy, image recognition of the alignment mark on the lower layer pattern side or an arbitrary pattern is performed. Alignment is performed. When conducting conduction between layers, insulation between various circuits, impurity implantation, formation of metal wiring, and the like, if the alignment is not accurately performed with respect to the lower layer, circuit conduction failure, circuit short circuit, and circuit malfunction will occur.

  Conventionally, high-precision alignment of the upper layer pattern with respect to the lower layer pattern has been performed by directly recognizing the lower layer image. Therefore, since it is necessary that the lower layer pattern is visible through the upper layer pattern, materials used for forming various layers such as an interlayer insulating film, a metal film for wiring, and a photosensitive resin for element isolation are limited to transparent materials. It was.

  Therefore, there is a problem that non-transparent materials cannot be used even if there are other optimum materials in terms of process and material characteristics.

  A specific example of the conventional method will be described with reference to FIGS. In each figure, (A) is a cross-sectional view taken along line AA in (B) (shown only in FIGS. 1 (1) and (B) for the sake of brevity), and (B) is an external view seen from above the substrate. It is a figure and shows a shape that can be actually visually recognized (the transparent layer contour appearing in the substrate region is not shown except for the part marked with a reference number).

  In FIG. 1A, connection pads 12 and a device pattern 14 are formed on the surface of a product substrate 10. When a wiring pattern is further formed thereon, for example, the device pattern 14 is used as an alignment mark.

  In FIG. 1 (2), a transparent photosensitive insulating resin layer 16 is formed on the entire surface of the substrate 10. As shown in (A), since the photosensitive insulating resin layer 16 covers the entire surface of the substrate 10 but is transparent, the alignment mark (device pattern) 14 is visible through the resin layer 16 as shown in (B). it can.

  In FIG. 1C, the resin layer 16 is patterned into a shape that defines the wiring pattern to be formed. At that time, the alignment mark 14 is visually recognized through the transparent resin layer 16 (imaged by a camera (not shown)), and a pattern mask (not shown) is aligned and exposed above the substrate 10 with reference to this, and then developed. Thus, the resin pattern 16P is formed. In this state, all the patterns 12, 14, 16P on the substrate 10 can be visually recognized.

  2A, a copper thin film 18 as an electroplating seed layer is formed on the entire surface of the substrate 10 by electroless plating as shown in FIG. Although the copper thin film 18 is opaque, it is extremely thin (several μm or less) compared to the size (several tens of μm to several hundreds of μm) of the patterns 12, 14, and 16P. The outer shape is maintained simply by being covered with the thin copper thin film 18 and is substantially visible as shown in FIG.

  In FIG. 2 (2), a transparent dry film resist 20 is laminated on the entire surface of the substrate 10 covered with the copper thin film 18. As shown in (A), the dry film resist 20 covers the entire surface of the substrate 10 but is transparent, so that the alignment mark (device pattern) 14 can be seen through the dry film resist 20 as shown in (B).

  In FIG. 2C, the dry film resist 20 is patterned into a shape that defines the wiring pattern to be formed. At that time, the alignment mark 14 is visually recognized through the transparent dry film resist 20 (imaged by a camera not shown), and a pattern mask (not shown) is aligned and exposed above the substrate 10 on the basis of this, and then exposed. Development is performed to form a dry film resist pattern 20P. In this state, all the patterns 12, 14, 16P, and 20P on the substrate 10 are visible.

  In FIG. 3A, by performing electrolytic copper plating on the entire surface of the substrate 10, a copper wiring pattern 22 is formed on the copper seed layer 18 in the opening of the dry film resist pattern 20P.

  In FIG. 3B, the dry film resist pattern 20P is removed, and thereby the copper seed layer 18 exposed in the region where the copper wiring pattern 22 is not formed is removed by flash etching. As a result, the wiring pattern 22 is formed on the substrate 10 as an upper layer of the connection pads 12 and the device pattern 14 that have already been formed, and one stage in the manufacturing process of the multilayer circuit board is completed.

  As described above with reference to FIGS. 1 to 3, in order to form a new upper layer on the already formed lower layer, the steps of FIG. 1 (2) and FIG. 2 (2) are performed. In order to make it possible to visually recognize the alignment mark 14 serving as a reference, the photosensitive insulating resin layer 16 and the dry film resist 20 provided in the previous steps of these two steps should be transparent. Limited.

  An object of the present invention is to provide a method of manufacturing a multilayer circuit board that solves the above-described conventional problems and enables alignment of the upper layer with respect to the lower layer without requiring transparency of the layer forming material.

In order to achieve the above object, according to the present invention, in a method of manufacturing a multilayer circuit board including a multilayer wiring structure in which wiring layers and insulating layers are alternately laminated on the surface of a product substrate,
A step of preparing the product substrate having an alignment mark on the surface;
Preparing an alignment-dedicated substrate having an alignment mark arranged on the surface with respect to the alignment mark on the surface of the product substrate;
Imaging the alignment mark on the product substrate with a first camera;
Imaging the alignment mark on the alignment substrate with a second camera;
Based on a composite image of the alignment mark image of the product substrate by the first camera and the alignment mark image of the alignment dedicated substrate by the second camera, the product substrate and the alignment dedicated substrate are aligned and the back surfaces are aligned. In the formation process of the multilayer wiring structure, the alignment between the already formed lower layer pattern and the upper layer pattern newly formed on the lower layer pattern is performed using the alignment mark on the alignment dedicated substrate. The manufacturing method of the multilayer circuit board characterized by including the process to perform is provided.

  Since the present invention performs alignment of the upper layer pattern with respect to the lower layer pattern using the alignment mark of the alignment dedicated substrate that is aligned and bonded to the product substrate, it is necessary to visually recognize the lower layer pattern through the upper layer pattern. Therefore, a multilayer circuit board can be manufactured without the restriction that the material of the upper layer pattern is transparent.

  As the alignment-dedicated substrate of the present invention, in addition to the silicon substrate, a highly rigid material such as a quartz glass substrate or a ceramic substrate can be used according to the use environment, and a flexible material such as a metal material such as titanium or aluminum can be used. Various materials can also be used.

  An adhesive is used to attach the alignment-dedicated substrate to the product substrate. In particular, when an adhesive that can be peeled off after use is used, the cost can be suppressed by reusing the alignment-dedicated substrate. As such an adhesive, a liquid or film adhesive is applied or laminated on the bonding surface. When the substrates are bonded together in the state of being applied or laminated, the substrates can be fixed with sufficient adhesive force. In a state where both substrates are bonded, various layers are formed on the product substrate while aligning with alignment marks on the alignment dedicated substrate to complete a final multilayer circuit substrate.

  Thereafter, the alignment dedicated substrate is peeled off from the product substrate as necessary. Adhesives include a type that dissolves in water or a solution, a type that peels off by ultraviolet irradiation, a type that peels off by heating, and the like.

  A specific example of manufacturing a multilayer circuit board including a multilayer wiring structure in which wiring layers and insulating layers are alternately laminated on the surface of a product substrate by the method of the present invention will be described.

  First, FIG. 4A shows (A) a product substrate 10 to which the present invention is applied, and (B) an alignment dedicated substrate 100 which is an important feature in the method of the present invention.

  The product substrate 10 is typically a silicon wafer, on which patterns 11 and 14 such as various devices are formed. Of these, the pattern 14 that is easy to recognize is selected as an alignment mark. If the alignment mark 14 is used at three or more places as shown in the drawing, high-precision alignment can be easily performed. In addition to the device pattern, the alignment mark 14 having a size of about several hundred μm, such as a user company name and a logo mark, is appropriate. When an appropriate pattern as an alignment mark is not found on the target product substrate 10, an appropriate pattern can be written in an empty area other than the dicing line by laser processing or lithography.

  The alignment dedicated substrate 100 is typically a silicon wafer, and an alignment mark 102 is formed on the surface thereof. The alignment mark 102 of the alignment dedicated substrate 100 is formed by a laser marking device or the like at a mirror image-related position with respect to the alignment mark 14 of the product substrate 10. The shape of the alignment mark 102 of the alignment dedicated substrate 100 is preferably a shape that fits with the alignment mark 14 of the product substrate 10. In the illustrated example, the alignment mark 14 of the product substrate 10 has a cross shape, and four squares are arranged in a square shape so as to be in a fitting relationship therewith.

  FIG. 4 (2) shows (A) a cross-sectional view in which the product substrate 10 and the alignment dedicated substrate 100 are arranged back to back, and (B) an arrangement view of the surface of the substrate 10 and the substrate 100. Show about. The cross section of the product substrate 10 shown in FIGS. 4 (2) (A) is a cross sectional view taken along the polygonal line AA of the surface layout shown in FIGS. 4 (2) (B). ) (A) is a cross-sectional view of the alignment mark dedicated substrate 100 shown in FIG. 4 (2) (B) is a cross-sectional view taken along line AA of the surface layout.

  As shown in FIGS. 4 (2) (A), the product substrate 10 and the alignment dedicated substrate 100 are bonded to each other with the back surfaces 10B and 100B. As described above, various adhesives can be used for this purpose. When the alignment dedicated substrate 100 is peeled off from the product substrate 10 after use, the above-described various types of peelable adhesives are used.

  In the bonding, the alignment mark 14 on the surface 10S of the product substrate 10 is imaged by the first camera K1, while the alignment mark 102 on the surface 100S of the dedicated alignment substrate 100 is imaged by the second camera. Based on the synthesized data, the substrate 10 and the substrate 100 are aligned.

  FIG. 4 (3) schematically shows a form in which the captured alignment mark images are combined. An image of the alignment mark 14 on the product substrate 10 by the first camera K1 (the left end in the figure) and an image of the alignment mark 102 on the alignment dedicated substrate 100 by the second camera K2 (the center in the figure) are combined to form a composite image ( On the right edge of the figure).

  The alignment between the substrate 10 and the substrate 100 is performed by the alignment of the U-shaped alignment mark 102 of the alignment dedicated substrate 100 facing each of the two corners of the four corners of the cross-shaped alignment mark 14 of the product substrate 10. This is done by relatively positioning the substrate 10 and the substrate 100 so that the intervals G between the two sides of the four squares are equal.

  In this way, the product substrate 10 and the alignment dedicated substrate 100 are bonded together in the process stage where the alignment mark 14 of the product substrate 10 is visible. In the process stage after bonding, alignment can be performed using the alignment mark 102 of the alignment dedicated substrate 100. Therefore, the layer to be newly formed on the product substrate 10 does not need to be transparent as in the prior art, and is not limited by transparency, and is made of an optimum material from the viewpoint of process and / or layer characteristics. Can be selected.

  A semiconductor wafer bonding apparatus can be used as an apparatus for aligning and bonding the product substrate 10 and the alignment dedicated substrate 100. Specific examples include EVG6200INFINITY (manufactured by EVG).

  A specific example of a process for manufacturing a multilayer circuit board by applying the method of the present invention will be described with reference to FIGS. In each figure, (A) is a cross-sectional view at the same position as in FIG. 4 (2), and (B) is an external view seen from above the substrate and shows a shape that can actually be seen.

  In FIG. 5A, the device pattern 14, the connection pad 12, and the wiring pattern 24 are formed on the surface of the product substrate 10, and these are embedded in the insulating resin layer 26. A copper thin film 28 is formed. In this state, at least the copper thin film 28 is opaque, and as viewed from the surface side of the substrate 10, the surface of the copper thin film 28 can only be visually recognized as shown in FIG. 24 are blocked by an opaque copper thin film 28 (or further an insulating resin layer 26) and cannot be visually recognized.

  On the back surface of the product substrate 10, the alignment dedicated substrate 100 is bonded to the back surface by the method described with reference to FIG. 4.

  In FIG. 5 (2), a dry film resist 30 is laminated on the entire surface of the copper thin film 28. As shown in (B), the appearance from above is such that only the surface of the dry film resist 30 can be visually recognized, and any of the underlying patterns cannot be visually recognized.

  In FIG. 5 (3), the pattern mask M is aligned by collating the image of the alignment mark 102 of the alignment dedicated substrate 100 by the second camera with the image of the pattern mask M by the first camera. This is done by the method described with reference to FIGS. 4 (1) and (2).

  In FIG. 6A, the dry film resist 30 is exposed through the pattern mask M aligned as described above, and then developed to form an opening 31 in the dry film resist 30 where the wiring pattern is to be formed. A pattern 30P is formed. In the appearance from above, the lower copper thin film 28 is exposed and visible in the opening 31 of the resist pattern 30P as shown in FIG.

  In FIG. 6B, electrolytic copper plating is performed to form a copper wiring pattern 32 on the copper thin film 28 exposed in the opening 31 of the resist pattern 30P. In the external appearance from above, the copper wiring pattern 32 can be visually recognized in the opening 31 of the resist pattern 30P as shown in FIG.

  In FIG. 6 (3), the dry film resist pattern 30P is removed, and thereby the copper thin film 28 exposed in the region where the copper wiring pattern 32 is not formed is removed by flash etching. As a result, the wiring pattern 32 is formed on the substrate 10 as an upper layer of the connection pads 12 and the device pattern 14 that have already been formed, and one stage in the manufacturing process of the multilayer circuit board is completed.

  In order to simplify the illustration, the wiring pattern 32 is shown only on the connection pad 12, but in actuality, it is variously arranged with a necessary planar extent.

  If it is not necessary to use the alignment dedicated substrate 100 in the subsequent process steps, the alignment dedicated substrate 100 is peeled from the product substrate 10 as shown in FIG.

  Thereby, the multilayer circuit board 150 is finally completed.

  The present invention provides a method for manufacturing a multilayer circuit board that enables alignment of the upper layer with respect to the lower layer without requiring that the layer forming material be transparent as in the prior art.

(A) Sectional drawing which shows the process of manufacturing a multilayer circuit board by the conventional method, and (B) The external view from upper direction. FIG. 2A is a cross-sectional view and FIG. 2B is an external view showing the next step of FIG. 1 in which a multilayer circuit board is manufactured by a conventional method. FIG. 3A is a sectional view and FIG. 3B is an external view showing the next step of FIG. 2 in which a multilayer circuit board is manufactured by a conventional method. A procedure for preparing and applying an alignment-dedicated substrate by the method of the present invention will be described. FIG. 4A is a cross-sectional view illustrating a process of manufacturing a multilayer circuit board by the method of the present invention, and FIG. FIG. 6A is a cross-sectional view and FIG. 5B is an external view showing the next step of FIG. 5 in which a multilayer circuit board is manufactured by the method of the present invention. FIG. 7A is a sectional view and FIG. 7B is an external view showing the next step of FIG. 6 in which a multilayer circuit board is manufactured by the method of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Product substrate 14 Alignment mark of product substrate 10 100 Dedicated alignment substrate 102 Alignment mark of alignment exclusive substrate 100 150 Multilayer circuit board K1 1st camera K2 2nd camera

Claims (2)

In a method for manufacturing a multilayer circuit board including a multilayer wiring structure in which wiring layers and insulating layers are alternately laminated on the surface of a product substrate,
A step of preparing the product substrate having an alignment mark on the surface;
Preparing an alignment-dedicated substrate having an alignment mark arranged on the surface with respect to the alignment mark on the surface of the product substrate;
Imaging the alignment mark on the product substrate with a first camera;
Imaging the alignment mark on the alignment substrate with a second camera;
Based on a composite image of the alignment mark image of the product substrate by the first camera and the alignment mark image of the alignment dedicated substrate by the second camera, the product substrate and the alignment dedicated substrate are aligned and the back surfaces are aligned. In the formation process of the multilayer wiring structure, the alignment between the already formed lower layer pattern and the upper layer pattern newly formed on the lower layer pattern is performed using the alignment mark on the alignment dedicated substrate. The manufacturing method of the multilayer circuit board characterized by including the process to perform.   2. The method for manufacturing a multilayer circuit board according to claim 1, further comprising a step of peeling off the alignment substrate after use from the product substrate.

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