JP2009146923A - Method of manufacturing compound semiconductor device - Google Patents

Method of manufacturing compound semiconductor device Download PDF

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JP2009146923A
JP2009146923A JP2007319376A JP2007319376A JP2009146923A JP 2009146923 A JP2009146923 A JP 2009146923A JP 2007319376 A JP2007319376 A JP 2007319376A JP 2007319376 A JP2007319376 A JP 2007319376A JP 2009146923 A JP2009146923 A JP 2009146923A
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main surface
compound semiconductor
substrate
integrated circuit
semiconductor substrate
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Kazumi Nishimura
一巳 西村
Suehiro Sugitani
末広 杉谷
Kiyomitsu Onodera
清光 小野寺
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Nippon Telegraph and Telephone Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a compound semiconductor device for covering the entire chip excluding its back with a passivation film and easily handling a substrate. <P>SOLUTION: The manufacturing method includes: a cutting formation process for forming a cutting 3 having scheduled depth at a part where no integrated circuits are manufactured on a first main surface of a semiconductor substrate 1, namely a compound semiconductor substrate, having a region 2 including an integrated circuit on the first main surface by dicing; a passivation film deposition process for depositing a passivation film 4 on the first main surface including the surface of the cutting 3; and a polishing process for polishing the second main surface of the semiconductor substrate 1 until the thickness of the semiconductor substrate 1 becomes equal to scheduled depth after the passivation film deposition process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は化合物半導体装置の製造方法に係る。   The present invention relates to a method for manufacturing a compound semiconductor device.

従来技術においては、下記特許文献１に記載されているように、複数の半導体装置が形成されている化合物半導体基板を、各半導体装置毎のチップに分離する場合、半導体装置の表面を保護することなく、基板を切断している。したがって、薄膜化したチップを得る場合、基板を研磨して薄膜化した後、切断する。このため、裏面を除くチップ全体をパッシベーション膜で覆うことが困難であり、さらに、基板強度が弱いため、基板の取扱が困難である。特に化合物半導体基板の場合には、基板の強度が小さいので、特に大きな基板の取扱が困難である。さらに、半導体基板上に形成された強度の小さいものを損傷することなく、薄膜化した基板を分離することも困難である。
特開２００５−１９１２３２号公報 In the prior art, as described in Patent Document 1 below, when a compound semiconductor substrate on which a plurality of semiconductor devices are formed is separated into chips for each semiconductor device, the surface of the semiconductor device is protected. Without cutting the substrate. Therefore, when obtaining a thinned chip, the substrate is polished and thinned, and then cut. For this reason, it is difficult to cover the entire chip except the back surface with a passivation film, and furthermore, the substrate is difficult to handle because the substrate strength is weak. In particular, in the case of a compound semiconductor substrate, since the strength of the substrate is small, it is difficult to handle a particularly large substrate. Furthermore, it is difficult to separate the thinned substrate without damaging the low-strength one formed on the semiconductor substrate.
JP 2005-191232 A

本発明は、薄膜化したチップを得る場合における、上記の、裏面を除くチップ全体をパッシベーション膜で覆うことが困難であり、基板の取扱が困難であるという問題に鑑みてなされたものであり、本発明が解決しようとする課題は、裏面を除くチップ全体をパッシベーション膜で覆うことを可能とし、基板の取扱が容易な化合物半導体装置の製造方法を提供することである。   In the case of obtaining a thinned chip, the present invention is made in view of the problem that it is difficult to cover the entire chip except the back surface with a passivation film, and it is difficult to handle the substrate. The problem to be solved by the present invention is to provide a method of manufacturing a compound semiconductor device that makes it possible to cover the entire chip except the back surface with a passivation film and to handle the substrate easily.

本発明においては、上記課題を解決するために、請求項１に記載のように、
化合物半導体基板の集積回路が製作されている側の主面を第１の主面とし、他の側の主面を第２の主面としたとき、前記第１の主面に、予定された深さの切り込みを形成する切り込み形成工程と、前記切り込みの表面を含む前記第１の主面上にパッシベーション膜を堆積するパッシベーション膜堆積工程と、前記パッシベーション膜堆積工程の後に、前記化合物半導体基板の厚さが予定された厚さになるまで前記第２の主面を研磨する研磨工程とを有することを特徴とする化合物半導体装置の製造方法を構成する。 In the present invention, in order to solve the above problem, as described in claim 1,
When the main surface on the side where the integrated circuit of the compound semiconductor substrate is manufactured is the first main surface and the main surface on the other side is the second main surface, the first main surface is scheduled. A notch forming step for forming a depth incision, a passivation film deposition step for depositing a passivation film on the first main surface including the surface of the notch, and after the passivation film deposition step, And a polishing step of polishing the second main surface until the thickness reaches a predetermined thickness.

また、本発明においては、請求項２に記載のように、
請求項１に記載の化合物半導体装置の製造方法において、前記切り込み形成工程の前に、前記集積回路を分離する工程を有することを特徴とする化合物半導体装置の製造方法を構成する。 In the present invention, as described in claim 2,
2. The method of manufacturing a compound semiconductor device according to claim 1, further comprising a step of separating the integrated circuit before the notch forming step.

また、本発明においては、請求項３に記載のように、
化合物半導体基板の、集積回路が製作されている側の主面を第１の主面とし、他の側の主面を第２の主面としたとき、
前記第１の主面上に保護膜を堆積する保護膜堆積工程と、
前記保護膜堆積工程の後に、前記第１の主面に予定された深さの切り込みを形成する切り込み形成工程と、前記切り込み形成工程の後に、前記化合物半導体基板の厚さが予定された厚さになるまで前記第２の主面を研磨する研磨工程とを有することを特徴とする化合物半導体装置の製造方法を構成する。 In the present invention, as described in claim 3,
When the main surface of the compound semiconductor substrate on which the integrated circuit is manufactured is the first main surface, and the main surface on the other side is the second main surface,
A protective film deposition step of depositing a protective film on the first main surface;
After the protective film deposition step, a notch forming step for forming a notch having a predetermined depth in the first main surface, and after the notch forming step, the thickness of the compound semiconductor substrate is expected. And a polishing step of polishing the second main surface until the step becomes, a manufacturing method of a compound semiconductor device is provided.

また、本発明においては、請求項４に記載のように、
請求項３に記載の化合物半導体装置の製造方法において、前記保護膜堆積工程と前記切り込み形成工程との間に、前記集積回路を分離する工程を有することを特徴とする化合物半導体装置の製造方法を構成する。 In the present invention, as described in claim 4,
4. The method of manufacturing a compound semiconductor device according to claim 3, further comprising a step of separating the integrated circuit between the protective film deposition step and the notch formation step. Constitute.

また、本発明においては、請求項５に記載のように、請求項１、２、３または４に記載の化合物半導体装置の製造方法において、前記予定された深さが前記予定された厚さに等しいことを特徴とする化合物半導体装置の製造方法を構成する。   According to the present invention, as described in claim 5, in the method for manufacturing a compound semiconductor device according to claim 1, 2, 3 or 4, the predetermined depth is set to the predetermined thickness. The manufacturing method of the compound semiconductor device is characterized by being equal.

また、本発明においては、請求項６に記載のように、請求項１、２、３または４に記載の化合物半導体装置の製造方法において、前記予定された深さが前記予定された厚さよりも小であることを特徴とする化合物半導体装置の製造方法を構成する。   Further, in the present invention, as described in claim 6, in the method for manufacturing a compound semiconductor device according to claim 1, 2, 3 or 4, the predetermined depth is larger than the predetermined thickness. The manufacturing method of the compound semiconductor device is characterized by being small.

本発明の実施によって、裏面を除くチップ全体をパッシベーション膜で覆うことが可能となり、半導体基板の取扱が容易となり、半導体基板上に形成された強度の小さいものを損傷することなく基板を分離することが可能となる。   By implementing the present invention, it becomes possible to cover the entire chip except for the back surface with a passivation film, facilitating the handling of the semiconductor substrate, and separating the substrate without damaging the low-strength one formed on the semiconductor substrate. Is possible.

その結果として、化合物半導体装置の耐湿性の向上、モジュール組み立て歩留まりの向上、モジュール組み立てコストの低減、ミリ波帯（３０〜３００ＧＨｚ）まで動作する高周波集積回路モジュールの高性能化、パワー密度の高いトランジスターの高性能化が実現する。   As a result, the moisture resistance of the compound semiconductor device is improved, the module assembly yield is improved, the module assembly cost is reduced, the performance of the high-frequency integrated circuit module operating up to the millimeter wave band (30 to 300 GHz), and the transistor with high power density are increased. High performance is realized.

本発明に係る化合物半導体装置の製造方法においては、第１の実施の形態として、集積回路が製作されている化合物半導体基板に対して、該集積回路が形成されている半導体基板表面（第１の主面とする）の切断したい箇所に、ダイシングにより、予定された深さまで、切り込みを入れ、次に、該切り込みの表面を含む半導体基板表面にパッシベーション膜を堆積した後、半導体基板裏面（第２の主面）から基板を研磨し、予定された厚さまで、基板を薄膜化する。   In the method for manufacturing a compound semiconductor device according to the present invention, as a first embodiment, a surface of a semiconductor substrate on which an integrated circuit is formed (first surface) A portion of the main surface) to be cut is cut to a predetermined depth by dicing, and then a passivation film is deposited on the surface of the semiconductor substrate including the surface of the cut, and then the back surface of the semiconductor substrate (second surface). The main surface) is polished, and the substrate is thinned to a predetermined thickness.

また、本発明に係る化合物半導体装置の製造方法においては、第２の実施の形態として、集積回路が製作されている化合物半導体基板に対して、該集積回路が形成されている半導体基板表面（第１の主面とする）に保護膜を堆積し、次に半導体基板表面から、切断したい箇所の半導体基板に、ダイシングにより、予定された深さまで、切り込みを入れ、次に半導体基板裏面（第２の主面）から基板を研磨し、予定された厚さまで、基板を薄膜化する。この場合に、切り込みを入れる工程と基板を薄膜化する工程との間に、保護膜を除去する工程と、その工程の後に上記のパッシベーション膜を堆積する工程とを挿入してもよい。   Moreover, in the method for manufacturing a compound semiconductor device according to the present invention, as a second embodiment, the surface of the semiconductor substrate on which the integrated circuit is formed (first step) with respect to the compound semiconductor substrate on which the integrated circuit is manufactured. A protective film is deposited on the main surface of the semiconductor substrate 1, and then the semiconductor substrate is cut from the surface of the semiconductor substrate to a predetermined depth by dicing, and then the back surface of the semiconductor substrate (second surface). The main surface) is polished, and the substrate is thinned to a predetermined thickness. In this case, a step of removing the protective film and a step of depositing the passivation film after the step may be inserted between the step of cutting and the step of thinning the substrate.

前記予定された深さが前記予定された厚さに等しければ、半導体基板裏面の研磨によって、半導体基板は、予定された厚さにまで研磨された時点で、集積回路毎のチップに分離される。   If the predetermined depth is equal to the predetermined thickness, the semiconductor substrate is separated into chips for each integrated circuit when the semiconductor substrate is polished to the predetermined thickness by polishing the back surface of the semiconductor substrate. .

前記予定された深さが前記予定された厚さよりも小である場合でも、切り込み底部の半導体基板は、他の部位の基板よりも薄くなっているので、研磨工程後は、容易にへき開し、その結果として、半導体基板は集積回路毎のチップに分離される。   Even when the planned depth is smaller than the planned thickness, the semiconductor substrate at the bottom of the cut is thinner than the substrate at the other part, so that after the polishing process, it is easily cleaved, As a result, the semiconductor substrate is separated into chips for each integrated circuit.

本発明に係る化合物半導体装置の製造方法における上記第１の実施の形態の製作フローの断面模式図を図１に示す。   FIG. 1 shows a schematic cross-sectional view of the manufacturing flow of the first embodiment in the method for manufacturing a compound semiconductor device according to the present invention.

図１の（ａ）は、化合物半導体基板である半導体基板１の１つの主面（これを第１の主面とする）に、集積回路を含む領域２が存在する状態を示す断面図である。図において、集積回路を含む領域２は、縦の破線で３つの部分領域に区別され、各部分領域には１つの集積回路が製作されているものとする。   FIG. 1A is a cross-sectional view showing a state in which a region 2 including an integrated circuit exists on one main surface (this is referred to as a first main surface) of a semiconductor substrate 1 which is a compound semiconductor substrate. . In the figure, a region 2 including an integrated circuit is divided into three partial regions by vertical broken lines, and one integrated circuit is manufactured in each partial region.

図１の（ｂ）は、図１の（ａ）に示した状態にある半導体基板１の第１の主面の、集積回路が製作されていない部位に、ダイシングによって、予定された深さの切り込み３を形成する切り込み形成工程後の状態を示す断面図である。ここで、上記の「予定された深さ」は、下記の「予定された厚さ」に等しいものとする。なお、切り込み形成工程の前に、あらかじめ集積回路を分離する工程を設け、その工程によって、切り込み形成前に、各集積回路を、ダイシングまたはエッチングによって、分離しておいてもよい（図示せず）。この際に、ウエットエッチングによる分離を行えば、格子欠陥を伴わない分離が可能である。さらに、強度の小さい形成物を保護するため、あるいは、ダイシング時の切削水、切削で生じる微粒子等から集積回路を保護するため、図２の（ｂ）に示したように、第１の主面に保護膜５を堆積した後、上記切り込み形成工程を行って図２の（ｃ）に示した状態とし、その後に保護膜５を除去して、図１の（ｂ）の状態としてもよい。   FIG. 1B shows a predetermined depth of the first main surface of the semiconductor substrate 1 in the state shown in FIG. It is sectional drawing which shows the state after the notch formation process which forms the notch. Here, the “scheduled depth” is equal to the “scheduled thickness” described below. Note that a step of separating the integrated circuit in advance may be provided before the notch forming step, and the integrated circuit may be separated by dicing or etching before the notch formation by that step (not shown). . At this time, if separation by wet etching is performed, separation without lattice defects is possible. Further, as shown in FIG. 2 (b), the first main surface is used to protect the formed product having a low strength or to protect the integrated circuit from cutting water during dicing, fine particles generated by cutting, and the like. After the protective film 5 is deposited, the above-described cut forming process is performed to obtain the state shown in FIG. 2C, and then the protective film 5 is removed to obtain the state shown in FIG.

図１の（ｃ）は、切り込み３の表面を含む第１の主面上にパッシベーション膜４を堆積するパッシベーション膜堆積工程後の状態を示す断面図である。このようにして、パッシベーション膜４を堆積すると、製作した集積回路を（集積回路の性能劣化に無関係な裏面すなわち第２の主面を除く）基板１ごと完全に覆うことができる。ここまでの工程では、基板厚さが十分厚いままなので、基板に十分な強度があるため、基板の取扱が容易である。   FIG. 1C is a cross-sectional view showing a state after the passivation film deposition step for depositing the passivation film 4 on the first main surface including the surface of the notch 3. When the passivation film 4 is deposited in this way, the manufactured integrated circuit can be completely covered with the substrate 1 (excluding the back surface, that is, the second main surface, which is irrelevant to the performance degradation of the integrated circuit). In the process so far, the substrate thickness remains sufficiently thick, and the substrate has sufficient strength, so that the substrate can be handled easily.

図１の（ｄ）は、パッシベーション膜堆積工程の後に、半導体基板１の厚さが予定された厚さになるまで半導体基板１の第２の主面を研磨する研磨工程後の状態を示す断面図である。「予定された深さ」が「予定された厚さ」に等しいので、この研磨工程によって、半導体基板１は集積回路毎のチップに分離される。ここで、半導体基板１が小さく分離されるので、基板厚さが薄くても、その取扱が容易である。   FIG. 1D is a cross-sectional view showing a state after the polishing step of polishing the second main surface of the semiconductor substrate 1 until the thickness of the semiconductor substrate 1 reaches a predetermined thickness after the passivation film deposition step. FIG. Since the “scheduled depth” is equal to the “scheduled thickness”, the semiconductor substrate 1 is separated into chips for each integrated circuit by this polishing process. Here, since the semiconductor substrate 1 is separated into small pieces, the handling is easy even if the substrate thickness is thin.

上記の工程によって、集積回路性能劣化と無関係な第２の主面を除くチップ全体がパッシベーション膜で覆われた化合物半導体装置を、基板の取扱が容易な工程によって製造することができる。   Through the above steps, a compound semiconductor device in which the entire chip except for the second main surface unrelated to the degradation of the integrated circuit performance is covered with a passivation film can be manufactured by a process that allows easy handling of the substrate.

なお、「予定された深さ」が「予定された厚さ」よりも小とすれば、研磨工程後は、図３に示した状態となる。この場合、チッピングが防止でき、さらに、半導体基板１が細かく分離されていないので、管理がしやすい。切り込み３底部の半導体基板１は、他の部位よりも薄くなっているので、容易にへき開し、その結果として、半導体基板は集積回路毎のチップに分離される。   If the “scheduled depth” is smaller than the “scheduled thickness”, the state shown in FIG. 3 is obtained after the polishing step. In this case, chipping can be prevented, and furthermore, since the semiconductor substrate 1 is not finely separated, it is easy to manage. Since the semiconductor substrate 1 at the bottom of the notch 3 is thinner than other parts, it is easily cleaved, and as a result, the semiconductor substrate is separated into chips for each integrated circuit.

本発明に係る化合物半導体装置の製造方法における上記第２の実施の形態の製作フローの断面模式図を図２に示す。   FIG. 2 shows a schematic cross-sectional view of the manufacturing flow of the second embodiment in the method for manufacturing a compound semiconductor device according to the present invention.

図２の（ａ）は、化合物半導体基板である半導体基板１の１つの主面（これを第１の主面とする）に、集積回路を含む領域２が存在する状態を示す断面図である。図において、集積回路を含む領域２は、縦の破線で３つの部分領域に区別され、各部分領域には１つの集積回路が製作されているものとする。   FIG. 2A is a cross-sectional view showing a state in which a region 2 including an integrated circuit exists on one main surface (this is referred to as a first main surface) of a semiconductor substrate 1 that is a compound semiconductor substrate. . In the figure, a region 2 including an integrated circuit is divided into three partial regions by vertical broken lines, and one integrated circuit is manufactured in each partial region.

図２の（ｂ）は、図１の（ａ）に示した状態の半導体基板１の第１の主面に、強度の小さい形成物を保護するため、あるいは、ダイシング時の切削水、切削で生じる微粒子等から集積回路を保護するため、保護膜５を堆積する保護膜堆積工程後の状態を示す断面図である。保護膜５は、裏面（第２の主面）から半導体基板１を研磨する時も、集積回路を保護できる。なお、下記の切り込み形成工程に移る前に、あらかじめ集積回路を分離する工程を設け、その工程によって、切り込み形成前に、各集積回路を、ダイシングまたはエッチングによって、分離しておいてもよい（図示せず）。   FIG. 2B shows the first main surface of the semiconductor substrate 1 in the state shown in FIG. 1A in order to protect a low-strength formed product, or by cutting water and cutting during dicing. It is sectional drawing which shows the state after the protective film deposition process which deposits the protective film 5 in order to protect an integrated circuit from the fine particle etc. which arise. The protective film 5 can protect the integrated circuit even when the semiconductor substrate 1 is polished from the back surface (second main surface). In addition, before moving to the following notch formation process, the process of isolate | separating an integrated circuit may be provided previously, and before the notch formation, each integrated circuit may be separated by dicing or etching (FIG. Not shown).

図２の（ｃ）は、図２の（ｂ）に示した状態の第１の主面の、集積回路が製作されていない部位に、ダイシングによって、予定された深さの切り込み３を形成する切り込み形成工程後の状態を示す断面図である。ここで、上記の「予定された深さ」は、下記の「予定された厚さ」に等しいものとする。ここまでの工程では、基板厚さが十分厚いままなので、基板に十分な強度があるため、基板の取扱が容易である。なお、すでに述べたように、図２の（ｃ）に示した状態の保護膜５を除去して、図１の（ｂ）に示した状態にし、それ以降は、図１に示した工程に従って、化合物半導体装置を製造してもよい。   In FIG. 2C, a notch 3 having a predetermined depth is formed by dicing on a portion of the first main surface in the state shown in FIG. 2B where no integrated circuit is manufactured. It is sectional drawing which shows the state after a notch formation process. Here, the “scheduled depth” is equal to the “scheduled thickness” described below. In the process so far, the substrate thickness remains sufficiently thick, and the substrate has sufficient strength, so that the substrate can be handled easily. As already described, the protective film 5 in the state shown in FIG. 2C is removed to obtain the state shown in FIG. 1B. Thereafter, the process shown in FIG. 1 is followed. A compound semiconductor device may be manufactured.

図２の（ｄ）は、図２の（ｃ）に示した状態の半導体基板１の厚さが予定された厚さになるまで半導体基板１の第２の主面を研磨する研磨工程後の状態を示す断面図である。「予定された深さ」が「予定された厚さ」に等しいので、この研磨工程によって、半導体基板１は集積回路毎のチップに分離される。ここで、半導体基板１が小さく分離されるので、基板厚さが薄くても、その取扱が容易である。   FIG. 2D shows a state after the polishing step of polishing the second main surface of the semiconductor substrate 1 until the thickness of the semiconductor substrate 1 in the state shown in FIG. It is sectional drawing which shows a state. Since the “scheduled depth” is equal to the “scheduled thickness”, the semiconductor substrate 1 is separated into chips for each integrated circuit by this polishing process. Here, since the semiconductor substrate 1 is separated into small pieces, the handling is easy even if the substrate thickness is thin.

上記の工程によって、強度の小さい形成物を保護し、あるいは、ダイシング時の切削水、切削で生じる微粒子等から集積回路を保護しながら、化合物半導体装置を、基板の取扱が容易な工程によって製造することができる。   The compound semiconductor device is manufactured by a process in which handling of the substrate is easy while protecting the formed circuit with low strength by the above process or protecting the integrated circuit from cutting water during dicing, fine particles generated by cutting, and the like. be able to.

なお、「予定された深さ」が「予定された厚さ」よりも小とすれば、研磨工程後は、図４に示した状態となる。この場合、チッピングが防止でき、さらに、半導体基板１が細かく分離されていないので、管理がしやすい。切り込み３底部の半導体基板１は、他の部位よりも薄くなっているので、容易にへき開し、その結果として、半導体基板は集積回路毎のチップに分離される。   If the “scheduled depth” is smaller than the “scheduled thickness”, the state shown in FIG. 4 is obtained after the polishing step. In this case, chipping can be prevented, and furthermore, since the semiconductor substrate 1 is not finely separated, it is easy to manage. Since the semiconductor substrate 1 at the bottom of the notch 3 is thinner than other parts, it is easily cleaved, and as a result, the semiconductor substrate is separated into chips for each integrated circuit.

［実施の形態例１］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、製作された集積回路をダイシングにより分離し、さらに、下地基板にダイシングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、ＳｉＮパッシベーション膜を堆積する。つぎに、１００μｍ〜２００μｍの厚さになるまで、基板を裏面から研磨する。このとき、基板を、切込みを入れた深さに等しくあるいはそれよりも薄くして、基板が集積回路毎のチップに分離するようにする。 [Embodiment 1]
After the integrated circuit is manufactured on the surface of the InP substrate or the GaAs substrate, the manufactured integrated circuit is separated by dicing, and further, a notch with a depth of 100 μm to 200 μm is made in the base substrate by dicing. Next, a SiN passivation film is deposited. Next, the substrate is polished from the back surface until the thickness becomes 100 μm to 200 μm. At this time, the substrate is made equal to or thinner than the depth of the cut so that the substrate is separated into chips for each integrated circuit.

［実施の形態例２］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、保護膜としてレジストを塗布（堆積）する。次にダイシングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、１００μｍ〜２００μｍの厚さになるまで、基板を裏面から研磨する。このとき、基板を、切込みを入れた深さに等しくあるいはそれよりも薄くして、基板が集積回路毎のチップに分離するようにする。 [Embodiment 2]
After an integrated circuit is manufactured on the surface of the InP substrate or GaAs substrate, a resist is applied (deposited) as a protective film. Next, cutting with a depth of 100 μm to 200 μm is made by dicing. Next, the substrate is polished from the back surface until the thickness becomes 100 μm to 200 μm. At this time, the substrate is made equal to or thinner than the depth of the cut so that the substrate is separated into chips for each integrated circuit.

［実施の形態例３］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、強度の小さい形成物を保護するため、レジストを塗布する。つぎに、製作された集積回路をダイシングにより分離し、さらに、下地基板にダイシングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、レジストを除去した後、ＳｉＮパッシベーション膜を堆積する。つぎに、１００μｍ〜２００μｍの厚さになるまで、基板を裏面から研磨する。このとき、基板を、切込みを入れた深さに等しくあるいはそれよりも薄くして、基板が集積回路毎のチップに分離するようにする。 [Embodiment 3]
After the integrated circuit is fabricated on the surface of the InP substrate or GaAs substrate, a resist is applied to protect the formed material having a low strength. Next, the manufactured integrated circuit is separated by dicing, and further, a notch with a depth of 100 μm to 200 μm is made by dicing on the base substrate. Next, after removing the resist, a SiN passivation film is deposited. Next, the substrate is polished from the back surface until the thickness becomes 100 μm to 200 μm. At this time, the substrate is made equal to or thinner than the depth of the cut so that the substrate is separated into chips for each integrated circuit.

［実施の形態例４］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、レジストを塗布し、フォトリソラフィ工程により、切断する箇所のレジストを除去する。つぎに、製作された集積回路をエッチングにより分離し、さらに、下地基板に、ダイシングまたはエッチングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、レジストを除去した後、ＳｉＮパッシベーション膜を堆積する。つぎに、１００μｍ〜２００μｍの厚さになるまで、基板を裏面から研磨する。このとき、基板を、切込みを入れた深さに等しくあるいはそれよりも薄くして、基板が集積回路毎のチップに分離するようにする。 [Embodiment 4]
After an integrated circuit is manufactured on the surface of the InP substrate or GaAs substrate, a resist is applied, and the resist at a portion to be cut is removed by a photolithography process. Next, the manufactured integrated circuit is separated by etching, and further, a cut having a depth of 100 μm to 200 μm is made in the base substrate by dicing or etching. Next, after removing the resist, a SiN passivation film is deposited. Next, the substrate is polished from the back surface until the thickness becomes 100 μm to 200 μm. At this time, the substrate is made equal to or thinner than the depth of the cut so that the substrate is separated into chips for each integrated circuit.

［実施の形態例５］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、保護膜としてレジストを塗布する。次にダイシングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、基板を裏面から研磨する。このとき、基板厚さが、切り込み深さより１００μｍ程度厚くなるようにする。 [Embodiment 5]
After an integrated circuit is manufactured on the surface of the InP substrate or GaAs substrate, a resist is applied as a protective film. Next, cutting with a depth of 100 μm to 200 μm is made by dicing. Next, the substrate is polished from the back surface. At this time, the substrate thickness is set to be about 100 μm thicker than the cut depth.

［実施の形態例６］
ＩｎＰ基板またはＧａＡｓ基板表面上に集積回路を製作した後、強度の小さい形成物を保護するため、レジストを塗布する。つぎに、製作された集積回路をダイシングにより分離し、さらに、下地基板にダイシングにより、１００μｍ〜２００μｍ深さの切り込みを入れる。次に、レジストを除去した後、ＳｉＮパッシベーション膜を堆積する。つぎに、基板を裏面から研磨する。このとき、基板厚さが、切り込み深さより１００μｍ程度厚くなるようにする。 [Embodiment 6]
After the integrated circuit is fabricated on the surface of the InP substrate or GaAs substrate, a resist is applied to protect the formed material having a low strength. Next, the manufactured integrated circuit is separated by dicing, and further, a notch with a depth of 100 μm to 200 μm is made by dicing on the base substrate. Next, after removing the resist, a SiN passivation film is deposited. Next, the substrate is polished from the back surface. At this time, the substrate thickness is set to be about 100 μm thicker than the cut depth.

本発明に係る化合物半導体装置の製造方法における第１の実施の形態の製作フローの断面模式図（「予定された深さ」が「予定された厚さ」に等しい場合）である。It is a cross-sectional schematic diagram (when "planned depth" is equal to "planned thickness") of the manufacturing flow of 1st Embodiment in the manufacturing method of the compound semiconductor device which concerns on this invention. 本発明に係る化合物半導体装置の製造方法における第２の実施の形態の製作フローの断面模式図（「予定された深さ」が「予定された厚さ」に等しい場合）である。It is a cross-sectional schematic diagram (when "planned depth" is equal to "planned thickness") of the manufacturing flow of 2nd Embodiment in the manufacturing method of the compound semiconductor device which concerns on this invention. 本発明に係る化合物半導体装置の製造方法における第１の実施の形態の製作フロー完了時の断面模式図（「予定された深さ」が「予定された厚さ」よりも小の場合）である。FIG. 3 is a schematic cross-sectional view (when “planned depth” is smaller than “planned thickness”) at the completion of the fabrication flow of the first embodiment in the method for fabricating a compound semiconductor device according to the present invention. . 本発明に係る化合物半導体装置の製造方法における第２の実施の形態の製作フロー完了時の断面模式図（「予定された深さ」が「予定された厚さ」よりも小の場合）である。FIG. 5 is a schematic cross-sectional view (when “planned depth” is smaller than “planned thickness”) at the completion of the fabrication flow of the second embodiment in the method for fabricating a compound semiconductor device according to the present invention. .

符号の説明Explanation of symbols

１：半導体基板、２：集積回路を含む領域、３：切り込み、４：パッシベーション膜、５：保護膜。   1: semiconductor substrate, 2: area including integrated circuit, 3: notch, 4: passivation film, 5: protective film.

Claims (6)

化合物半導体基板の集積回路が製作されている側の主面を第１の主面とし、他の側の主面を第２の主面としたとき、
前記第１の主面に、予定された深さの切り込みを形成する切り込み形成工程と、
前記切り込みの表面を含む前記第１の主面上にパッシベーション膜を堆積するパッシベーション膜堆積工程と、
前記パッシベーション膜堆積工程の後に、前記化合物半導体基板の厚さが予定された厚さになるまで前記第２の主面を研磨する研磨工程とを有することを特徴とする化合物半導体装置の製造方法。 When the main surface of the compound semiconductor substrate on which the integrated circuit is manufactured is the first main surface, and the other main surface is the second main surface,
A notch forming step for forming a notch of a predetermined depth in the first main surface;
A passivation film deposition step of depositing a passivation film on the first main surface including the surface of the notch;
And a polishing step of polishing the second main surface until the thickness of the compound semiconductor substrate reaches a predetermined thickness after the passivation film deposition step. 請求項１に記載の化合物半導体装置の製造方法において、
前記切り込み形成工程の前に、前記集積回路を分離する工程を有することを特徴とする化合物半導体装置の製造方法。 In the manufacturing method of the compound semiconductor device according to claim 1,
A method of manufacturing a compound semiconductor device, comprising a step of separating the integrated circuit before the notch forming step. 化合物半導体基板の、集積回路が製作されている側の主面を第１の主面とし、他の側の主面を第２の主面としたとき、
前記第１の主面上に保護膜を堆積する保護膜堆積工程と、
前記保護膜堆積工程の後に、前記第１の主面に予定された深さの切り込みを形成する切り込み形成工程と、
前記切り込み形成工程の後に、前記化合物半導体基板の厚さが予定された厚さになるまで前記第２の主面を研磨する研磨工程とを有することを特徴とする化合物半導体装置の製造方法。 When the main surface of the compound semiconductor substrate on which the integrated circuit is manufactured is the first main surface, and the main surface on the other side is the second main surface,
A protective film deposition step of depositing a protective film on the first main surface;
A notch forming step for forming a notch of a predetermined depth in the first main surface after the protective film deposition step;
And a polishing step of polishing the second main surface until the thickness of the compound semiconductor substrate reaches a predetermined thickness after the notch forming step. 請求項３に記載の化合物半導体装置の製造方法において、
前記保護膜堆積工程と前記切り込み形成工程との間に、前記集積回路を分離する工程を有することを特徴とする化合物半導体装置の製造方法。 In the manufacturing method of the compound semiconductor device according to claim 3,
A method of manufacturing a compound semiconductor device, comprising a step of separating the integrated circuit between the protective film deposition step and the notch formation step. 請求項１、２、３または４に記載の化合物半導体装置の製造方法において、
前記予定された深さが前記予定された厚さに等しいことを特徴とする化合物半導体装置の製造方法。 In the manufacturing method of the compound semiconductor device according to claim 1, 2, 3, or 4,
A method of manufacturing a compound semiconductor device, wherein the predetermined depth is equal to the predetermined thickness. 請求項１、２、３または４に記載の化合物半導体装置の製造方法において、
前記予定された深さが前記予定された厚さよりも小であることを特徴とする化合物半導体装置の製造方法。 In the manufacturing method of the compound semiconductor device according to claim 1, 2, 3, or 4,
The method for manufacturing a compound semiconductor device, wherein the predetermined depth is smaller than the predetermined thickness.
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