JP2009146566A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device stably executing precise operation without causing a malfunction that may occur between synchronous circuits receiving clock signals asynchronous to each other. <P>SOLUTION: An external clock generation circuit 40 generates an external clock signal T1 synchronized with a write command buffer signal TXLWE in response to a mode instruction signal RDY in an "H" level when an internal operation mode is not entered. The external clock signal T1 is fixed to an "L" level in response to entry to the internal operation mode and transition of the mode instruction signal RDY from "H" to "L". An external CUI 10 is not supplied with the external clock signal T1, and enters an external command reception prohibited state. A malfunction due to an external command input, during asynchronous reset, is avoided by keeping the mode instruction signal RDY at the "L" level until asynchronous reset is completed, and setting the signal to the "H" level after the end of asynchronous reset. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more specifically, takes an external command in synchronization with an external clock signal, and transitions between a plurality of operating states corresponding to the taken external command in synchronization with an internal clock signal. The present invention relates to a semiconductor memory device.

  In a semiconductor memory device, various commands are received from the outside, various internal control signals are generated in response to these commands, and internal circuits are controlled by these internal control signals, so that data writing and data reading can be performed. Perform internal operations.

  At this time, the semiconductor memory device takes in the external command in synchronization with the external clock signal having a predetermined cycle by using the included external control signal generation circuit, and generates an external control signal in response to the taken-in external command. Further, in the internal control signal generation circuit, when an external control signal is taken in synchronization with the internal clock signal, in response to this, data is written to the memory cell array or data is erased from the memory cell array. An internal control signal is generated. The control circuit operates the internal circuit in response to the internal control signal.

  Here, the semiconductor memory device requires a certain period of time from receiving an external command to completing a predetermined operation corresponding thereto. Among semiconductor memory devices, particularly in a flash memory that is a nonvolatile memory capable of electrically writing and reading data, it takes time to write data. Inevitably longer.

  Therefore, in the semiconductor memory device, external commands are input in synchronization with an external clock signal, and internal operations are generated in an internal oscillation circuit and are synchronized with an external clock signal that is asynchronous with the external clock signal. It is common to do this. At this time, when the output from the synchronization circuit of the external clock signal is input to the synchronization circuit of the internal clock signal, or vice versa, the timing for accepting the external command and the timing of the internal operation should be adjusted so that they do not overlap. It is necessary to avoid malfunction.

  As for this malfunction, for example, in a DRAM (Dynamic Random Access Memory), when an external command for executing read and write overlaps with an internal command for executing a refresh operation, or in a single port RAM This can also occur when data writing controlled by the CPU (central processing unit) competes with data reading controlled by the communication gate array. For example, Patent Documents 1 and 2 disclose techniques for preventing data destruction and communication failure due to these malfunctions. However, any technique corresponds to a single clock signal to be supplied, and does not necessarily correspond to the above semiconductor memory device to which two clock signals that are asynchronous with each other are supplied.

JP 2002-304895 A JP 9-311811 A

  As described above, in the conventional semiconductor memory device to which two clock signals that are asynchronous with each other are supplied, it is indispensable to adjust the timing of the external command and the internal control signal, but during the internal operation period However, the current situation is that an external command is input to the external control signal generation circuit.

  For this reason, for example, at the end of the internal operation, a reset signal for initializing the included latch circuit or the like is input from the internal control signal generation circuit to the external control signal generation circuit. If a command is input from the outside during the asynchronous reset of the external control signal generation circuit, a logic mismatch occurs in the external control signal generation circuit, resulting in malfunction.

  Further, since the external control signal generation circuit and the internal control signal generation circuit are synchronous circuits that are respectively synchronized with clock signals that are in an asynchronous relationship, they are included in the transfer of the control signal between these circuits. In a sequential circuit such as a flip-flop, a metastable state in which an output signal becomes unstable may occur. When the metastable state occurs, in the control signal generation circuit, the indefinite state is propagated to the logic circuit or the like in the subsequent stage, and there is a possibility that normal operation is impaired.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device that can stably execute an accurate operation without causing a malfunction that may occur between synchronous circuits to which clock signals that are asynchronous with each other are supplied. is there.

  A semiconductor memory device according to the present invention includes an external clock generation circuit for generating an external clock signal in synchronization with a clock signal from outside the device, and an external command given from outside the device in synchronization with the external clock signal An external control signal generating circuit for generating an external control signal in response to the received external command, a memory cell array, and a read / write circuit for performing internal operations of data reading and data writing to the memory cell array An external control signal that is synchronized with an internal clock signal that is asynchronous with the external clock signal, and an internal control signal that controls the memory circuit in response to the captured external control signal. An internal control signal generating circuit for generating and a first logic state in response to the memory circuit entering an internal operation mode; A mode instruction signal generator for generating a mode instruction signal that is in a second logic state in response to the end of the internal operation mode, and the internal clock in response to the mode instruction signal in the first logic state. And an internal clock generation circuit for generating a signal. The external clock generation circuit receives the mode instruction signal and executes an external clock signal generation unit for executing / stopping the generation of the external clock signal, and is synchronized with the device external clock signal regardless of the mode instruction signal. And a second external clock signal generator. The external control signal generation circuit includes a latch circuit that holds a suspend command for suspending the internal operation mode, and the external control signal that suspends the memory circuit in response to the latched suspend command. Generating combinational logic circuit. The latch circuit latches the suspend command in response to the second external clock signal.

  According to the semiconductor memory device in accordance with one aspect of the present invention, when the semiconductor memory device is in the internal operation mode, the acceptance of the external command is prohibited until the internal operation ends and the asynchronous reset of the external control signal generation circuit ends. As a result, it is possible to avoid malfunction due to logic mismatch occurring in the external control signal generation circuit.

  According to a semiconductor memory device according to another aspect of the present invention, a metastable state that may occur at the time of control signal transfer between an internal control circuit and an external control circuit that are asynchronous with each other is avoided, a malfunction is suppressed, and a stable operation is realized. Is done.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of an external clock generation circuit 40 shown in FIG. 1. FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG. 1. It is a block diagram which shows the structure of the semiconductor memory device according to Embodiment 2 of this invention. FIG. 5 is a circuit diagram for explaining asynchronous data transfer between the external CUI 10 and the internal CUI 20 in the semiconductor memory device shown in FIG. 4. FIG. 6 is a circuit diagram showing a configuration of a latch circuit L30 arranged in the asynchronous transfer circuit shown in FIG. FIG. 7 is a timing diagram for explaining a metastable that can occur in the latch circuit L30 shown in FIG. 6. FIG. 11 is a timing diagram for illustrating the operation of the semiconductor memory device according to the second embodiment of the present invention.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

Embodiment 1 FIG.
1 is a block diagram showing a structure of a semiconductor memory device according to the first embodiment of the present invention.

  Referring to FIG. 1, the semiconductor memory device takes in a plurality of external commands and transitions between a plurality of operation states (data read, data write, data erase, etc.) in accordance with the taken-out external commands. Memory. In the following, a flash memory capable of electrically writing and erasing data is applied as a typical nonvolatile memory.

  The flash memory takes in an external command in synchronization with an external clock generation circuit 40 and an external clock signal, and generates an external control signal in response to the external command taken in (hereinafter also referred to as CUI). 10, an internal CUI 20 that generates an internal control signal for controlling the memory circuit 60 in response to the external control signal, and an internal clock generation circuit 50.

  The external clock generation circuit 40 generates external clock signals T1, T2, T1_D, and T2_D_O using a write enable signal WE given from the outside as a trigger. In the present embodiment, it is assumed that a clock signal is generated using a write command buffer signal TXLWE, which is a buffer signal of the write enable signal WE, as a trigger. The generated external clock signal is transmitted to the external CUI 10.

  The external CUI 10 is a synchronization circuit that is controlled in synchronization with an external clock signal, and is also referred to as an external system circuit below. Although not shown, the external CUI 10 includes a plurality of latch circuits that latch external commands from 8-bit input data IOD [7: 0] in response to an external clock signal, and in response to latched external commands. A plurality of combinational logic circuits for generating external control signals. The external control signal functions as a signal for controlling the transition of the operation state of the flash memory and is generated inside the flash memory. The generated external control signal is transmitted to the internal CUI 20.

  Internal clock generation circuit 50 includes an oscillation circuit such as a ring oscillator (not shown). In response to a mode instruction signal RDY indicating that the flash memory has entered an internal operation mode such as an erase operation or a write operation, the oscillation circuit operates and generates complementary internal clock signals P1 and P2.

  Thus, in the semiconductor memory device according to the first embodiment, the external clock signal and the internal clock signal are signals generated independently by different clock generation circuits, and have an asynchronous relationship in which the phases are different from each other.

  The internal CUI 20 is a synchronization circuit that is controlled in synchronization with an internal clock signal, and is also referred to as an internal system circuit below. The internal CUI 20 includes a plurality of latch circuits that latch external control signals in response to internal clock signals, and a plurality of combinations that decode the latched external control signals and generate internal control signals in response to the decoded signals. Including logic circuit. The internal control signal functions as a signal for controlling the internal operation in each operation state of the flash memory. The generated internal control signal is transmitted to the memory circuit 60 and the external CUI 10.

  Memory circuit 60 includes a memory cell array 61 including a plurality of flash memory type memory cells arranged in a matrix, and read / write for reading and erasing data from memory cell array 61 and writing data into the memory cell array Circuit 62.

  Read / write circuit 62 includes a row decoder that selectively activates a word line in response to a row address signal, a column decoder that selectively activates a column selection line in response to a column address signal, An output (I / O) circuit, a row address buffer, a column address buffer, and a preamplifier are included. The I / O circuit accesses the corresponding bit line in response to the column selection line activated by the column decoder, and inputs / outputs data.

  The internal control signal is a signal that controls an operation of erasing or reading data held in the memory cell array 61 of the memory circuit 60 and writing data into the memory cell array 61. The internal control signal includes a row address latch signal for latching the row address signal in the row address buffer, a row address enable signal for activating the row decoder, a word line enable signal for activating the word line driver, A column decoder enable signal for activating the column decoder is included.

  As an example, the row address latch signal is applied to a row address buffer (not shown) of the memory circuit 60. The row address buffer latches a row address signal applied from the outside in response to the row address latch signal.

  As another example, the word line enable signal is supplied to a row decoder (not shown) of the memory circuit 60. The row decoder selectively activates the word line in response to the word line enable signal.

  Here, the external CUI 10 and the internal CUI 20 are parts that are controlled in synchronization with clock signals that are asynchronous with each other. Therefore, in data transfer between the external CUI 10 and the internal CUI 20, it is referred to as a metastable. There may be a problem.

  Metastable means that when an asynchronous signal from the outside is synchronized by a latch or flip-flop, the output signal becomes unstable because it is unknown where the input signal changes. When the metastable state is entered, an indefinite state for a certain period appears in the output signal, and this indefinite state propagates to the subsequent logic circuit, thereby causing a problem that the logic circuit cannot operate normally. This metastable state does not last for a long time and does not necessarily occur, but it causes a malfunction.

  Therefore, in the present embodiment, an asynchronous transfer circuit 30 for adjusting the timing of data transfer is arranged between the external CUI 10 and the internal CUI 20. Although not shown, the asynchronous transfer circuit 30 includes an internal latch circuit that latches an external control signal in response to the internal clock signal, and an external latch circuit that latches the internal control signal in response to the external clock signal. And an asynchronous RS flip-flop.

  In the asynchronous transfer circuit 30, the external control signal and the internal control signal are adjusted in timing to the internal system signal and the external system signal, respectively, and transferred to the corresponding internal system circuit and external system circuit.

  Asynchronous transfer circuit 30 further outputs a mode instruction signal generator 35 for outputting mode instruction signal RDY indicating that the flash memory has entered an internal operation mode such as erasure or program operation based on the external control signal and the internal control signal. Is provided. The mode instruction signal RDY indicates “H” level (= “READY”) in an idle state where the flash memory has not entered the internal operation mode, and “L” in response to the flash memory entering the internal operation mode. Transition to level (= “BUSY”). Mode designation signal RDY is transmitted to external clock generation circuit 40 and internal clock generation circuit 50 as shown in FIG.

  FIG. 2 is a circuit diagram showing a configuration of external clock generation circuit 40 shown in FIG. The external clock generation circuit 40 is a part that generates an external clock signal using a write command buffer signal TXLWE generated in response to a write enable signal WE as an external command as a trigger.

  Referring to FIG. 2, external clock generation circuit 40 includes a phase comparator 41 that performs phase comparison between mode instruction signal RDY and write command buffer signal TXLWE, delay circuits 42 to 45, NAND circuits G42 to G45, Inverters I40 to I46.

  The phase comparator 41 includes an RS type flip-flop composed of NAND circuits G40 and G41. In the RS flip-flop, the mode instruction signal RDY is input to the set input node via the delay circuit 42, and the inverted signal of the write command buffer signal TXLWE is input to the reset input node via the inverter I40. The RS flip-flop performs a phase matching comparison of these two signals and outputs a comparison result signal to the set output node. The set output of the RS flip-flop, that is, the comparison result signal in the phase comparator 41 is inverted by the inverter I41 and input to the first input node of the NAND circuit G42.

  In the phase comparison between the mode instruction signal RDY and the inverted signal of the write command buffer signal TXLWE, the phase comparator 41 determines that the mode instruction signal RDY is “H”, that is, the semiconductor memory device has not entered the internal operation mode. In the “READY” state, an “L” level phase comparison result signal is output. Therefore, the phase comparison result signal inverted to the “H” level is input to the NAND circuit G42.

  On the other hand, the phase comparator 41 outputs an “H” level phase comparison result signal when the mode instruction signal RDY is “L”, that is, in the “BUSY” state in which the flash memory enters the internal operation mode. To do. Therefore, the NAND circuit G42 receives the phase comparison result signal inverted to the “L” level.

  The write command buffer signal TXLWE is inverted by the inverter I40 and input to the third input node of the NAND circuit G42 and the second input node of the NAND circuit G43.

  Further, when the write command buffer signal TXLWE is delayed by a predetermined delay amount (hereinafter referred to as t1) in the delay circuit 43, the write command buffer signal TXLWE is inverted via the inverter I42, and the second input node of the NAND circuit G42 and the NAND The signal is input to the first input node of the circuit G43.

  When the inverted signal of the comparison result signal from the phase comparator 41 is “H” level (corresponding to the “READY” state), the NAND circuit G42 delays the inverted signal of the write command buffer signal TXLWE by the delay amount t1. The logical product of the write command buffer signal TXLWE and the inverted signal is calculated, and the external clock signal T1 is generated as the calculation result. The generated external clock signal T1 is a signal obtained by inverting the write command buffer signal TXLWE, and is delayed by a delay amount t1 from the time when the write command buffer signal TXLWE falls from “H” to “L”. To “H”.

  On the other hand, in the NAND circuit G42, when the inverted signal of the comparison result signal is “L” level (corresponding to “BUSY” state), the external clock signal T1 output from the NAND circuit G42 is fixed to “L” level. Is done.

The NAND circuit G43 calculates the logical product of the inverted signal of the write command buffer signal TXLWE and the inverted signal of the write command buffer signal TXLWE delayed by the delay amount t1, and generates an external clock signal T1_D as the calculation result. The generated external clock signal T1_D is a signal obtained by inverting the write command buffer signal TXLWE, and is delayed by the delay amount t1 from the time when the write command buffer signal TXLWE falls from “H” to “L”. To “H”.

  The write command buffer signal TXLWE is further input to the first input node of the NAND circuit G44. A write command buffer signal TXLWE delayed by a predetermined delay amount (hereinafter referred to as t2) by the delay circuit 44 is input to the second input node of the NAND circuit G44. The NAND circuit G44 outputs an external clock signal T2 as a result of the logical product of these two signals. The external clock signal T2 is a signal synchronized with the write command buffer signal TXLWE, and is delayed by a delay amount t2 determined by the delay circuit 44 from the time when the write command buffer signal TXLWE rises from “L” to “H”. ”To“ H ”.

  The write command buffer signal TXLWE delayed by the delay amount t2 by the delay circuit 44 and the external clock signal T1_D delayed by a predetermined delay amount (hereinafter referred to as t3) by the delay circuit 45 are input to the NAND circuit G45. The The NAND circuit G45 uses the logical product of these two signals as an external result of the one-shot pulse having a pulse width t3-t2 corresponding to the difference between the delay amount t3 of the delay circuit 45 and the delay amount t2 of the delay circuit 44. The clock signal T2_D_O is output.

  Of the external clock signals generated in the external clock generation circuit 40 configured as described above, the generation of only the external clock signal T1 is controlled by the phase comparison result between the mode instruction signal RDY and the write command buffer signal TXLWE. As shown in FIG. 2, the phase comparator 41 is composed of an RS flip-flop, so that its operation state varies depending on the input timing of two signals. Specifically, as shown in FIG. 2, when the two input terminals of the RS flip-flop 41 are A and B and the output terminal is C, the input level of the input terminal B is “L”. In addition, in response to the transition of the input level of the input terminal A from “L” to “H”, the output level of the output terminal C is set to the “L” level reset state.

  Here, when “H” level signals are simultaneously input to the two input terminals A and B, the RS flip-flop is in the “L” level when the output of the output terminal C is in the reset state or in the hold state. In this case, it is impossible to determine whether the signal is at the “H” level, and the output signal is not stable. The metastable state has a possibility of destabilizing the external clock signal T1 for a relatively short period.

  Therefore, as a means for avoiding this metastable state, in this embodiment, as shown in FIG. 2, a delay circuit 43 is provided to adjust the timing at which the external clock signal T1 is output from the NAND circuit G42. A delay amount t1 is given between the time when the buffer signal TXLWE falls and the time when the external clock signal T1 rises. The delay amount t1 is set to be longer than the period during which the metastable state occurs in the phase comparator 41. The specific period of the delay amount t1 is about 10 times or more the gate delay time of the NAND circuits G40 and G41, and is about 5 to 10 [ns].

  As described above, a signal (hereinafter referred to as a second signal) delayed by a certain period with respect to a signal (hereinafter referred to as a first signal) generated from the mode instruction signal RDY and the write command buffer signal TXLWE. The activation timing of the external clock signal T1 (here, the rising timing of the clock) is determined. This fixed period corresponds to a value obtained by subtracting the delay amount generated in the phase comparator 41 from the delay amount t1. As a result, after the phase comparison result signal of the phase comparator 41 returns from the metastable state to the stable state, the NAND circuit G42 is opened and a stable external clock signal T1 is output.

  Next, prohibition of external command reception during the asynchronous reset period of the external CUI 10 will be described.

  Referring to FIG. 1 again, when the external CUI 10 receives the write command buffer signal TXLWE and outputs an external control signal, and this external control signal is transmitted to the internal CUI 20 via the asynchronous transfer circuit 30, the flash memory Entry into the internal operation mode. At this time, the mode instruction signal RDY output from the mode instruction signal generator 35 transits from the “H” level indicating the “READY” state to the “L” level indicating the “BUSY” state. Internal clock generation circuit 50 generates internal clock signals P1 and P2 using “L” level mode instruction signal RDY as a trigger.

  When the internal CUI 20 enters the internal operation mode, the internal CUI 20 performs an internal operation in synchronization with the internal clock signals P1 and P2. Further, when the predetermined operation ends, the internal CUI 20 outputs a reset signal OPRST for initializing a latch circuit arranged in the external CUI 10. The reset signal OPRST is a signal activated (“H” level) for a predetermined period immediately before the flash memory transitions from the “BUSY” state to the “READY” state.

  The external CUI 10 asynchronously resets the internal latch circuit in response to the activated reset signal OPRST. As a result, the external CUI 10 returns to the idle state.

  Here, in the latch circuit arranged in the external CUI 10, if an external command is input during the asynchronous reset period, the asynchronous reset is performed during the synchronous control, which causes a problem. In order to avoid the occurrence of this problem, it is necessary to prohibit the acceptance of external commands during the asynchronous reset period.

  Therefore, in the present embodiment, command input in the external CUI 10 is controlled using the mode instruction signal RDY indicating whether or not the flash memory is in the internal operation mode. After the asynchronous reset is completed, the mode instruction signal RDY is changed from “L” to “H” in response to the deactivation of the reset signal OPRST (“L” level).

  When the mode instruction signal RDY is input to the external clock generation circuit 40, as shown in FIG. 2, the phase is compared with the write command buffer signal TXLWE to control the generation of the external clock signal T1. The external clock generation circuit 40 generates an external clock signal T1 synchronized with the write command buffer signal TXLWE when the mode instruction signal RDY is at “H” level.

  On the other hand, external clock signal T1 is fixed at “L” level in response to transition of mode instruction signal RDY from “H” level to “L” level. That is, when the flash memory enters the internal operation mode and is in the “BUSY” state, the external clock signal T1 is not generated even if the write command buffer signal TXLWE is toggled. Since the external clock signal T1 is not supplied to the external CUI 10, the external CUI 10 is prohibited from accepting external commands.

  Therefore, in order to prevent malfunction due to an external command input during the asynchronous reset period, the mode instruction signal RDY is set to “L” level until the asynchronous reset ends, and is set to “H” level after the asynchronous reset ends. good. When the mode instruction signal RDY is at “L” level, generation of the external clock signal T1 is suppressed, so that acceptance of the external command can be prohibited.

  In order to realize this, as shown in FIG. 2, a delay circuit 42 for delaying the mode instruction signal RDY and inputting it to the input terminal A of the phase comparator 41 is provided. As a result, the external clock generation circuit 40 again generates the external clock signal T1 after delaying a predetermined delay amount of the delay circuit 42 after the mode instruction signal RDY becomes “H” level. That is, the delay circuit 42 is arranged to generate the external clock signal T1 after the operation of the external CUI 10 is reliably completed after the mode instruction signal RDY has transitioned from the “L” level to the “H” level. Yes.

  Here, the delay circuit 42 delays the rising edge of the mode instruction signal RDY compared to the falling edge, and the rising delay may be about 1/6 of the pulse width of the reset signal OPRST. Specifically, the pulse width of the reset signal OPRST is 30 [ns], but is approximately 1 to 5 [ns]. In order to avoid the metastable of the phase comparator 41, the delay amount of the delay circuit 42 needs to be smaller than the delay amount of the delay circuit 43.

  Next, the relationship between each signal and acceptance of an external command will be described. The external clock generation circuit 40 receives the external clock signal T1 in response to the mode instruction signal RDY being at “H” level and the write command buffer signal TXLWE falling from “H” level to “L” level. Raising from “L” level to “H” level, generation of external clock signal T1 is started. When the generated external clock signal T1 is input to the external CUI 10, the external CUI 10 can accept an external command.

FIG. 3 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG.
Referring to FIG. 3, a command for executing a predetermined operation is input to external CUI 10. In the following, it is assumed that the write command buffer signal TXLWE is input for the data erasing operation. The write command buffer signal TXLWE is also input to the external clock generation circuit 40.

  The external clock generation circuit 40 further receives a “H” level mode instruction signal RDY indicating that the flash memory is in the “READY” state. As shown in FIG. 2, the external clock generation circuit 40 generates an external clock signal T1 based on the phase comparison between the mode instruction signal RDY and the write command buffer signal TXLWE. When the mode instruction signal RDY is “H”, the external clock signal T1 is a signal synchronized with the write command buffer signal TXLWE. The external clock signal T1 is “L” at a timing delayed by a delay amount t1 from the falling edge of the write command buffer signal TXLWE in order to avoid a metastable generated by the phase comparator 41 in the external clock generation circuit 40. ”Rise from the“ H ”level to the“ H ”level.

  In addition to the external clock signal T1, the external clock generation circuit 40, as shown in FIG. 3, external clock signals T2 and T1_D that operate independently of the mode instruction signal RDY and a one-shot pulse external clock signal T2_D_O (not shown). ).

  The external CUI 10 latches the write command buffer signal TXLWE in response to the external clock signal T1 in the included latch circuit. Further, in the combinational logic circuit, an external control signal is generated in response to the latched signal.

When this external control signal is transmitted to the internal CUI 20 via the asynchronous transfer circuit 30, the flash memory enters the internal operation mode. At this time, the mode instruction signal RDY output from the mode instruction signal generator 35 transitions from the “H” level indicating the “READY” state to the “L” level indicating the “BUSY” state.

  Internal clock generation circuit 50 generates internal clock signals P1 and P2 that are complementary to each other using mode instruction signal RDY at "L" level as a trigger. The internal CUI 20 generates an internal control signal in response to the external control signal in synchronization with the internal clock signals P1 and P2. In the memory circuit 60, internal operations such as data erasure and program are executed in accordance with the internal control signal.

  On the other hand, in external clock generation circuit 40, external clock signal T1 is fixed at “L” level in response to transition of mode instruction signal RDY from “H” level to “L” level. As a result, the external CUI 10 is in a state where acceptance of external commands is prohibited.

  Next, the internal CUI 20 outputs a reset signal OPRST for returning the external CUI 10 to an idle state immediately before a series of erase operations is completed and the flash memory transitions from “BUSY” to “READY”. The latch circuit of the external CUI 10 is asynchronously reset in response to the reset signal OPRST.

  Finally, in response to the completion of the asynchronous reset in the external CUI 10, the mode instruction signal RDY rises from the “L” level to the “H” level.

  In the external clock generation circuit 40, when the mode instruction signal RDY is “H”, the external clock signal T1 is generated again in response to the fall of the write command buffer signal TXLWE. As a result, the external CUI 10 can accept external commands again.

  As described above, according to the first embodiment of the present invention, when the semiconductor memory device is in the internal operation mode, the external command is accepted until the internal operation is completed and the asynchronous reset of the external control signal generating circuit is completed. Therefore, it is possible to avoid malfunction due to logic mismatch occurring in the external control signal generation circuit.

  In the external clock generation circuit, a stable external clock signal can be transmitted by arranging a delay circuit having a delay amount corresponding to a period in which the phase comparator is in the metastable state.

Embodiment 2. FIG.
In the first embodiment, when the semiconductor memory device is in the internal operation mode, the external command is inhibited from being accepted until the internal operation ends and the asynchronous reset of the external control signal generation circuit ends. The configuration for preventing malfunctions occurring in the control signal generation circuit has been described.

  However, even in the internal operation mode, among the various commands given from the outside, it is necessary to permit only the suspend command for causing the semiconductor memory device to be in a suspended state.

  Therefore, the present embodiment proposes a configuration in which the semiconductor memory device of the first embodiment is further provided with a suspend command receiving function.

  FIG. 4 is a block diagram showing the structure of the semiconductor memory device according to the second embodiment of the present invention. Also in the present embodiment, as in the first embodiment, a flash memory is applied as an example of a semiconductor memory device.

  Referring to FIG. 4, flash memory controls external clock signal generation circuit 40, external CUI 10 that generates an external control signal in synchronization with the external clock signal, and memory circuit 60 in response to the external control signal. The internal CUI 20 for generating the internal control signal, the internal clock generation circuit 50, and the asynchronous transfer circuit 30 are provided. Since these parts are common to the flash memory of the first embodiment shown in FIG. 1, detailed description is omitted.

  The flash memory further includes a suspend-dedicated latch circuit L10 for receiving a suspend command in the external CUI 10. As shown in FIG. 4, the suspend command is given by 8-bit input data IOD [7: 0].

  The suspend-dedicated latch circuit L10 latches the suspend command in response to the external clock signal supplied from the external clock generation circuit 40, like the other latch circuits arranged in the external CUI 10.

  Of the external clock signals generated by the external clock generation circuit 40, for the external clock signal T1, as described above, the mode instruction signal RDY changes from “H” (corresponding to the “READY” state) to “L” (“BUSY”). It is fixed at the “L” level in response to the transition to the “state”. As a result, the external CUI 10 is prohibited from accepting external commands.

  On the other hand, the suspend-dedicated latch circuit L10 is supplied with the external clock signal T1_D. The external clock signal T1_D is a clock signal that operates independently of the mode instruction signal RDY, as described with reference to FIG. Therefore, the suspend-dedicated latch circuit L10 can always accept a suspend command in response to the external clock signal T1_D having a fixed period regardless of the operation mode of the flash memory.

  When the suspend command received by the flash memory during the “BUSY” period is latched by the suspend-dedicated latch circuit L10, it is sent to a combinational logic circuit (not shown). The combinational logic circuit generates an external control signal in response to the latched suspend command and transmits it to the internal CUI 20.

  Here, since the external control signal is a signal synchronized with the external clock signal T1_D, the asynchronous transfer circuit 30 needs to convert the external control signal into a signal synchronized with the internal clock signal when input to the asynchronous internal CUI 20.

  FIG. 5 is a circuit diagram for explaining asynchronous data transfer between the external CUI 10 and the internal CUI 20 in the flash memory shown in FIG.

  Referring to FIG. 5, external CUI 10 is responsive to external clock signals T1 and T2, and latch circuits L11 to L14 for latching various commands input, and external CUI 10 in response to a plurality of latched commands. Combinational logic (CL) circuits 12 and 13 for generating a control signal and an AND circuit G11 for outputting an external control signal in synchronization with the external clock signal T2 are included. The commands applied to the latch circuits L11 to L14 include the mode instruction signal RDY, the setup command SETUP, the internal control signal XHSSPND generated in response to the suspend command in the internal CUI 20, and the like.

  The external CUI 10 includes a suspend-dedicated latch circuit L10 for latching a suspend command in response to the external clock signal T1_D, and a combinational logic (CL) circuit 11 for generating an external control signal in response to the latched suspend command. And an AND circuit G10 for outputting the external control signal in synchronization with the external clock signal T2_D_O of the one-shot pulse.

  The suspend dedicated latch circuit L10 latches the suspend command in response to the external clock signal T1_D, and inputs the latched command to the combinational logic (CL) circuit 11. The combinational logic (CL) circuit 11 decodes the suspend command and generates a signal hrq_sspnd. When the signal hrq_sspnd is input, the AND circuit G10 outputs a one-shot pulse external control signal ORQSSPND in response to the external clock signal T2_D_O.

  Asynchronous transfer circuit 30 includes an asynchronous RS-type flip-flop 32 and latch circuits L30 to L32 that latch external control signals in response to internal clock signals P1 and P2.

  When the external control signal ORQSSPND instructing the suspend is output from the AND circuit G10 of the external CUI 10, the three stages of latch circuits L30 to L30 connected in series via the asynchronous RS flip-flop 32 of the asynchronous transfer circuit 30 are used. Latched at L32. The configuration of the latch circuit will be described later in detail. The latched external control signal ORQSSPND is converted into an internal signal HRQSSPND synchronized with the internal clock signals P 1 and P 2 and transmitted to the internal CUI 20. The internal CUI 20 executes a suspend process in the memory circuit 60 (not shown) in response to the suspend command that has become the internal system signal HRQSSPND. At this time, the internal CUI 20 generates the activated internal control signal HSSPND in response to the memory circuit 60 being saved to the temporary stop state. Further, these latch circuits L30 to L32 are reset in response to activation of the reset signal OPRST.

  Asynchronous transfer circuit 30 further includes, as mode instruction signal generator 35, asynchronous RS flip-flop 33 that receives an internal control signal, asynchronous RS flip-flop 34 that receives an external control signal, and a combinational logic (CL) circuit. 31 and an OR circuit G30.

  When the semiconductor memory device is in the internal operation mode, the OR circuit G30 has the input terminals A and B both at the “L” level and outputs the “L” level mode instruction signal RDY. Further, after the end of normal internal operation (except for the end due to suspend), the input terminal B becomes “H” level, and the mode instruction signal RDY changes to “H” level.

  The RS flip-flop 33 receives the internal control signal HSSPND and generates a signal XHSSPND. The RS flip-flop 34 receives the external control signal and transmits it to the combinational logic (CL) circuit 31. The combinational logic (CL) circuit 31 generates a signal in response to an external control signal and an internal signal. The logical sum of the signal XHSSPND and the output signal of the combinational logic (CL) circuit 31 is calculated in the OR circuit G30, and the mode instruction signal RDY is output as the calculation result.

  FIG. 6 is a circuit diagram showing a configuration of latch circuit L30 arranged in the asynchronous transfer circuit shown in FIG. Note that the latch circuits L30, L31, and L32 included in the asynchronous transfer circuit 30 have the same configuration, and therefore the latch circuit L30 will be described as a representative.

  Referring to FIG. 6, latch circuit L30 includes a transfer gate T30, a NAND circuit G31, and inverters I32 to I34.

  Transfer gate T30 is turned on in response to internal clock signal P2 at "H" level, and takes in an input signal. NAND circuit G31 and inverter I32 form a latch unit in which one input node is coupled to the other output node when inverted signal / OPRST of reset signal OPRST is "H", and the received signal is Hold. Inverter I33 outputs the held signal.

  In the configuration of FIG. 6, the latch circuit L30 is turned off when the internal clock signal P2 is at "H" level and the transfer gate T30 is turned on to take in the input signal, and is turned off when the internal clock signal P2 is at "L" level. The latched signal is held in the latch section. Thus, latch circuit L30 performs a latch operation in synchronization with internal clock signal P2. As shown in FIG. 5, an asynchronous external control signal transferred from the external CUI 10 is input to the latch circuit L30. At this time, in the latch circuit L30, a problem of metastable may occur because the external control signal violates the input timing regulation.

  FIG. 7 is a timing chart for explaining a metastable that can occur in the latch circuit L30 of FIG. In the following, an external control signal ORQSSPND generated from a suspend command is input to the latch circuit L30 as an external control signal.

  As shown in FIG. 7, the external control signal ORQSSPND transitions between valid (“Valid”) and invalid (“Invalid”). In the latch circuit L30, the internal clock signal P2 falls from "H" to "L" and holds the value immediately before the transfer gate T30 is turned off.

  Here, as shown in FIG. 7, when the timing at which the internal clock signal P2 falls coincides with the timing at which the external control signal ORQSSPND transitions from invalid to valid, the output signal of the latch circuit L30 is output for a certain period. There is a case where a metastable that is not fixed occurs. If the metastable appearing in the output signal of the latch circuit L30 is propagated to the internal CUI 20, there is a possibility of causing a malfunction.

  Therefore, as means for avoiding this metastable, as shown in FIG. 5, the asynchronous transfer circuit 30 is constituted by a plurality of stages of latch circuits. For example, in the present embodiment, it is configured by three stages of latch circuits L30 to L32. The latch circuits L30 and L32 latch the input signal in response to the internal clock signal P2, and the latch circuit L31 latches the input signal in response to the internal clock signal P1. The latch circuit L31 is equivalent to a circuit obtained by replacing the input signal of the latch circuit L30 in FIG. 6 from the internal clock signal P2 to P1.

  The external control signal input to the asynchronous transfer circuit 30 is latched in response to the falling of the internal clock signal P2 in the leading latch circuit L30, and is output to the second latch circuit L31. The second latch circuit L31 takes in the external control signal ORQSSPND in response to the internal clock signal P1 rising to H level at the timing when the period t5 has elapsed from the falling edge of the internal clock signal P2. Then, the second latch circuit L31 latches the external control signal ORQSSPND in response to the falling of the internal clock signal P1, and outputs it to the third latch circuit L32. The third latch circuit L32 latches and outputs the external control signal ORQSSPND in response to the rise of the internal clock signal P2 at the timing when the period t4 has elapsed from the fall of the internal clock signal P1.

  That is, the external control signal ORQSSPND is delayed by one clock of the internal clock signal P2 with respect to the case where it is latched by one latch circuit L30. In the first latch circuit L30, metastable may occur due to asynchronous input. However, since the metastable period is usually short enough to fit within one clock, the data logic is determined while data is transferred from the first latch circuit L30 to the third latch circuit L32, and the third In the latch circuit L32, the metastable is not affected, and the external control signal ORQSSPND whose logic is determined as either valid / invalid is latched. With this configuration, a stable signal is transferred to the subsequent internal CUI 20.

  FIG. 8 is a timing diagram for illustrating the operation of the semiconductor memory device according to the second embodiment of the present invention. Hereinafter, a case where an erase operation is executed in the flash memory in response to the write command buffer signal TXLWE will be described as an example.

  The external clock generation circuit 40 generates external clock signals T1, T1_D, T2, and T2_O using the write command buffer signal TXLWE as a trigger. As described in the first embodiment, external clock signal TT1 is a signal synchronized with write command buffer signal TXLWE when mode instruction signal RDY is at “H” level. On the other hand, as shown in FIG. 8, the external clock signal T1_D is a signal that is always synchronized with the write command buffer signal TXLWE regardless of the mode instruction signal RDY.

  Next, mode instruction signal RDY transitions from “H” level indicating “READY” state to “L” level indicating “BUSY” state in response to the semiconductor memory device entering the internal operation mode.

  In external clock generation circuit 40, external clock signal T1 is fixed at "L" level in response to mode instruction signal RDY becoming "L" level. As a result, the external CUI 10 is in a state where acceptance of external commands is prohibited. At this time, the suspend command, which is the only command that needs to be received in the internal operation mode, can be received by the suspend-dedicated latch circuit L10 disposed in the external CUI 10.

  Here, as shown in FIG. 8, it is assumed that the suspend command B0 is input during the “BUSY” period in the data input IOD [7: 0] to the suspend-dedicated latch circuit L10.

  The suspend command B0 is latched in response to the external clock signal T1_D in the suspend dedicated latch circuit L10 shown in FIG. Further, the latched suspend command B 0 is decoded by the combinational logic (CL) circuit 11. The decoded suspend command hrq_sspnd is converted into an external control signal ORQSSPND having a one-shot pulse synchronized with the external clock signal T2_O in the AND circuit G10.

  Further, the external control signal ORQSSPND is transmitted to the asynchronous transfer circuit 30. In the asynchronous transfer circuit 30, the external control signal ORQSSPND is converted into an internal signal HRQSSPND by the asynchronous RS flip-flop 32 and the three-stage latch circuits L 30 to L 32 and transmitted to the internal CUI 20.

  The internal CUI 20 generates an internal control signal by an internal combinational logic (CL) circuit, and temporarily stops the memory circuit 60 by the internal control signal. Further, the internal CUI 20 generates the activated internal control signal HSSPND in response to the memory circuit 60 being saved to the temporary stop state.

  The internal control signal HSSPND is transmitted to the mode instruction signal generator 35. The internal control signal HSSPND becomes a signal XHSSPND via the asynchronous RS flip-flop 33 and is input to the OR circuit G30. The OR circuit G30 outputs the mode instruction signal RDY activated to the “H” level in response to the signal XHSSPND at the “H” level.

  When the mode instruction signal RDY is activated to “H” level, the external clock generation circuit 40 generates the external clock signal T1 in synchronization with the fall of the write command buffer signal TXLWE. When the external clock signal T1 is supplied, the external CUI 10 can accept an external command again.

  As described above, in order to avoid the metastable state, by using the plurality of stages of latch circuits L30 to L32, it is possible to stably transfer the signal between the external system circuit and the internal system circuit. Further, after the internal circuit is temporarily stopped, an external command is received by the external clock signal T1 generated in response to the mode instruction signal RDY, so that the external system circuit can be operated.

  As described above, according to the second embodiment of the present invention, when the semiconductor memory device is in the internal operation mode, the acceptance of external commands is prohibited, so that malfunction can be prevented.

  On the other hand, a suspend command that only needs to be accepted during the internal operation period can be always accepted by providing a dedicated latch circuit and latching in response to an external clock signal that operates regardless of the operation mode.

  Furthermore, in the transfer of control signals between the asynchronous external system circuit and internal system circuit, it is possible to avoid the occurrence of metastable state by adopting a configuration that captures data with a multi-stage latch circuit, and stable operation Can be secured.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 10 External CUI, 11-13, 31 Combinational logic circuit, 20 Internal CUI, 30 Asynchronous transfer circuit, 32, 33 RS type flip-flop, 34 SR type flip-flop, 35 Mode instruction signal generation part, 40 External clock generation circuit, 41 Phase comparator, 42 to 45 delay circuit, 50 internal clock generation circuit, 60 memory circuit, 61 memory cell array, 62 read / write circuit, G31, G40 to G45 NAND circuit, G10, G11 AND circuit, G30 OR circuit, I32 to I34, I40 to I46 Inverter, L10 suspend dedicated latch circuit, L11 to L14, L30 to L32 latch circuit, T30 transfer gate.

Claims (2)

An external clock generation circuit for generating an external clock signal in synchronization with a clock signal from the outside of the device;
An external control signal generating circuit that takes in an external command given from outside the device in synchronization with the external clock signal, and generates an external control signal in response to the taken-in external command;
A memory circuit including a memory cell array and a read / write circuit that performs internal operations of data reading and data writing to the memory cell array;
Internal control signal generation that takes in the external control signal in synchronization with an internal clock signal that is asynchronous with the external clock signal, and generates an internal control signal for controlling the memory circuit in response to the taken-in external control signal Circuit,
A mode instruction signal generator for generating a mode instruction signal that enters a first logic state in response to the memory circuit entering an internal operation mode and enters a second logic state in response to the end of the internal operation mode; ,
An internal clock generation circuit for generating the internal clock signal in response to the mode instruction signal of the first logic state;
The external clock generation circuit includes:
An external clock signal generator for receiving / generating the external clock signal in response to the mode instruction signal;
A second external clock signal generator that is generated in synchronization with the device external clock signal independently of the mode instruction signal,
The external control signal generation circuit is
A latch circuit for holding a suspend command for temporarily suspending the internal operation mode;
A combinational logic circuit for generating the external control signal for suspending the memory circuit in response to the latched suspend command;
The semiconductor memory device, wherein the latch circuit latches the suspend command in response to the second external clock signal. The internal control signal generation circuit and the internal control signal generation circuit are arranged between the external control signal generation circuit and the internal control signal generation circuit. It further includes an asynchronous transfer circuit for transferring,
The asynchronous transfer circuit includes:
2. The semiconductor memory device according to claim 1, further comprising a plurality of stages of latch circuits that latch the external control signal in response to the internal clock signal.

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