JP2009146168A - Part mounting substrate for plc - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a part mounting substrate for PLC (programmable logic controller), capable of responding to an IO memory specification with backup function and an IO memory specification with ECC function at low cost. <P>SOLUTION: The substrate can respond to the IC memory specification with backup function and the IC memory specification with ECC function by selection of mode designation to an ASIC (application specific IC) (4), selection of the type of SRAMs (5 and 6) to be installed to first and second memory installation parts, selection of presence/absence of battery backup to the first and second memory installation parts, and determination of a memory assignment rule in designation of a second mode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a component mounting board for PLC suitable for a programmable controller (hereinafter referred to as “PLC”) having two I / O memories for normal use and backup use.

  A PLC that includes two data memories for normal use and for backup use and has improved reliability when the power is turned off has been known (see Patent Document 1).

  An example of a component mounting board for PLC employed in such a PLC is shown in FIG. As shown in the figure, the PLC component mounting board 100 includes a user memory (hereinafter referred to as “UM”) 1 for storing a user program and a system memory (hereinafter referred to as “UM”) for storing a system program. 2) and a microprocessor (hereinafter referred to as “MPU”) 3 that realizes various functions necessary for the PLC such as an IO refresh function and a peripheral service function by executing a system program stored in the ROM 2. ASIC (Application Specific IC) 4 in which an operation execution circuit for executing a user program stored in UM1 is incorporated, and a first I / O memory having a memory capacity as a normal IO memory (hereinafter referred to as “IOM”) SRAM 5 and a memory capacity as a backup IO memory (hereinafter referred to as “BIOM”) 2, a work RAM (hereinafter referred to as “WRAM”) 7 used as a work area when the MPU 3 executes the system program in the SRAM 2, and a backup user memory (hereinafter referred to as “BUM”). 8) are mounted on a predetermined circuit board.

  The types of the memories 1, 2, 5 to 8 are configured as follows. That is, high-speed synchronous SRAM as UM1, flash memory as SRAM2, high-speed asynchronous SRAM as first SRAM functioning as IOM, and medium-speed SRAM backed up by battery as second SRAM 6 functioning as BIOM However, a medium speed SRAM backed up by a battery is used as the WRAM 7 and a flash memory is used as the BUM 8.

  Here, as is well known to those skilled in the art, a high-speed SRAM is composed of current-driven elements, and it is difficult to back up with a battery for a long time because of its power consumption. On the other hand, since a medium-speed SRAM uses a relatively low power consumption element, it can be backed up for a long time by a battery.

  In FIG. 9, reference numeral 9a is a connector to which peripheral devices are connected, 9b is a connector to which devices supporting RS232 are connected, 9c is an interface for a compact flash (registered trademark) device, 9d is an IO unit and various types It is a connector with the internal bus to which the special function unit is connected.

  In addition to the operation execution circuit for executing the user program stored in the UM1, the ASIC 4 has a startup process for batch copying IO data from the second SRAM 6 to the first SRAM 5 (FIG. 10A )) And when the write command is given, the IO data related to the write command is written in parallel to the first SRAM 5 and the second SRAM 6, while when the read command is given, the IO command related to the read command is given. Processing at the time of calculation execution (see FIG. 10B) designed to read IO data only from the first SRAM 5 and processing at power interruption to back up the second SRAM 6 functioning as a BIOM with a battery (FIG. 10 ( a control circuit designed to support c) is incorporated.

  With the above configuration, the MPU 3 and the ASIC 4 operate to realize the function of the PLC CPU, and the contents of the IOM are retained even in the event of a power failure. Reading is performed only from the side of the first SRAM 5 configured by the high-speed asynchronous SRAM, so that the reading speed can be increased.

  Recently, it has been pointed out that there is a possibility that the PLC malfunctions due to the inversion of the memory cell bit in the SRAM constituting the IOM as a result of the increase in the capacity of the SRAM functioning as the IOM and the miniaturization of the semiconductor process. It is estimated that such memory cell bit inversion in the SRAM is caused by a soft error due to cosmic rays or the like.

  Among the various memories constituting the PLC, the error detection and correction processing by software is mainly adopted for the other memories except the IOM. The error detection and correction processing by this software performs calculation / comparison based on the SUM value, etc., identifies the abnormal location of the memory, and when detecting an abnormality (memory corruption) If the repair is possible, the process tries to repair. However, the IOM that is the storage destination of the IO data is written asynchronously from the MPU 3 and the ASIC 4, so that software detection / correction by the firmware of the MPU 3 is substantially difficult, and what happens to memory corruption? Currently, no measures are taken.

  On the other hand, in the main memory of a personal computer (mainly server system), as shown in FIG. 11, a redundant memory c is added to the main memory b, and the arithmetic processing unit a, the main memory b, and the redundant memory c are added. A hardware error detection and correction method is employed, in which an ECC circuit d is interposed between them and a ECC function is realized using a memory controller.

In this example, an example is shown in which 6 bits are required as a redundant memory that enables 1-bit error correction and 2-bit error detection for a 16-bit data length. In the figure, 16 bits described between the ECC circuit d and the main memory b represent the data length, and the bus width for transmitting and receiving data is appropriately designed according to the data width of the main memory b. Further, 6 bits described between the ECC circuit d and the redundant memory c indicates that the bit length that enables 1-bit error correction and 2-bit error detection for data having a data length of 16 bits is 6 bits. The bus width for transmitting and receiving data is appropriately designed according to the data width of the redundant memory c.
JP 2002-341908 A

  However, it has been found that when the above-described hardware error detection and correction method using the ECC circuit d is applied to the PLC, various problems occur as follows. This problem will be described with reference to FIGS.

  A conventional configuration example is shown in FIG. In this example, the first and second data buses B1 and B2 have a 32-bit width, and correspondingly, the first and second SRAMs 5 and 6 have a 16-bit width, respectively. It has been adopted. In addition, a core 4 a is incorporated in the ASIC 4. The core 4a incorporates at least a calculation execution circuit for executing a user program stored in the UM1 and a control circuit configured to support the three processes shown in FIG.

  FIG. 12B shows a configuration example in which a redundant memory is simply added to the above-described conventional configuration example. As shown in the figure, in this example, the ECC circuits 4b and 4c are incorporated in the ASIC 4, while the SRAM 5-1 which is a redundant memory is also provided for the first SRAM 5 which is the main memory. An SRAM 6-1 that is a redundant memory is provided for the second SRAM 6 that is a main memory.

  In the figure, the SRAM 5 having a 32-bit width that functions as the main IOM is shown separately in the upper 16-bit width area 5a and the lower 16-bit width area 5b, and functions as a redundant IOM-P correspondingly. The 16-bit SRAM 5-1 is shown separately in an upper 8-bit area 5a-1 and a lower 8-bit area 5b-1. Similarly, a 32-bit SRAM 6 that functions as a main BIOM is shown separately in an upper 16-bit width area 6a and a lower 16-bit width area 6b, and correspondingly, 16-bit functions as a redundant BIOM-P. The width SRAM 6-1 is shown separately in an upper 8-bit width region 6a-1 and a lower 8-bit width region 6b-1.

  B1 is a first data bus connecting the ASIC 4 and the first SRAM 5, B2 is a second data bus connecting the ASIC 4 and the second SRAM 6, and B3 is a second data bus connecting the ASIC 4 and the redundant SRAM 5-1. The third data bus B4 is a fourth data bus connecting the ASIC 4 and the redundant SRAM 6-1.

  FIG. 13 shows a configuration example of a use memory (SRAM) according to product specifications. As shown in the figure, when the product specification is “IO memory specification with backup function”, as shown in FIG. 12A, a high-speed SRAM (16 + 16 bits) is used as an IOM, and a battery is used as a BIOM. The medium speed SRAM (16 + 16 bits) backed up by the above is adopted, and neither the IOM redundant memory nor the BIOM redundant memory is mounted. On the other hand, when the product specification is “IO memory specification with ECC function”, the high-speed SRAM (16 + 16 bits) as the IOM, the high-speed SRAM (8 + 8 bits) as the redundant memory for the IOM, and the battery as the BIOM are backed up by the battery. The medium speed SRAM (16 + 16 bits) backed up by a battery is used as the redundant memory for BIOM.

  As described above, if an error detection and correction method using hardware using an ECC circuit is adopted as it is in a PLC, an 8-bit redundant memory is required for the main memory (for example, 16-bit width), which is necessary as a whole. As the number and types of memory devices increase, the third and fourth data buses B3 and B4 must be newly laid, and there is a problem that significant development costs are required due to these factors. In addition, as shown in FIG. 13, in order to cope with two types of product specifications, the number of ASIC pins increases, and there is a problem that the mounting area of the circuit board cannot be secured.

  The present invention has been made paying attention to such conventional problems, and the object of the present invention is to be able to deal with low cost for IO memory specifications with a backup function and IO memory specifications with an ECC function. It is to provide a component mounting board for PLC.

  Other objects and operational effects of the present invention will be easily understood by those skilled in the art by referring to the following description of the specification.

  The above technical problem can be solved by a PLC component mounting board having the following configuration.

  That is, the component mounting board for PLC includes a user memory for storing a user program, a system memory for storing a system program, an IO refresh function by executing the system program stored in the system memory, At least an ASIC in which a microprocessor for realizing various functions necessary for a PLC such as a peripheral service function and an operation execution circuit for executing a user program stored in a user memory are incorporated.

  A first SRAM having a memory capacity as an IO memory can be mounted on the component mounting board for PLC, and battery backup can be selectively performed with respect to the mounted first SRAM. A second SRAM having a memory capacity as a first memory mounting unit and a memory capacity as an IO memory can be mounted, and a battery backup can be selectively performed with respect to the mounted second SRAM. And a memory mounting portion.

  Further, a first data bus is laid between the ASIC and the first memory mounting portion, and a second data bus is laid between the ASIC and the second memory mounting portion. .

  Thereby, the function of the PLC as a CPU is realized by the operation of the microprocessor and the ASIC.

  In addition, when a write command is given to the ASIC, an error correction code is generated based on IO data related to the write command, while when a read command is given, data related to the read command is generated. An ECC circuit configured to perform error detection or error correction based on an error correction code attached to the first, a first mode control circuit that operates alternatively in response to an external mode designation, and a second mode Control circuit.

  The control circuit in the first mode writes IO data related to the write command in parallel to the first SRAM and the second SRAM when the write command is given, and reads the read data when the read command is given. Supporting the operation execution process designed to read IO data related to the command only from the first SRAM and the startup process for batch copying IO data from the second SRAM to the first SRAM It is structured.

  When the write command is given, the control circuit in the second mode gives the IO data related to the write command to the ECC circuit, and outputs the IO data and the error correction code generated by the ECC circuit to the first mode. In the storage target area composed of the SRAM and the second SRAM, when writing is performed according to a predetermined memory allocation rule, and when a read command is given, the IO data and the error code related to the read command are displayed. In accordance with a predetermined memory allocation rule, the system is designed to support reading processing from the storage target area configured by the first SRAM and the second SRAM and supplying the read target area to the ECC circuit.

  Accordingly, selection of mode designation for the ASIC, selection of the SRAM type to be mounted on the first and second memory mounting units, selection of whether or not the battery backup is performed on the first and second memory mounting units, and second The arrangement of the memory allocation rule at the time of mode designation makes it possible to support the IO memory specification with the backup function and the IO memory specification with the ECC function.

  According to such a configuration, selection of mode designation for the ASIC, selection of the SRAM type to be mounted on the first and second memory mounting units, whether or not battery backup is performed on the first and second memory mounting units By selecting and allocating the memory allocation rule when specifying the second mode, it corresponds to the IO memory specification with the backup function and the IO memory specification with the ECC function. It is possible to use an ASIC and a circuit board, which makes it possible to cope with two types of product specifications at a low cost.

  As a preferred embodiment, in order to support the IO memory specification with a backup function, the mode designation for the ASIC is set to the first mode, the first memory mounting unit is a high-speed SRAM, and the second memory mounting unit is In order to support the IO memory specification with the ECC function, the ASIC mode specification is set to the second mode in order to support the backup of the medium speed SRAM mounted on the second memory mounting portion and the medium speed SRAM. The high-speed SRAM is mounted on the first memory mounting section, the medium-speed SRAM is mounted on the second memory mounting section, and the high-speed SRAM mounted on the first memory mounting section and the second memory mounting section are mounted. The medium-speed SRAM is backed up by a battery, and the memory allocation rule in the second mode is used to store two words of IO data in each of the first memories. While it stored in less, and stores the two-word error correction code to each one word of the second memory.

  According to such a configuration, the IO memory specification with the backup function and the IO memory specification with the ECC function can be sold separately at the product level, and the circuit board can be shared, and the number of memory components also changes. Therefore, it is possible to realize two product specifications at low cost.

  As still another preferred embodiment, in order to comply with the IO memory specification with a backup function, the mode designation for the ASIC is set to the first mode, and the first memory mounting unit is equipped with the high-speed SRAM and the second memory mounting. In order to support the IO memory specification with the ECC function in order to backup the medium speed SRAM mounted in the second memory mounting section and battery back up the medium speed SRAM mounted in the second memory mounting section, 2 mode, a high-speed SRAM is mounted on the first memory mounting unit, a medium-speed SRAM is mounted on the second memory mounting unit, and a medium-speed SRAM mounted on the second memory mounting unit is backed up by a battery. In addition, the memory allocation rule of the second memory is a series of the first memory and the second memory for both IO data for one word and its error correction code. It is intended to be stored in each of addresses.

  Even with such a configuration, the IO memory specification with the battery backup function and the IO memory specification with the ECC function can be sold separately at the product level, and the circuit board can be shared, and the number of memory components can be increased. Since there is no change, two types of product specifications can be realized at low cost.

  According to the present invention, selection of mode designation for the ASIC, selection of the SRAM type to be mounted on the first and second memory mounting units, selection of whether or not the battery backup is performed on the first and second memory mounting units, And by deciding the memory allocation rule when specifying the second mode, it is possible to support the IO memory specification with backup function and the IO memory specification with ECC function, so the circuit board is shared and the number of used memory parts is the same Thus, it is possible to realize the correspondence to the two types of product specifications at a low cost.

  A preferred embodiment of a component mounting board for PLC according to the present invention will be described below in detail with reference to the accompanying drawings (FIGS. 1 to 8).

  A block diagram of the first embodiment of the present invention is shown in FIG. 1, and an explanatory diagram of the first embodiment is shown in FIG.

  The overall configuration of the component mounting board for PLC according to the present invention is the same as that of the conventional component mounting board 100 described above with reference to FIG. 9 except for the configuration of the ASIC 4 and the two SRAMs 5 and 6. is there. However, the component mounting board 100 shown in FIG. 9 is a 16-bit bus system, whereas in the embodiment of the present invention, it is a 32-bit bus system. However, this is not an essential difference between the two. It will be easily understood by a trader.

  That is, similar to the conventional example shown in FIG. 9, the component mounting board 100 according to the present invention includes a UM1 for storing a user program, an SRAM 2 for storing a system program, and a system stored in a system memory. An MPU 3 that realizes various functions necessary for PLC such as an IO refresh function and a peripheral service function by executing a program, and an ASIC 4 in which an arithmetic execution circuit 41 for executing a user program stored in the UM 1 is incorporated At least installed.

  The component mounting board 100 can be mounted with the first SRAM 5 having a memory capacity as an IO memory, and the battery can be selectively backed up with respect to the mounted first SRAM. A second memory 6 can be mounted with a second SRAM 6 having a memory capacity as an IO memory, and a battery backup can be selectively performed with respect to the mounted second SRAM. And a memory mounting portion.

  Here, the “memory mounting portion” refers to a socket for mounting a memory package fixed on a circuit board, a terminal pad group for soldering and fixing a memory package, and various types for mounting memory components. All these mechanisms are generically named. In addition, “selective battery backup is possible” means that at least circuit backup wiring is laid on the circuit board, and a battery holder is attached to this in advance or as necessary. On the other hand, it means a configuration that can supply power during a power failure.

  Further, a first data bus B1 is laid between the ASIC 4 and the first memory mounting portion (the first SRAM 5 is mounted), and the ASIC 4 and the second memory mounting portion (the second memory mounting portion (the second SRAM 5 are mounted)). A second data bus B2 is laid between the first and second SRAMs 6). In this example, these data buses B1 and B2 are 32 bits wide.

  In addition to the arithmetic execution circuit 41 described above, a front end circuit 42 is incorporated in the ASIC 4. The front end circuit 42 includes an ECC circuit 42a, a first mode control circuit 42b, and a second mode control circuit 42c, which will be described in detail later.

  When a write command is given from the arithmetic execution circuit 41, the ECC circuit 42a generates an error correction code based on the IO data related to the write command, while when a read command is given, the data related to the read command Is configured to perform error detection or error correction on the basis of the error correction code attached to.

  The control circuit 42b in the first mode and the control circuit 42c in the second mode are configured to operate alternatively in response to a mode designation from the outside. Here, conventionally known various methods may be adopted as a method for giving the mode designation from the outside. For example, one of the external terminals of the ASIC 4 is assigned for mode designation, and the control circuit 42b for the first mode and the control circuit 42c for the second mode are selected depending on whether the logical state of the external terminal is “H” or “L”. Can be configured to be activated.

  The control circuit 42b in the first mode performs a start-up process (see FIG. 10A) for batch copying IO data from the second SRAM 6 to the first SRAM 5, and when a write command is given, the write command The I / O data related to the data is written to the first SRAM 5 and the second SRAM 6 in parallel, and when a read command is given, the IO data related to the read command is read out only from the first SRAM 5 Supports the run-time process (see FIG. 10B) and the power-off process (see FIG. 10C) for backing up the second SRAM 6 with a battery when the power is cut off due to a power failure or the like. It is structured.

  When the write command is given, the control circuit 42c in the second mode gives the IO data related to the write command to the ECC circuit 42a, and the IO data and the error correction code generated by the ECC circuit 42a. A process at the time of writing in accordance with a predetermined memory allocation rule (details will be described later) in a storage target area composed of the first SRAM 5 and the second SRAM 6, and when a read command is given, When reading IO data and error code from a storage target area configured by the first SRAM 5 and the second SRAM 6 in accordance with a predetermined memory allocation rule (details will be described later), and supplying the read data to the ECC circuit 42a It is structured to support processing.

  An operation for causing the component mounting board having the above configuration to correspond to the IO memory specification with the backup function and the IO memory specification with the ECC function will be described with reference to FIG.

  First, in order to configure the component mounting board according to the present invention as an I / O memory specification with a battery backup function, as shown in the table of FIG. A high speed SRAM is mounted as the first SRAM 5 and a medium speed SRAM is mounted as the second SRAM 6. When the operation mode is designated and the memory types of the first and second SRAMs 5 and 6 are selected as described above, the control circuit 42b in the first mode operates, and the description has been given with reference to FIG. As described above, the backup method using the IOM and the BIOM is executed.

  In contrast, in order to make the component mounting board according to the present invention the IO memory specification with the ECC function, as shown in the table of FIG. 2B, the designation of the operation mode of the ASIC 4 is “ECC valid”. Mode, the memory type of the first SRAM 5 is set to medium speed SRAM, and the memory type of the second SRAM 6 is set to medium speed SRAM.

  In addition, the memory allocation rule in the ECC valid mode is set as shown in FIG. That is, in FIG. 2A, 51 is the upper 16-bit width area of the first SRAM (32-bit width) 5, 52 is the lower-order 16-bit width area, and 61 is the upper 12-bit width area of the second SRAM (32-bit width) 6. The first half 6-bit area, 62 is the latter half 6-bit area. As apparent from the figure, IO data is stored in the upper 16-bit area 51 of the first SRAM, and an error code corresponding to this IO data is stored in the 6-bit area 61 of the second SRAM, while the first SRAM IO data is stored in the lower 16-bit area 52 of one SRAM, and an error code corresponding to this IO data is stored in a 6-bit width area 62 of the second SRAM. According to such memory allocation, all IO data is stored in the first SRAM 5, while an error code corresponding to the IO data is stored in the second SRAM 6.

  As described above, assuming that the mode setting and memory type selection shown in FIG. 2B and the memory allocation shown in FIG. When a write command is given from the circuit 41, IO data related to the write command is given to the ECC circuit 42a, and the IO data and the error correction code generated by the ECC circuit 42a are sent to the first SRAM 5 and the first SRAM 5. 2 when writing is performed in accordance with a predetermined memory allocation rule (see FIG. 2A) and a read command is given from the arithmetic execution circuit 41. The first SRAM 5 and the second SRAM 6 according to a predetermined memory allocation rule (see FIG. 2A) Is read out from the storage target area configured by the CPU, and the process at the time of reading is given to the ECC circuit 42a, whereby hardware error detection and error correction using the ECC circuit is performed, and the PLC Operation reliability will be maintained.

  In addition, according to the first embodiment, since the first SRAM 5 itself functions as a BIOM by being backed up by a battery, there is an advantage that IO data is not lost even during a power failure. is there.

  Next, a configuration diagram of a second embodiment of the component mounting board according to the present invention is shown in FIG. 3, and an explanatory diagram thereof is shown in FIG.

  The difference between the component mounting board shown in the second embodiment and the component mounting board shown in the first embodiment is that not only “normal” mode but also “ECC effective” is shown in FIG. 4B. Also in the mode, a high-speed SRAM is used as the first SRAM 5. According to such a configuration, although the power consumption of the first SRAM at the time of a power failure is slightly increased, the user can switch between the “normal” mode and the “ECC valid” mode.

  Next, a configuration diagram of a third embodiment of the component mounting board according to the present invention is shown in FIG. 5, and an explanatory diagram thereof is shown in FIG.

  In the third embodiment, as shown in FIGS. 5 (b) and 6 (a), the first SRAM 5 and the second SRAM 6 have their first half 16-bit width areas 51 and 61 storing IO data. The latter half 16-bit width areas 52 and 62 are error code storage areas (redundant memories). Therefore, in the first and second data buses B1 and B2, the first half 16-bit width area is for IO data transmission / reception, and the subsequent 6-bit width area is for error code transmission / reception.

  On the other hand, in order to make the component mounting board according to the third embodiment have the IO memory specification with the battery backup function, the operation mode designation is set to the “normal” mode as shown in the table of FIG. 6B. The memory type of the first SRAM 5 is a high speed SRAM, and the memory type of the second SRAM 6 is a medium speed SRAM. As a result, as described above, the component mounting board has an IO memory specification with a backup function.

  On the other hand, in order to make the component mounting board the IO memory specification with the ECC function, as shown in the table of FIG. 6B, the operation mode designation is set to the “ECC valid” mode. The memory type of the first SRAM is a high speed SRAM, and the memory type of the second SRAM is a medium speed SRAM. That is, in the third embodiment, the memory type and the battery backup specifications are the same regardless of whether in the “normal” mode or the “ECC valid” mode.

  On the other hand, as described above, as shown in FIG. 6A, regarding the memory allocation in the “ECC valid” mode, the first half 16-bit width area in both the first and second SRAMs 5 and 6. IO data is stored for 51 and 61, and error codes are stored for the subsequent 6-bit width regions 52 and 62, thereby functioning as a redundant memory. In other words, in this third embodiment, the memory allocation rule in the “ECC valid” mode is that both the IO data for one word (16 bits) and its error correction code are transferred to the first SRAM 5 and the second SRAM. It can be said that the data is stored in each of a series of addresses of the SRAM 6.

  In such a configuration, when the control circuit 42c in the second mode operates, when a write command is given from the arithmetic execution circuit 41, IO data related to the write command is given to the ECC circuit 42a, and the IO data and ECC are also given. When writing the error correction code generated by the circuit 42a into a storage target area composed of the first SRAM 5 and the second SRAM 6 in accordance with a predetermined memory allocation rule (see FIG. 6A) When a read command is given from the process and the arithmetic execution circuit 41, the IO data and the error code related to the read command are transferred to the first SRAM 5 and the first SRAM in accordance with a predetermined memory allocation rule (see FIG. 6A). Read-out processing is performed by reading from the storage target area composed of two SRAMs 6 and supplying it to the ECC circuit a Is, bit inversion of the IO data stored in the results area 51, 61 is repaired if necessary, so that the thereby improving the operational reliability in the PLC.

  Note that error correction processing using ECC is well-known in various documents and will not be described in detail. However, if illustrated schematically, processing at the time of writing as shown in FIG. In this case, in response to the write data being given from the host, the ECC circuit executes a Hamming code generation process and outputs write data and parity. The write data and parity output in this way are stored in the main memory and the redundant memory, respectively.

  On the other hand, as shown in FIG. 7B, in the processing at the time of reading, read data and parity are read from the main memory and the redundant memory and are supplied to the ECC circuit. Then, the ECC circuit executes error detection and correction processing based on the parity and the read data, and sends the read data to the host if correction is possible, while sending it to the host if correction is impossible. To report.

  At this time, as for the bit width of the redundant memory for performing 1-bit error correction and 2-bit error detection, as shown in FIG. 8, the necessary redundant memory width (bit) is given to the bus width (bit). In the case of the bus width (16 bits) in the present embodiment, the necessary redundant memory width (bit) is 6 bits.

  As described above in detail, the component mounting board 100 for PLC according to the present invention executes the UM1 for storing the user program, the ROM2 for storing the system program, and the system program stored in the ROM2. By doing so, at least the MPU 3 that realizes various functions necessary for the PLC such as the IO refresh function and the peripheral service function, and the ASIC 4 in which the arithmetic execution circuit 41 for executing the user program stored in the UM is incorporated are mounted. (See FIG. 9).

  In addition, a first SRAM 5 having a memory capacity as an IO memory can be mounted on the component mounting board, and a battery backup can be selectively performed with respect to the mounted first SRAM 5. A second memory 6 that can be mounted with one memory mounting unit and a second SRAM 6 having a memory capacity as an IO memory, and that can be selectively backed up with respect to the mounted second SRAM 6. And a mounting portion. Further, on this component mounting board, the first data bus B1 is laid between the ASIC 4 and the first memory mounting portion, and the second data mounting portion is between the ASIC 4 and the second memory mounting portion. The data bus B2 is laid (see FIGS. 1, 3, and 5).

  As a result, the MPU 3 and the ASIC 4 operate to realize the function of the PLC as a CPU.

  When a write command is given, the ASIC 4 generates an error correction code based on the IO data related to the write command. On the other hand, when a read command is given, it is attached to the data related to the read command. ECC circuit (see FIGS. 7 and 8) 42a configured to perform error detection or error correction based on the error correction code, and a first mode that operates alternatively in response to an external mode designation The second control circuit 42b and the second mode control circuit 42c are incorporated (see FIGS. 1, 3, and 5).

  When the write command is given, the control circuit 42b in the first mode writes IO data related to the write command in parallel to the first SRAM 5 and the second SRAM 6, while when the read command is given, Processing at the time of calculation execution (see FIG. 10B) designed to read out IO data related to the read command only from the first SRAM 5 and batch copy of the IO data from the second SRAM 6 to the first SRAM 5 It is structured to support startup processing (see FIG. 10A).

  On the other hand, when the write command is given, the control circuit 42c in the second mode gives the IO data related to the write command to the ECC circuit 42a, and the IO data and the error correction code generated by the ECC circuit 42a. Is written according to a predetermined memory allocation rule (see FIG. 2A, FIG. 4A, and FIG. 6A) in the storage target area composed of the first SRAM 5 and the second SRAM 6. When the time process and the read command are given, the IO data and the error code related to the read command are read from the storage target area composed of the first SRAM 5 and the second SRAM 6 according to a predetermined memory allocation rule. It is structured to support reading and processing at the time of reading to the ECC circuit 42a.

  Therefore, according to the component mounting board for PLC of the present invention, selection of the mode designation for the ASIC 4, selection of the type of the SRAMs 5 and 6 to be mounted to the first and second memory mounting portions, the first and second By selecting whether or not the battery backup is performed for the memory mounting part 2 and determining the memory allocation rule when the second mode is specified, the IO memory specification with the backup function and the IO memory specification with the ECC function can be supported at low cost. It is.

  In the above embodiment, the present invention is applied to a 32-bit bus system. However, the application of the present invention is not limited to this, and other bus systems such as a 16-bit width, a 64-bit width, and a 128-bit width are also used. Of course, it can be applied.

  According to the present invention, selection of mode designation for the ASIC, selection of the SRAM type to be mounted on the first and second memory mounting units, selection of whether or not the battery backup is performed on the first and second memory mounting units, In addition, the arrangement of the memory allocation rule when the second mode is specified has an advantage that the IO memory specification with the backup function and the IO memory specification with the ECC function can be handled at low cost.

It is a block diagram of 1st Embodiment of this invention. It is explanatory drawing of 1st Embodiment of this invention. It is a block diagram of 2nd Embodiment of this invention. It is explanatory drawing of 2nd Embodiment of this invention. It is a block diagram of 3rd Embodiment of this invention. It is explanatory drawing of 3rd Embodiment of this invention. It is explanatory drawing of the error correction process using ECC. It is explanatory drawing of the redundant memory width for performing 1 bit correction and 2 bit detection. It is a block diagram of the whole mounting circuit of the built-in circuit board of a CPU unit. It is explanatory drawing of the backup method using IOM and BIOM. It is explanatory drawing of the ECC function implementation example in a personal computer (mainly server type). It is explanatory drawing (the 1) of the subject which this invention tends to solve. It is explanatory drawing (the 2) of the subject which this invention tends to solve.

Explanation of symbols

1 User memory 2 System memory 3 Microprocessor 4 ASIC
5 First SRAM
6 Second SRAM
7 Work RAM
8 buffer user memory 9a, 9b, 9c, 9d connector 41 operation execution circuit 42 front end circuit 42a ECC circuit 42b first mode control circuit 42c second mode control circuit 51 upper 16-bit area of first SRAM 52 first Lower 16-bit area of SRAM 61 First-half 6-bit area of first 12 bits of second SRAM 62 Second-half 6-bit area of first 12 bits of second SRAM 100 Component mounting board B1 First data bus B2 Second data bus

Claims (5)

User memory for storing a user program, system memory for storing a system program, and various functions necessary for PLC such as an IO refresh function and peripheral service function by executing the system program stored in the system memory And at least an ASIC in which an arithmetic execution circuit for executing a user program stored in a user memory is incorporated,
A first memory mounting unit that can be mounted with a first SRAM having a memory capacity as an IO memory, and that is selectively backupable with respect to the mounted first SRAM;
A second memory mounting unit that can be mounted with a second SRAM having a memory capacity as an IO memory and that is capable of selectively performing battery backup with respect to the mounted second SRAM; In addition, a first data bus is laid between the ASIC and the first memory mounting section, and a second data bus is laid between the ASIC and the second memory mounting section. And
Thereby, a component mounting board for PLC in which the function of the CPU of the PLC is realized by the operation of the microprocessor and the ASIC,
Inside the ASIC,
When a write command is given, an error correction code is generated based on the IO data related to the write command, while when a read command is given, based on the error correction code attached to the data related to the read command An ECC circuit configured to perform error detection or correction;
A first mode control circuit and a second mode control circuit that operate alternatively in response to a mode designation from the outside are incorporated,
The control circuit in the first mode is
When a write command is given, the IO data related to the write command is written in parallel to the first SRAM and the second SRAM, while when the read command is given, the IO data related to the read command is written to the first SRAM. It is structured so as to support an operation execution process that is structured to read from only the SRAM and a start-up process that collectively copies IO data from the second SRAM to the first SRAM.
The control circuit in the second mode is
When a write command is given, IO data related to the write command is given to the ECC circuit, and the IO data and the error correction code generated by the ECC circuit are sent from the first SRAM and the second SRAM. Write processing to be written in the storage target area configured according to a predetermined memory allocation rule, and when a read command is given, IO data and an error code related to the read command are determined according to the predetermined memory allocation rule. Read from a storage target area constituted by the first SRAM and the second SRAM, and is configured to support a process at the time of reading to the ECC circuit,
Accordingly, selection of mode designation for the ASIC, selection of the SRAM type to be mounted on the first and second memory mounting units, selection of whether or not the battery backup is performed on the first and second memory mounting units, and second A component mounting board for a PLC, characterized by being able to support an IO memory specification with a backup function and an IO memory specification with an ECC function by determining a memory allocation rule at the time of mode designation. To support the IO memory specification with backup function,
The mode designation for the ASIC is the first mode, a high speed SRAM is mounted on the first memory mounting section, a medium speed SRAM is mounted on the second memory mounting section, and a medium speed mounted on the second memory mounting section. SRAM backup battery,
To support the IO memory specification with ECC function,
The ASIC mode designation is set to the second mode, both the first memory mounting section and the second memory mounting section are mounted with a medium speed SRAM, and the medium speed SRAM and the second memory mounting section are mounted on the first memory mounting section. Both of the medium speed SRAMs mounted in the memory mounting unit are backed up by the battery, and the memory allocation rule in the second mode stores 2 words of IO data in each address of the first memory, while 2 words The component mounting board for PLC according to claim 1, wherein an error correction code for 1 minute is stored in each word of the second memory. To support the IO memory specification with backup function,
The mode designation for the ASIC is the first mode, a high speed SRAM is mounted on the first memory mounting section, a medium speed SRAM is mounted on the second memory mounting section, and a medium speed mounted on the second memory mounting section. SRAM backup battery,
To support the IO memory specification with ECC function,
The ASIC mode designation is set to the second mode, a high-speed SRAM is mounted on the first memory mounting section, a medium-speed SRAM is mounted on the second memory mounting section, and a high-speed SRAM mounted on the first memory mounting section, and While all the medium speed SRAMs mounted in the second memory mounting part are battery-backed up, and the memory allocation rule in the second mode stores IO data for two words at each address of the first memory, 2. The component mounting board for PLC according to claim 1, wherein an error correction code for two words is stored in each one word of the second memory. To support the IO memory specification with backup function,
The mode designation for the ASIC is the first mode, a high speed SRAM is mounted on the first memory mounting section, a medium speed SRAM is mounted on the second memory mounting section, and a medium speed mounted on the second memory mounting section. SRAM backup battery,
To support the IO memory specification with ECC function,
The ASIC mode designation is set to the second mode, the first memory mounting unit is mounted with a high-speed SRAM, the second memory mounting unit is mounted with a medium-speed SRAM, and the medium-speed mounted on the second memory mounting unit. RAM backup by battery, and memory allocation rule in second mode stores both IO data for one word and its error correction code in each of a series of addresses of the first memory and the second memory The component mounting board for PLC according to claim 1, wherein:   A PLC on which the component mounting board according to claim 1 is mounted.

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