JP2009141744A5 - - Google Patents
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- JP2009141744A5 JP2009141744A5 JP2007316940A JP2007316940A JP2009141744A5 JP 2009141744 A5 JP2009141744 A5 JP 2009141744A5 JP 2007316940 A JP2007316940 A JP 2007316940A JP 2007316940 A JP2007316940 A JP 2007316940A JP 2009141744 A5 JP2009141744 A5 JP 2009141744A5
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- circuit
- detection
- frame
- sampling
- point
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- 238000001514 detection method Methods 0.000 claims 32
- 238000005070 sampling Methods 0.000 claims 25
- 239000004065 semiconductor Substances 0.000 claims 7
- 230000002776 aggregation Effects 0.000 claims 4
- 238000004220 aggregation Methods 0.000 claims 4
- 230000005540 biological transmission Effects 0.000 claims 2
Claims (8)
前記通信装置における受信回路は、
受信回路におけるクロックの逓倍の周波数で複数の検出ポイントを設定し、フレーム受信中継続して前記検出ポイント毎に受信データの変化を検出する検出回路と、
前記複数の検出ポイント毎に、受信データの変化回数を集計する集計回路と、
前記集計回路で集計された情報に基づき前記検出ポイントのいずれかをサンプリングポイントとして選択する選択回路と、
前記選択回路で選択されたサンプリングポイントにおける受信データをサンプリングするサンプリング回路と、
前記サンプリング回路で検出された受信データを復号化し、受信データとして取り込む回路と、を有し、
前記検出ポイント毎の受信データの変化の検出、前記検出ポイント毎の受信データの変化回数の集計及び前記サンプリングポイントの選択をフレーム受信中全期間において実行することで、フレーム受信中のサンプリングポイントの修正を継続して行うことを特徴とする通信装置。 A communication apparatus for use in a communication system that sends and receives data to be encoded frame structure between the communication devices,
The receiving circuit in the communication device is:
A detection circuit that sets a plurality of detection points at a frequency multiplied by a clock in the reception circuit , detects a change in reception data for each detection point continuously during frame reception, and
For each of the plurality of detection points , a counting circuit that counts the number of changes in received data;
A selection circuit that selects any of the detection points as a sampling point based on the information aggregated by the aggregation circuit ;
A sampling circuit that samples received data at the sampling point selected by the selection circuit;
Decodes the received data detected by the sampling circuit, possess a circuit for taking as the received data, and
Correction of sampling points during frame reception by detecting changes in received data for each detection point, summing up the number of changes in received data for each detection point, and selecting the sampling points over the entire period during frame reception. A communication device characterized by continuously performing
前記選択回路は、サンプリングポイントとして、最も変化回数が多いサンプリングポイントの逆相を選択することを特徴とする通信装置。 The communication device according to claim 1.
The selection circuit is a sub pump ring point, the communication device and selects the reverse phase of the most change a large number of times sampling point.
前記通信装置は送信回路と受信回路をそれぞれ備え、The communication device includes a transmission circuit and a reception circuit,
前記通信装置における前記受信回路は、The receiving circuit in the communication device is:
受信回路におけるクロックの逓倍の周波数で複数の検出ポイントを設定し、相手方通信装置の送信回路から送出される前記フレーム構成の信号を受信している間継続して前記検出ポイント毎に信号レベルの変化を検出する検出回路と、A plurality of detection points are set at a frequency multiplied by the clock in the receiving circuit, and the signal level changes continuously for each detection point while receiving the signal of the frame configuration transmitted from the transmission circuit of the counterpart communication device. A detection circuit for detecting
前記複数の検出ポイント毎に、前記信号レベルの変化の回数を集計する集計回路と、For each of the plurality of detection points, a counting circuit that counts the number of changes in the signal level;
前記集計回路で集計された情報に基づき前記検出ポイントのいずれかをサンプリングポイントとして選択する選択回路と、A selection circuit that selects one of the detection points as a sampling point based on the information aggregated by the aggregation circuit;
前記選択回路で選択されたサンプリングポイントで受信データをサンプリングするサンプリング回路と、A sampling circuit that samples received data at a sampling point selected by the selection circuit;
前記サンプリング回路で検出された受信データを復号化し、受信データとして取り込む回路と、を有し、A circuit that decodes the received data detected by the sampling circuit and captures the received data as received data,
前記検出ポイント毎の信号レベルの変化の検出、前記検出ポイント毎の信号レベルの変化回数の集計及び前記サンプリングポイントの選択をフレーム受信中全期間において実行することで、フレーム受信中に受信フレームに対するサンプリングポイントの修正を継続して行うことを特徴とする通信装置。By detecting the change in signal level at each detection point, summing up the number of changes in signal level at each detection point, and selecting the sampling point over the entire period during frame reception, sampling the received frame during frame reception. A communication apparatus characterized by continuously correcting points.
前記半導体装置上に形成された受信回路は、
受信回路におけるクロックの逓倍の周波数で複数の検出ポイントを設定する手段と、
前記フレームに対し、前記複数の検出ポイントそれぞれにおける受信フレームの信号レベルを検出する検出回路と、
前記検出ポイントそれぞれで検出される信号レベルの変化の回数を集計する集計回路と、
前記集計回路で集計された情報に基づき前記検出ポイントのいずれかをサンプリングポイントとして選択する選択回路と、
前記選択回路で選択されたサンプリングポイントで受信データをサンプリングするサンプリング回路と、
前記サンプリング回路で検出された受信データを復号化し、受信データとして取り込む回路と、を有し、
前記半導体装置が組み込まれた通信装置において前記受信回路は、
前記複数の検出ポイントそれぞれにおける受信フレームの信号レベルの検出と、前記検出ポイントそれぞれで検出される信号レベルの変化の回数の集計と、当該集計された情報に基づくサンプリングポイントの修正と、修正されたサンプリングポイントにおける受信フレームに対するサンプリングとを、フレーム受信中全期間において継続して実行するように構成されてなることを特徴とする半導体装置。 A semiconductor device incorporated in a communication device to send and receive signals encoded frame structure,
The receiving circuit formed on the semiconductor device is
Means for setting a plurality of detection points at a frequency multiplied by a clock in the receiving circuit;
Relative to the frame, a detection circuit for detecting a signal level of a received frame in the plurality of detection points respectively,
A counting circuit that counts the number of signal level changes detected at each of the detection points ;
A selection circuit that selects any of the detection points as a sampling point based on the information aggregated by the aggregation circuit ;
A sampling circuit that samples received data at a sampling point selected by the selection circuit;
A circuit that decodes the received data detected by the sampling circuit and captures the received data as received data,
In the communication device in which the semiconductor device is incorporated, the receiving circuit is
The detection of the signal level of the received frame at each of the plurality of detection points, the aggregation of the number of changes in the signal level detected at each of the detection points, the correction of the sampling point based on the aggregated information, and the correction A semiconductor device configured to continuously perform sampling for a received frame at a sampling point in all periods during frame reception .
前記選択回路は、前記信号レベルの変化回数が最も多いと判定された検出ポイントの逆相になる検出ポイントをサンプリングポイントとして選択することを特徴とする半導体装置。 The semiconductor device according to claim 6 .
The selection circuit is a semiconductor device characterized by selecting a detection point in opposite phase detection point number of changes in the signal level is determined to be highest in the sampling points.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007316940A JP2009141744A (en) | 2007-12-07 | 2007-12-07 | Communication equipment and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007316940A JP2009141744A (en) | 2007-12-07 | 2007-12-07 | Communication equipment and semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JP2009141744A JP2009141744A (en) | 2009-06-25 |
JP2009141744A5 true JP2009141744A5 (en) | 2010-11-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007316940A Pending JP2009141744A (en) | 2007-12-07 | 2007-12-07 | Communication equipment and semiconductor device |
Country Status (1)
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JP (1) | JP2009141744A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5649496B2 (en) * | 2011-03-30 | 2015-01-07 | 三菱電機株式会社 | Burst CDR circuit and method for reproducing input data signal from burst signal |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3178612B2 (en) * | 1991-05-24 | 2001-06-25 | 日本電信電話株式会社 | Phase synchronous clock extraction circuit |
JP2000031951A (en) * | 1998-07-15 | 2000-01-28 | Fujitsu Ltd | Burst synchronization circuit |
JP2002082830A (en) * | 2000-02-14 | 2002-03-22 | Mitsubishi Electric Corp | Interface circuit |
JP2001230765A (en) * | 2000-02-17 | 2001-08-24 | Fujikura Ltd | Clock signal extraction circuit |
JP2002300141A (en) * | 2001-03-30 | 2002-10-11 | Anritsu Corp | Device and method for controlling data capturing timing |
JP4599247B2 (en) * | 2005-07-29 | 2010-12-15 | 株式会社ケンウッド | Symbol detection apparatus, symbol detection method, symbol detection control program, and recording medium |
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2007
- 2007-12-07 JP JP2007316940A patent/JP2009141744A/en active Pending
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