JP2009141624A - Image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image sensor capable of reducing the 1/f noise by a simple control. <P>SOLUTION: The image sensor 1 comprises: a selection signal generating part 12 which outputs pulse waves P output from a pulse generating part 11 as a selection signal SEL1 to be input to a selecting transistor of a pixel cell 100 on a first line and a selection signal SEL2 to be input to the selecting transistor of the pixel cell 100 on a second line when line selection address signals AD1, AD2 output from a line selection address signal generating part 200 become in an active level; and an output reading part 13 for reading outputs (Q11, Q12, Q21, Q22) of an amplifying transistor of each pixel cell 100 to output signal lines (S1, S2). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image sensor.

  In recent years, CMOS image sensors have become widespread as image pickup devices such as digital cameras. In this CMOS image sensor, potential information defined by charges generated in a photoelectric conversion element such as a photodiode is transmitted to the outside through an amplifying transistor.

  As a general configuration, a CMOS image sensor amplifies a photoelectric conversion element, a transfer transistor that transfers charges accumulated in the photoelectric conversion element, and a potential defined by the charge transferred by the transfer transistor. A pixel cell having an amplifying transistor, a resetting transistor for setting a reset potential to the amplifying transistor, and a selecting transistor for selectively operating the amplifying transistor when a row selection address signal is input. The configuration to be arranged in.

  In order to meet the recent demand for improvement in pixel density, the size of the pixel cell is reduced, and each transistor of the pixel cell is almost set to a very small gate width and length. In particular, the amplifying transistor is often the smallest dimension possible in the manufacturing process used. As a result, there arises a problem that 1 / f noise increases as a characteristic of the MOS transistor.

  As a method for reducing the 1 / f noise, it is known that it is effective to lower the gate voltage of the MOS transistor or lower the drain-source voltage. Therefore, conventionally, an amplifying fixed imaging device that reduces the 1 / f noise generated in the amplifying transistor by shifting the gate potential of the amplifying transistor to the low potential side before the potential is transferred from the transferring transistor ( For example, refer to Patent Document 1), or a sample hold circuit is added to the amplifying transistor, and when the sample hold circuit is in the hold state, the source potential of the amplifying transistor is switched multiple times to generate 1 in the amplifying transistor. An imaging device that reduces / f noise has been proposed (see, for example, Patent Document 2).

However, in the above-described amplification type fixed imaging device, in order to shift the gate potential of the amplification transistor to the low potential side, it is necessary to increase and decrease the gate voltage of the transfer transistor in a short time, Alternatively, in the above-described imaging device, there is a problem that it is difficult to control the operation around the amplifying transistor, for example, the sample / hold operation must be synchronized with the amplifying operation of the amplifying transistor after adding the sample / hold circuit. there were.
JP 2007-60500 A JP 2003-32554 A

  An object of the present invention is to provide an image sensor capable of reducing 1 / f noise by simple control.

  According to one embodiment of the present invention, a photoelectric conversion element, a transfer transistor that transfers charge accumulated in the photoelectric conversion element, and an amplification that amplifies a potential defined by the charge transferred by the transfer transistor A pixel cell having a transistor, a reset transistor that sets a reset potential to the amplification transistor, and a selection transistor that selectively operates the amplification transistor when a selection signal is input is arranged in a matrix An image sensor having a cycle shorter than an interval between a timing at which a reset signal for controlling conduction of the reset transistor becomes active level and a timing at which a transfer signal for controlling conduction of the transfer transistor becomes active level. Pulse generating means for generating a changing pulse wave; Selection signal generating means for outputting the pulse wave output from the pulse generating means as the selection signal when the selection address signal becomes active level, and when both the transfer signal and the selection signal are at the active level There is provided an image sensor comprising output reading means for reading the output of the amplifying transistor to an output signal line.

  According to the present invention, 1 / f noise generated in an image sensor can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram schematically illustrating the configuration of the image sensor according to the first embodiment of the invention. For ease of explanation, FIG. 1 shows an example in which pixel cells 100 are arranged in a matrix of 2 rows × 2 columns. In practice, a much larger number of pixel cells 100 are arranged.

  Here, prior to the description of the image sensor 1 of the present embodiment, the configuration of the pixel cell 100 used in the present embodiment will be described.

  FIG. 2 is a circuit diagram illustrating an example of the configuration of the pixel cell 100.

  The pixel cell 100 is transferred by a photodiode PD that is a photoelectric conversion element, a transfer transistor MT1 that transfers charges accumulated in the photodiode PD when the transfer signal TG becomes an active level, and a transfer transistor MT1. An amplifying transistor MT2 for amplifying a potential defined by the charges, a reset transistor MT3 for setting the operating power supply potential VDD as a reset potential in the amplifying transistor MT2 when the reset signal R becomes active level, and a power supply terminal A selection transistor MT4 that selectively operates the amplification transistor MT2 when a potential is applied to VD from the outside and the selection signal S is input.

  Next, the image sensor 1 of the present embodiment will be described.

  The image sensor 1 shown in FIG. 1 is arranged in a matrix of 2 rows × 2 columns, a pixel cell 100 to which an operation power supply potential VDD is applied to a power supply terminal VD, and a row selection that outputs row selection address signals AD1 and AD2. The timing at which the address signal generator 200 and the reset signal R1 (R2) for controlling the conduction of the reset transistor MT3 become active level and the timing at which the transfer signal TG1 (TG2) for controlling the conduction of the transfer transistor MT1 becomes active level The pulse generator 11 that generates a pulse wave P that changes at a cycle shorter than the interval of the above, and the pulse wave P that is output from the pulse generator 11 when the row selection address signals AD1 and AD2 are at an active level, Selection signal SEL for pixel cell 100 in the first row, for pixel cell 100 in the first row The selection signal generation unit 12 that outputs each as EL2, and the transfer signal TG1 and the selection signal SEL1 in the first row, or the amplification of each pixel cell 100 when the transfer signal TG2 and the selection signal SEL2 in the second row are both at the active level. And an output reading unit 13 for reading out the outputs (Q11, Q12, Q21, Q22) of the transistor MT2 to the output signal lines (S1, S2).

  The selection signal generation unit 12 includes a switch SW1 that switches a signal output to the selection signal SEL1 by the row selection address signal AD1, and a switch SW2 that switches a signal output to the selection signal SEL2 by the row selection address signal AD2. Have.

  The switch SW1 outputs the pulse wave P output from the pulse generator 11 as the selection signal SEL1 when the row selection address signal AD1 is at the active level, and selects the selection signal when the row selection address signal AD1 is at the inactive level. SEL1 is set to the ground potential.

  Similarly, the switch SW2 outputs the pulse wave P output from the pulse generator 11 as the selection signal SEL2 when the row selection address signal AD2 is at the active level, and when the row selection address signal AD2 is at the inactive level. Uses the selection signal SEL2 as the ground potential.

  Next, the operation of the image sensor 1 of the present embodiment will be described using the waveform diagram shown in FIG. Here, the active levels of the reset signals R1 and R2, the transfer signals TG1 and TG2, and the row selection address signals AD1 and AD2 are all set to the 'H' level.

  The pulse generator 11 generates a pulse wave P that changes at a cycle T2 shorter than the interval T1 between the timing when the reset signal R1 (R2) becomes “H” and the timing when the transfer signal TG1 (TG2) becomes “H”. .

  When the row selection address signal AD1 becomes 'H', a pulse wave P is output to the selection signal SEL1 by switching the SW1 of the selection signal generator 12. As a result, the gate voltage of the selection transistor MT4 of the pixel cell 100 in the first row changes in the cycle T2, and the conductive / non-conductive state of the selection transistor MT4 changes in the cycle T2.

  When the selection transistor MT4 is turned on, the drain potential of the amplification transistor MT2 becomes high, but when the selection transistor MT4 is turned off, the drain potential of the amplification transistor MT2 is lowered.

  On the other hand, the 'H' level is inputted to the gate electrode of the amplifying transistor MT2 through the resetting transistor MT3 which is turned on by the reset signal R1 inputted together with the row selection address signal AD1. Even if the reset signal R1 is turned off, the 'H' level is held by a parasitic capacitance such as the gate capacitance of the amplifying transistor MT2 until the transfer signal TG1 is input.

  Therefore, the output Q (Q11, Q12) of the amplifying transistor MT2 corresponds to the change in the drain potential of the amplifying transistor MT2 during the period T1 until the reset signal R1 is input and the transfer signal TG1 is input. The output potential changes.

  At this time, when the drain potential of the amplifying transistor MT2 decreases and the drain-source voltage decreases, the number of charges trapped in the gate oxide film of the amplifying transistor MT2 that causes 1 / f noise decreases. Noise generated in the amplifying transistor MT2 is reduced.

  In this case, since the drain-source voltage of the amplifying transistor MT2 changes in the cycle T2, 1 / f noise having a cycle longer than the cycle T2 is reduced.

  Thereafter, when the transfer signal TG1 is input, the electric charge accumulated in the photodiode PD is transferred to the gate electrode of the amplifying transistor MT2, and the gate potential of the amplifying transistor MT2 is lowered according to the amount of the electric charge.

  When the selection signal SEL1 becomes “H” level when the transfer signal TG1 is “H” level, the drain potential of the amplifying transistor MT2 becomes high potential, and the output Q (Q11, Q12) of the amplifying transistor MT2 is a photodiode. A signal having a level corresponding to the gate potential determined by the charge transferred from the PD is output.

  Therefore, the output reading unit 13 reads the output Q11 of the amplifying transistor MT2 when the transfer signal TG1 and the selection signal SEL1 are both at the “H” level, and reads the output Q12 to the signal line S2.

  Similarly, when the row selection address signal AD2 becomes 'H', a pulse wave P is output to the selection signal SEL2 by switching the SW2 of the selection signal generation unit 12. As a result, the gate voltage of the selection transistor MT4 of the pixel cell 100 in the second row changes in the cycle T2, and the conduction / non-passage state of the selection transistor MT4 changes in the cycle T2.

  As a result, also in the amplifying transistor MT2 of the pixel cell 100 in the second row, 1 / f noise having a period longer than the period T2 is reduced.

  The output readout unit 13 connected to the pixel cell 100 in the second row reads out the output Q21 of the amplification transistor MT2 when the transfer signal TG2 and the selection signal SEL2 are both at the “H” level to the signal line S1, and outputs the output Q22. To the signal line S2.

  In this way, a signal having a level corresponding to the amount of charge photoelectrically converted is output from the pixel cells in the row selected by the row selection address signal to the signal lines S1 and S2.

  According to the present embodiment, by periodically changing the gate potential of the selection transistor in a pulse shape, the drain-source voltage of the amplification transistor is periodically changed, and a period longer than this period. 1 / f noise can be reduced.

  In addition, since the 1 / f noise is reduced in the selection transistor whose gate potential changes periodically, the 1 / f noise of the entire image sensor can be further reduced.

  The amplitude of the pulse wave P output from the pulse wave generator 11 of the first embodiment is normally set to the operating power supply potential VDD. Therefore, when the pulse wave P is applied to the gate electrode of the selection transistor MT4, the maximum level of the gate potential of the selection transistor MT4 is VDD. However, when viewed from the amount of 1 / f noise generated, there is no change even if the gate potential of MT4 is somewhat lower than VDD. On the other hand, the higher the gate potential of the selection transistor MT4, the higher the power consumption of the selection transistor MT4.

  Therefore, in this embodiment, the amplitude of the pulse wave P output from the pulse wave generator 11 is made variable so that the amplitude of the pulse wave P can be reduced.

  FIG. 4 shows a schematic block diagram of a configuration of an image sensor according to the second embodiment of the present invention.

  The image sensor 2 of the present embodiment is obtained by adding an amplitude controller 14 that controls the amplitude of the pulse wave P output from the pulse wave generator 11 to the image sensor 1 of the first embodiment. Therefore, blocks having the same functions as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

  The amplitude controller 14 changes the amplitude of the pulse wave P output from the pulse wave generator 11 according to the setting of the input amplitude setting signal.

  The amplitude setting signal is input, for example, in order to adjust the amplitude of the pulse wave P as low as possible within a range where the noise generation state of the image sensor output does not deteriorate.

  FIG. 5 shows the state of the amplitude of the pulse wave P controlled by the amplitude control unit 14.

  FIG. 5A shows the waveform of the pulse wave P when it is controlled to be “large amplitude”, and FIG. 5B is the pulse wave when it is controlled to be “small amplitude”. P waveform.

  According to this embodiment, the gate potential of the selection transistor can be lowered while reducing the 1 / f noise generated in the amplification transistor and the selection transistor, so that the power consumption of the selection transistor is reduced. Can be reduced. In particular, in an image sensor using a large number of pixel cells, a selection transistor is used as many as the number of pixel cells, so that a large power consumption reduction effect can be expected.

  In the first and second embodiments, the operating power supply potential VDD is applied to the power supply terminal VD of the selection transistor MT4 of each pixel cell 100. However, the selection transistor MT4 operates only when the row selection address signal is input. When the row selection address signal is not input, the gate potential of the selection transistor MT4 is the ground potential, and the selection transistor MT4 is non-conductive. However, even if the gate potential is the ground potential, if the operating power supply potential VDD is applied to the power supply terminal VD, a small amount of current flows through the selection transistor MT4. Even if the number is small, a large-scale image sensor uses a large number of selection transistors MT4, and the current consumption is considerably large.

  Therefore, in this embodiment, the potential applied to the power supply terminal VD of the selection transistor MT4 is switched according to the input of the row selection address signal, and when the input of the row selection address signal is not input, the ground potential is applied to the power supply terminal VD. To.

  FIG. 6 shows a schematic block diagram of a configuration of an image sensor according to the third embodiment of the present invention.

  The image sensor 3 of the present embodiment shown in FIG. 6 is a power supply that switches the potential applied to the power supply terminal VD of the selection transistor MT4 in accordance with the input of the row selection address signal to the image sensor 2 of the second embodiment shown in FIG. This is an example in which a switching unit 15 is added.

  Therefore, blocks having the same functions as those in the second embodiment are denoted by the same reference numerals as those in FIG. 4, and detailed description thereof is omitted here.

  In addition to the example shown in FIG. 6, the power supply switching unit 15 may be added to the image sensor 1 of the first embodiment.

  The power supply switching unit 15 switches the potential applied to the power supply terminal VD of the selection transistor MT4 of the pixel cell 100 in the first row by the row selection address signal AD1, and the pixel in the second row by the row selection address signal AD2. And a switch SW12 that switches a potential applied to the power supply terminal VD of the selection transistor MT4 of the cell 100.

  The switch SW11 applies a VDD potential to the power supply terminal VD of the selection transistor MT4 of the pixel cell 100 in the first row when the row selection address signal AD1 is at an active level, and the row selection address signal AD1 is at an inactive level. When the ground potential is applied.

  Similarly, the switch SW12 applies a VDD potential to the power supply terminal VD of the selection transistor MT4 of the pixel cell 100 in the second row when the row selection address signal AD2 is at an active level, and the row selection address signal AD1 is inactive. When it is level, a ground potential is applied.

  FIG. 7 shows how the potential of the power supply terminal VD of the selection transistor MT4 is switched by the row selection address signal AD1 or AD2.

  When the row selection address signal AD1 or AD2 is 'H', the VDD potential is applied to the power supply terminal VD of the selection transistor MT4. When the row selection address signal AD1 or AD2 is 'L', the selection transistor A ground potential (GND) is applied to the power supply terminal VD of MT4.

  According to the present embodiment, since the operation power supply potential is applied to the selection transistor power supply terminal only when the selection transistor performs the selection operation on the amplification transistor, unnecessary current consumption of the selection transistor can be suppressed. The power consumption of the image sensor can be reduced.

1 is a block diagram showing an outline of the configuration of an image sensor according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram illustrating an example of a configuration of a pixel cell according to an embodiment of the present invention. FIG. 6 is a waveform diagram illustrating an example of the operation of the image sensor according to the first embodiment. FIG. 5 is a block diagram illustrating an outline of a configuration of an image sensor according to a second embodiment of the invention. FIG. 6 is a waveform diagram illustrating an example of pulse wave amplitude control of the image sensor according to the second embodiment. FIG. 5 is a block diagram illustrating an outline of a configuration of an image sensor according to a third embodiment of the invention. FIG. 10 is a waveform diagram illustrating an example of an operation of a power supply switching unit of the image sensor according to the third embodiment.

Explanation of symbols

1, 2, 3 Image sensor 11 Pulse wave generation unit 12 Selection signal generation unit 13 Output reading unit 14 Amplitude control unit 15 Power supply switching unit SW1, SW2, SW11, SW12 switch

Claims (4)

A photoelectric conversion element; a transfer transistor that transfers charges accumulated in the photoelectric conversion element; an amplification transistor that amplifies a potential defined by the charge transferred by the transfer transistor; and a reset to the amplification transistor An image sensor in which pixel cells having a reset transistor for setting a potential and a selection transistor for selectively operating the amplification transistor when a selection signal is input are arranged in a matrix,
A pulse that generates a pulse wave that changes in a cycle shorter than the interval between the timing at which the reset signal for controlling conduction of the reset transistor becomes active level and the timing at which the transfer signal for controlling conduction of the transfer transistor becomes active level Generating means;
Selection signal generation means for outputting the pulse wave output from the pulse generation means when the row selection address signal becomes an active level as the selection signal;
An image sensor comprising: an output reading unit that reads the output of the amplification transistor to an output signal line when both the transfer signal and the selection signal are at an active level. The image sensor according to claim 1, further comprising an amplitude control unit that changes an amplitude of a pulse wave generated by the pulse generation unit. The image sensor according to claim 1, further comprising a power supply potential switching unit that switches a power supply potential of the selection transistor in accordance with an output of the row selection address signal. The power supply potential switching unit is
When the row selection address signal is at an active level, an operating power supply potential is output,
4. The image sensor according to claim 3, wherein a ground potential is output when the row selection address signal is at an inactive level.

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