JP2009136077A - Motor drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor drive circuit that appropriately carries out overcurrent protection. <P>SOLUTION: The motor drive circuit includes: an energization control circuit that controls turn-on/off of a drive transistor connected to a motor coil to energize the motor coil; an overcurrent detection circuit that detects whether an overcurrent state has occurred and the current passed through the drive transistor has exceeded a predetermined threshold; a charging and discharging circuit that discharges a capacitor when an overcurrent is not detected any more after charging of the capacitor was started because the overcurrent was detected by the overcurrent detection circuit; and an overcurrent protection control circuit. Until a charging period during which the charging voltage of the capacitor at a predetermined voltage exceeds a threshold voltage passes, the overcurrent protection control circuit stops on/off control on the drive transistor by the energization control circuit to keep the drive transistor off. After the charging period has passed, the overcurrent protection control circuit determines whether to carry out overcurrent protection control to turn off the drive transistor in response to the detection of the above overcurrent. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a motor drive circuit.

  The motor drive circuit usually includes an overcurrent protection circuit that protects the motor drive circuit from an overcurrent state that occurs due to a short-circuit accident (such as a power fault, a ground fault, or a load short-circuit). Hereinafter, the motor drive circuit 10 including the overcurrent protection circuit will be described with reference to FIG.

  The motor drive circuit 10 has a configuration surrounded by an alternate long and short dash line shown in FIG. Specifically, the motor drive circuit 10 includes an H bridge circuit 11, an energization control circuit 12, an overcurrent state detection circuit 13, an overcurrent protection circuit 14, and a mask period setting circuit 15. 6 is configured.

  The H bridge circuit 11 bridges the source transistors 1 and 2 on the power supply Vdd side and the sink transistors 3 and 4 on the ground side (for example, N-channel MOSFETs) via the motor coil 5.

  The energization control circuit 12 controls the H bridge circuit 11 to turn on and off the pair of the source transistor 1 and the sink transistor 4 and the pair of the source transistor 2 and the sink transistor 3 in a complementary manner. As a result, the direction of the drive current flowing through the motor coil 5 changes, and the motor is driven to rotate.

  When the overcurrent state detection circuit 13 detects an overcurrent state in which the current flowing through the transistors 1 to 4 exceeds a predetermined threshold due to an external factor, the overcurrent state detection circuit 13 has a logic level (hereinafter referred to as L level) indicating that fact. An overcurrent state detection signal DET is output. It should be noted that the overcurrent state is caused by external factors such as 1) when the source transistors 1 and 2 are turned on, and the respective source sides are shorted to the ground, or 2) when the sink transistors 3 and 4 are turned on. Occurs when each drain side is short-circuited to the power supply Vdd.

  When the overcurrent protection circuit 14 receives an L-level overcurrent state detection signal DET indicating that an overcurrent state has been detected from the overcurrent state detection circuit 13, in principle, all of the overcurrent protection circuit 14 configures the H bridge circuit 11. Overcurrent protection control for turning off the transistors 1 to 4 is performed. However, there is a possibility that an overcurrent state is erroneously detected by sudden noise (spike noise or the like) superimposed on the drive current. For this reason, the overcurrent protection circuit 14 includes all the transistors from when the overcurrent state is detected by the overcurrent state detection circuit 13 until the mask period set as the charging period in the mask period setting circuit 15 elapses. A mechanism for temporarily prohibiting overcurrent protection control for turning off 1 to 4 is provided.

  Note that an external capacitor 6 that is easy to attach and detach is mainly used for the mask period so that a free time can be set according to the usage state of the motor drive circuit 10. Specifically, the mask period setting circuit 15 includes a comparator 16, a constant current source 17, and a discharge transistor 18 (for example, an N-channel type MOSFET). The period from the zero level when not accumulated or the initial level corresponding to the charge when accumulated charges) to the reference voltage Vref1 is set as the mask period.

  More specifically, the discharging transistor 18 is turned off by the L-level overcurrent state detection signal DET indicating that an overcurrent state has been detected, and charging of the capacitor 6 from the constant current source 17 is started. Then, when the charging voltage of the capacitor 6 reaches the reference voltage Vref1 from the predetermined voltage, the mask period has elapsed, and the comparator 16 changes from the H level output to the L level output. Therefore, the overcurrent protection circuit 14 determines whether or not to perform overcurrent protection control that turns off all the transistors 1 to 4 based on the output logic level of the comparator 16.

  Hereinafter, the operation of the motor drive circuit 10 will be described based on the waveform diagram of main signals of the motor drive circuit 10 shown in FIG.

  First, at time TA, it is assumed that the overcurrent state detection circuit 13 does not detect an overcurrent state and outputs an H-level overcurrent state detection signal DET. In this case, complementary ON / OFF control for rotationally driving the motor by the energization control circuit 12 is performed on the transistors 1 to 4 constituting the H bridge circuit 11. In this case, since the discharging transistor 18 is turned on by the H-level overcurrent state detection signal DET, the capacitor 6 is not charged.

  Next, it is assumed that an overcurrent state caused by sudden noise is detected by the overcurrent state detection circuit 13 at time TB and an L-level overcurrent state detection signal DET is output. In this case, since the discharging transistor 18 is turned off by the L level overcurrent state detection signal DET, charging of the capacitor 6 is started. At time TB, the transistors 1 to 4 are subjected to complementary on / off control for rotating the motor as usual (a state where no overcurrent state has occurred) by the energization control circuit 12.

  Next, at time TC, since the overcurrent state detected at time TB is due to sudden noise, the overcurrent state detection circuit 13 determines that the overcurrent state is no longer detected, Assume that an H-level overcurrent state detection signal DET is output. In this case, since the discharge transistor 18 is turned on by the H level overcurrent state detection signal DET, the capacitor 6 that has been continuously charged from time TB is discharged.

  The capacitor 6 is charged during the period from time TB to time TC, but the mask period is set after the charging voltage of the capacitor 6 does not reach the reference voltage Vref1 and an overcurrent state is detected. The mask period of the circuit 15 has not elapsed. That is, the overcurrent protection circuit 14 determines that the overcurrent state detected between time TB and time TC is caused by noise, and temporarily performs overcurrent protection control to turn off all the transistors 1 to 4. Prohibit.

  Next, at time TD, the overcurrent state detection circuit 13 detects an overcurrent state caused by a short-circuit accident instead of noise and outputs an L-level overcurrent state detection signal DET. In this case, since the discharging transistor 18 is turned off by the L level overcurrent state detection signal DET, the charging of the capacitor 6 is started again. The transistors 1 to 4 perform complementary on / off operations for rotating the motor by the energization control circuit 12.

At time TE, the charging voltage of the capacitor 6 reaches the reference voltage Vref1, and the mask period set by the mask period setting circuit 15 elapses after the overcurrent state is detected at time TD. Then, with the passage of the mask period, the overcurrent protection circuit 14 performs the overcurrent protection control that stops the on / off control by the energization control circuit 12 and turns off all the transistors 1 to 4.
Japanese Patent Laid-Open No. 5-111144

  As described above, the motor drive circuit having the conventional overcurrent protection circuit is in excess of noise due to a period from when the overcurrent state is detected until the mask period set as the capacitor charging period elapses. Assuming that the current state is erroneously detected, an overcurrent protection control for temporarily turning off all the drive transistors is temporarily prohibited, and a mechanism for continuing on / off control of the drive transistor for rotationally driving the motor is provided.

  However, by providing such a mechanism, overcurrent protection control is temporarily prohibited during the mask period even though an overcurrent state caused by a short circuit accident rather than noise is detected. It will be. For this reason, when the mask period is set to be inappropriately long, there is a possibility of causing a failure of an overcurrent protection target (a motor coil, a drive transistor, etc.).

  Capacitors vary in capacitance, and the capacitance varies due to environmental conditions such as temperature. Moreover, the failure conditions for overcurrent protection also vary depending on the applied voltage, supply current, ambient temperature, and the like. For this reason, it has been difficult to appropriately set the length of the mask period as the capacitor charging period in order to suppress erroneous detection of an overcurrent state caused by noise.

  The main invention for solving the above problems is an energization control circuit for controlling on / off of a drive transistor connected to the motor coil to energize the motor coil, and an overcurrent in which a current flowing through the drive transistor exceeds a predetermined threshold value. An overcurrent state detection circuit for detecting whether or not a state is present, and when the overcurrent state is detected by the overcurrent state detection circuit, charging of the capacitor is started, and then the overcurrent state is detected. A charging / discharging circuit that discharges the capacitor in response to the fact that it is no longer performed, and until the charging period until the charging voltage of the capacitor exceeds a threshold voltage exceeds a threshold voltage. Stop the on-off control to turn off the drive transistor, after the charging period has passed, Serial and be provided with, and the overcurrent protection control circuit for determining whether to perform the overcurrent protection control for turning off the drive transistor by detecting the overcurrent state.

  ADVANTAGE OF THE INVENTION According to this invention, the motor drive circuit which performs an overcurrent protection appropriately can be provided.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

<<< Configuration of Motor Drive Circuit >>>
FIG. 1 is a block diagram showing a motor drive circuit according to an embodiment of the present invention. In FIG. 1, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted. In addition, in FIG. 1, a configuration surrounded by an alternate long and short dash line is a motor driving circuit 100 integrated on one chip, and a motor coil 5 and a capacitor 6 are connected to the outside of the motor driving circuit 100. To do.

  The motor drive circuit 100 includes an H bridge circuit 11, an overcurrent state detection circuit 110, an energization control circuit 120, a first monitoring circuit 130, a first control circuit 140, an overcurrent protection circuit 150, and a mask period setting circuit 15. ing. Further, the motor drive circuit 100 includes a second control circuit 160, a second monitoring circuit 170, and a third monitoring circuit 180. Note that the overcurrent protection circuit 150, the first control circuit 140, and the second control circuit 160 correspond to the overcurrent protection control circuit of this claim.

  When the overcurrent state detection circuit 110 detects an overcurrent state in which the current flowing through the transistors 1 to 4 exceeds a predetermined threshold due to an external factor, the overcurrent state detection circuit 110 outputs a logic level signal S1 indicating that fact. In the following, the H level signal S1 indicates that an overcurrent state has not been detected, and the L level signal S1 indicates that an overcurrent state has been detected. It should be noted that the overcurrent state is caused by external factors such as 1) when the source transistors 1 and 2 are turned on, and the respective source sides are shorted to the ground, or 2) when the sink transistors 3 and 4 are turned on. Occurs when each drain side is short-circuited to the power supply Vdd.

  The overcurrent state detection circuit 110 includes four comparators 111 to 114, four NAND gates 115 to 118, and one AND gate 119.

  In the comparator 111, a reference voltage Vref2 that is lower than the power supply voltage Vdd of the H-bridge circuit 11 by a predetermined voltage and lower than the source voltage when the source transistor 2 is on is applied to the + terminal, and the source transistor 2 is applied to the − terminal. The voltage at the connection point of the sink transistor 4 is applied. As a result, the output of the comparator 111 becomes L level when the source transistor 2 is turned on.

  In the comparator 112, the reference voltage Vref2 is applied to its + terminal, and the voltage at the connection point between the source transistor 1 and the sink transistor 3 is applied to its − terminal. The operation of the comparator 112 is the same as that of the comparator 111.

  In the comparator 113, a reference voltage Vref3 that is higher than the ground voltage of the H bridge circuit 11 by a predetermined voltage and higher than the drain voltage when the sink transistor 4 is on is applied to the negative terminal, and the source transistor 2 is applied to the positive terminal. The voltage at the connection point of the sink transistor 4 is applied. As a result, the output of the comparator 113 becomes L level when the sink transistor 4 is turned on.

  In the comparator 114, the reference voltage Vref3 is applied to the negative terminal, and the voltage at the connection point of the source transistor 1 and the sink transistor 3 is applied to the positive terminal. The operation of the comparator 114 is the same as that of the comparator 113.

  The NAND gates 115 to 118 perform a NAND operation using the drive signal output from the energization control circuit 120 and the outputs of the comparators 111 to 114. The AND gate 119 performs an AND operation on each output of the NAND gates 115 to 118, and outputs the result as a signal S1. That is, when an overcurrent state occurs, any one of the outputs of the NAND gates 115 to 118 becomes L level. Accordingly, in this case, the AND gate 119 outputs an L level signal S1 indicating that an overcurrent state has been detected.

  In addition to the embodiment described above, the overcurrent state detection circuit 110 is provided with a resistor between the H bridge circuit 11 and the ground point, and the voltage level generated between both terminals of the resistor exceeds the threshold voltage. The state may be detected as an overcurrent state.

  When the overcurrent state is not detected, the energization control circuit 120 performs energization control for flowing a drive current to the motor coil 5 to rotationally drive the motor by performing on / off control of the transistors 1 to 4 in a complementary manner.

  The first monitoring circuit 130 monitors whether or not the L level continues for the “first period” when the signal S1 becomes the L level. That is, when the signal S1 instantaneously changes from the H level to the L level and immediately returns to the H level, the on / off control of the transistors 1 to 4 for rotating the motor is stopped based on the L level signal S1. Is not preferred. Therefore, when it is monitored that the L level of the signal S1 continues for the first period, the energization control circuit 120 stops the on / off control of the transistors 1 to 4 for rotationally driving the motor, and the transistor 1 Turn off all -4.

  Note that the first monitoring circuit 130 of this embodiment is realized by a counter constituted by four D-type flip-flops (hereinafter referred to as DFFs) 131 to 134. Note that the number of DFFs is not limited to four, and is a number corresponding to the length of the first period. Each of the DFFs 131 to 134 has a D terminal and a / Q terminal connected thereto, the clock signal CLK is input to the C terminal of the first stage DFF 131, and the output of the / Q terminal of the DFFs 131 to 133 is the output of the next stage DFFs 132 to 134. Input to the C terminal. The signal S1 is input to the R terminals of the DFFs 131 to 134 through the NOR gate 141.

  For example, when the signal S1 becomes H level (when the overcurrent state is not detected), the DFFs 131 to 134 output the L level output of the NOR gate 141 (the Q terminal output of the RS flip-flop 142 is output by the L level initial reset signal S11). The signal S2 that is the output of the / Q terminal of the final stage DFF 134 maintains the H level. On the other hand, when the signal S1 becomes L level (when an overcurrent state is detected), the H level output of the NOR gate 141 (when the Q terminal output of the RS flip-flop 142 is at L level by the L level initial reset signal S11) ), The DFFs 131 to 134 are reset and the change of the / Q terminal of the first stage DFF 131 is sequentially input to the C terminals of the next stage DFFs 132 to 134 every time the clock signal CLK rises. When the signal S1 continues to be at the L level during the first period, the signal S2 changes from the H level to the L level. At this time, the motor drive circuit 100 determines that the first period set by the first monitoring circuit 130 has elapsed after the overcurrent detection by the overcurrent state detection circuit 110.

  When the signal S1 changes from the L level to the H level during the first period, the DFFs 131 to 134 are reset, and the signal S2 continues to be at the H level. Accordingly, when the signal S2 changes from the H level to the L level, the overcurrent state is detected by the overcurrent state detection circuit 110 (the signal S1 is at the L level), and the first monitoring circuit 130 sets the first current. It can be seen that the period of.

  The first control circuit 140 controls the energization control circuit 120 to stop the on / off control of the transistors 1 to 4 when the signal S2 output from the first monitoring circuit 130 becomes L level. The first control circuit 140 controls the energization control circuit 120 to store the level of the gate drive signal of the transistors 1 to 4 in the register 125 when the signal S <b> 2 becomes L level. Further, the first control circuit 140 performs control to turn off the discharging transistor 18 of the mask period setting circuit 15 and start charging the capacitor 6 when the signal S2 becomes L level. Furthermore, the first control circuit 140 performs control to turn off all the transistors 1 to 4 in conjunction with the start of charging of the capacitor 6. That is, the first control circuit 140 has a mask period set as a charging period until the charging voltage of the capacitor 6 reaches the reference voltage Vref1 from a predetermined voltage (0 level or initial level) when charging of the capacitor 6 starts. In the meantime, all the transistors 1 to 4 are turned off, and the energization in the H bridge circuit 11 is stopped.

  The first control circuit 140 of the present embodiment is mainly configured by a NOR gate 141, an RS flip-flop 142 whose reset input and set input are negative logic, a NAND gate 143, and an inverter 144. .

  The NOR gate 141 receives the signal S1 output from the overcurrent state detection circuit 110 and the Q terminal output of the RS flip-flop 142. That is, the NOR gate 141 constitutes the first monitoring circuit 130 when the signal S1 becomes H level indicating that the overcurrent state is not detected (when the output of the Q terminal of the RS flip-flop 142 is ignored). The L level that resets the DFFs 131 to 134 is output. On the other hand, when the signal S1 becomes the L level indicating that the overcurrent state is detected (when the Q terminal output of the RS flip-flop 142 is ignored), the NOR gate 141 releases the reset of the DFFs 131 to 134. Is output.

  By the way, after the reset of the DFFs 131 to 134 is released, when the signal S2 output from the / Q terminal of the final stage DFF 134 changes from the H level to the L level (when the first period has elapsed), the RS flip-flop 142 Since the signal S2 is input to the / S terminal, the Q terminal output of the RS flip-flop 142 input to the NOR gate 141 changes from the L level to the H level. Therefore, after resetting the DFFs 131 to 134, the NOR gate 141 outputs an L level that resets the DFFs 131 to 134 again. That is, when an overcurrent state is detected by the overcurrent state detection circuit 110 and the first period set by the first monitoring circuit 130 has elapsed, the signal S2 has an L-level one-shot waveform.

  In the RS flip-flop 142, the signal S2 is input to the / S terminal, and the initial reset signal S11 is input to the / R terminal via the AND gate 163. The initial reset signal S11 is a signal that becomes L level at the time of initial reset and then becomes H level. Accordingly, the RS flip-flop 142 is in a reset state when the L-level initial reset signal S11 is input to the / R terminal via the AND gate 163 (when the signal S8 is at the H level), and then until the set state is reached. The signal S3 of H level is continuously output from the / Q terminal. Further, the RS flip-flop 142 is set when the L level signal S2 output from the first monitoring circuit 130 is input to the / S terminal, and then remains at the L level from the / Q terminal until it is reset. Continue to output signal S3.

  The energization control circuit 120 stops the on / off control of the transistors 1 to 4 when the L level signal S3 output from the RS flip-flop 142 is received, and stores the on / off states of the transistors 1 to 4 in the register 125. After that, all the transistors 1 to 4 are turned off. Specifically, the logic level (ON is 1 and OFF is 0) of the gate drive signal that turned on / off the transistors 1 to 4 when the on / off control of the transistors 1 to 4 is stopped is stored in the register 125 as the on / off state. Let The following description of the on / off state also means the logic level of the gate drive signals of the transistors 1 to 4.

  When the signal S9 is at the H level, the NAND gate 143 outputs a signal S4 obtained by inverting the Q terminal output of the RS flip-flop 142 toward the gate electrode of the discharging transistor 18 of the mask period setting circuit 15. That is, when the overcurrent state is not detected or when the first period has not elapsed even when the overcurrent state is detected (when the signal S2 is at the H level), the capacitor 6 is discharged by the H level signal S4. . When an overcurrent state is detected and the first period has elapsed (when the signal S2 has an L-level one-shot waveform), the capacitor 6 is charged by the L-level signal S4.

  The inverter 144 inverts the signal S3 and performs output for controlling the overcurrent protection circuit 150.

  The overcurrent protection circuit 150 detects the overcurrent state based on the output of the inverter 144 constituting the first control circuit 140 and the transistor 1 with respect to the energization control circuit 120 when the first period has elapsed. Control is performed to turn off all .about.4. At the same time, the mask period setting circuit 15 starts charging the capacitor 6 by the L level signal S4 output from the first control circuit 140. Therefore, the overcurrent protection circuit 150 is configured such that when a mask period set as a charging period from when all of the transistors 1 to 4 are turned off until the charging voltage of the capacitor 6 reaches the reference voltage Vref1 from a predetermined voltage has elapsed. Control is performed to restore the on / off states of the transistors 1 to 4 stored in 125.

  Note that the overcurrent protection circuit 150 of this embodiment is mainly realized by the NAND gate 151 and the AND gate 154.

  The NAND gate 151 receives the inverted output of the signal S3 from the inverter 144 and the signal S10 output from the comparator 16. That is, when an overcurrent state is detected and the first period has elapsed, an L level signal S5 for turning off the transistors 1 to 4 is output to the energization control circuit 120. Thereafter, when the charging voltage of the capacitor 6 reaches the reference voltage Vref1 and the logic level of the signal S10 output from the comparator 16 changes from the H level to the L level, an H level signal S5 for turning on the transistors 1 to 4 is generated. Output. At this time, the energization control circuit 120 reads the ON / OFF state of the transistors 1 to 4 (the logic level of the gate drive signal at the time of overcurrent detection) stored in the register 125, and determines the ON / OFF state of the transistors 1 to 4. The read on / off state is restored.

  The second monitoring circuit 170 confirms that the outputs of the transistors 1 to 4 can be stably obtained after returning the state of the transistors 1 to 4 to the on / off state stored in the register 125 after the mask period has elapsed. A “second period” for compensation is set.

  Note that the second monitoring circuit 170 of this embodiment is realized by two DFFs 171 and 172. The DFFs 171 and 172 each have a Q terminal and a D terminal connected thereto, and a clock signal CLK is input to each C terminal. The signal S6 output from the AND gate 153 is input to the D terminal of the DFF 171 and inverted and input to the R terminals of the DFFs 171 and 172.

  Here, the NOR gate 152 receives the signal S3 output from the RS flip-flop 142 and the signal S10 output from the comparator 16. The AND gate 153 receives the output of the NOR gate 152 and the signal S9 output from the RS flip-flop 162. For this reason, the signal S6 output from the AND gate 153 changes from the L level to the H level after the mask period has elapsed. When the signal S6 becomes H level, the DFFs 171 and 172 are released from the reset state, and every time the DFF 171 in the first stage rises the clock signal CLK, the change from the H level to the L level of the Q terminal changes to the D of the next stage DFF 172. Input to the terminal. Then, after the signal S6 changes from the L level to the H level, when the signal S7 output from the / Q terminal of the DFF 172 changes from the H level to the L level, the second period has elapsed.

 Note that, even after the second period, even if the signal S1 is at the H level indicating that an overcurrent state is not detected, the signal S1 at the H level may be instantaneous. Therefore, the third monitoring circuit 180 monitors whether or not the H level of the signal S1 continues the “third period” after the second period has elapsed.

  Note that the third monitoring circuit 180 of this embodiment is realized by two DFFs 181 and 182. The DFFs 181 and 182 each have a Q terminal and a D terminal connected thereto, and a clock signal CLK is input to each C terminal. The signal S6 is inverted and input to the R terminals of the DFFs 181 and 182, and the D terminal of the DFF 181 is connected to the Q terminal of the DFF 172 constituting the second monitoring circuit 170. If the overcurrent state is not detected and the signal S1 is at the H level, the signal S6 is also at the H level, and the DFFs 181 and 182 continue to release the reset. Therefore, after the elapse of the second period, when the H level is input from the Q terminal of the DFF 172 to the D terminal of the DFF 181 and the L level signal S8 is output from the / Q terminal of the DFF 182, the H level of the signal S1 is It will be continued for the third period.

  The second control circuit 160 performs overcurrent protection control that turns off the transistors 1 to 4 with respect to the energization control circuit 120 when an overcurrent flows after the second period and the signal S1 is at the L level. Make a decision to do. On the other hand, when no overcurrent flows and the signal S1 is at the H level, and the H level of the signal S1 continues for the third period, it is decided not to perform the overcurrent protection control, and the energization control circuit 120 performs the on / off control. The process is resumed from the on / off state stored in the register 125.

  Note that the second control circuit 160 of the present embodiment is mainly realized by an OR gate 161, an RS flip-flop 162, and an AND gate 163.

  The OR gate 161 receives the signal S7 output from the second monitoring circuit 170 and the signal S1 output from the overcurrent state detection circuit 110. The signal S7 becomes L level when the second period has elapsed after the mask period has elapsed. That is, until the second period elapses after the mask period elapses, the output of the OR gate 161 is fixed to the H level by the H level signal S7 regardless of the output of the signal S1. When the signal S7 becomes L level after the second period has elapsed, the output of the OR gate 161 becomes an output corresponding to the logic level of the signal S1.

  In the RS flip-flop 162, the output of the OR gate 161 is input to the / S terminal, and the initial reset signal S11 is input to the / R terminal. Therefore, the RS flip-flop 162 outputs the signal S9 at the L level when the signal S1 is at the H level when the signal S7 becomes the L level after the second period has elapsed.

  The AND gate 163 receives the initial reset signal S11 and the signal S8 output from the third monitoring circuit 180. That is, the output of the AND gate 163 becomes the H level when the third period has passed and the L level signal S8 is output. The H level output from the AND gate 163 is input to the R terminal of the RS flip-flop 142. As a result, the signal S3 becomes H level, and the on / off control of the stopped transistors 1 to 4 is resumed.

  Corresponding to the second control circuit 160, the overcurrent protection circuit 150 further includes a NOR gate 152 and an AND gate 153 in addition to the NAND gate 151 and the AND gate 154 described above.

  The NOR gate 152 receives the signal S3 output from the RS flip-flop 142 and the signal S10 output from the comparator 16. That is, the NOR gate 152 outputs the L level when the overcurrent state is not detected, and outputs the L level until the mask period elapses when the overcurrent state is detected, and the mask period elapses. Later, H level is output.

  The AND gate 153 receives the output of the NOR gate 152 and the signal 9 output from the RS flip-flop 162. That is, the signal S6 output from the AND gate 153 becomes H level after the mask period elapses, and becomes L level when the signal S1 after elapse of the second period is L level, and the signal S1 after elapse of the second period. Is at the H level until the third period elapses.

<<< Operation of Motor Drive Circuit 100 >>>
The operation of the motor drive circuit 100 shown in FIG. 1 will be described using the flowchart shown in FIG. 2 with reference to waveform diagrams of main signals of the motor drive circuit 100 shown in FIGS.

  First, suppose that no noise or short circuit accident has occurred. In this case, the signal S1 output from the overcurrent state detection circuit 110 is at H level, and the energization control circuit 120 performs on / off control of the transistors 1 to 4 for rotationally driving the motor (S100). For example, this is the state shown at time T0 in FIG.

  Next, it is assumed that noise or a short circuit accident occurs and an overcurrent flows through the transistors 1 to 4 and the signal S1 output from the overcurrent state detection circuit 110 becomes L level (S101: YES). In this case, the first monitoring circuit 130 monitors whether or not the L level of the signal S1 continues for the first period (S102). For example, this is the state shown at time T1 and time T3 in FIG.

  Here, it is assumed that the L level of the signal S1 does not continue for the first period and the signal S2 output from the first monitoring circuit 130 continues to be the H level (S102: NO). For example, this is a state from time T1 to time T2 in FIG. In this case, it is determined that the overcurrent state detected by the overcurrent state detection circuit 110 is caused by noise. Then, the on / off control of the transistors 1 to 4 for rotationally driving the motor is continued (S100).

  On the other hand, it is assumed that the L level of the signal S1 continues for the first period, and the signal S2 output from the first monitoring circuit 130 changes from the H level to the L level (S102: YES). For example, this is a state from time T3 to time T4 in FIG. In this case, it is determined that the overcurrent state detected by the overcurrent state detection circuit 110 is caused by a short circuit accident rather than noise. Then, the first control circuit 140 stores the ON / OFF state of the transistors 1 to 4 in the register 125 when the first period has elapsed, starts charging the capacitor 6, and turns off the transistors 1 to 4. The energization of the circuits 11 is stopped all at once (S103). For example, this is the state shown at time T4 in FIG.

  Next, after the charging of the capacitor 6 starts, when the charging voltage of the capacitor 6 reaches from the predetermined voltage to the reference voltage Vref1 and the mask period elapses (S104), the first control circuit 140 registers the transistors 1-4. The on / off state stored in 125 is restored (S105). For example, this is the state shown at time T5 in FIG. 3 or FIG.

  Next, assume that a second period set by the second monitoring circuit 170 has elapsed after the mask period has elapsed (S106). For example, it is a state from time T5 to time T6 in FIG. 3 or FIG.

  Here, when the overcurrent flows through the transistors 1 to 4 when the second period has elapsed and the signal S1 output from the overcurrent state detection circuit 110 is at the L level (S107: YES), all the transistors 1 to 4 are turned on. It is determined to perform overcurrent protection control to be turned off (S108). For example, this is the state shown at time T6 in FIG.

  On the other hand, when the short circuit accident is resolved during the mask period and the signal S1 output from the overcurrent state detection circuit 110 is at the H level when the second period elapses (S107: NO), the third monitoring circuit 180 is Then, it is monitored whether or not the H level of the signal S1 continues for the third period (S109). For example, this is the state shown at time T6 in FIG.

  Here, when it is monitored that the H level of the signal S1 when the second period has elapsed continues for the third period (S109: YES), it is determined not to perform the overcurrent protection control, and the transistors 1 to 4 are The on / off control is resumed from the on / off state stored in the register 125. For example, this is the state shown from time T6 to time T7 in FIG.

  On the other hand, when it is not monitored that the H level of the signal S1 at the time of the second period has continued for the third period (S109: NO), the logic level of the signal S1 is confirmed again (S107).

  From the above, until the mask period elapses from the detection of the overcurrent state, all the transistors 1 to 4 in the H bridge circuit 11 are turned off and the energization of the H bridge circuit 11 is stopped. That is, according to the conventional overcurrent protection method, overcurrent protection was not performed until detection of an overcurrent state continued for the mask period to prevent erroneous detection due to noise. Even if there are, all the transistors 1 to 4 are temporarily turned off. Therefore, even if the capacitor 6 is inappropriately selected and a long mask period is set inappropriately as overcurrent protection, the overcurrent protection target can be reliably protected.

  Further, by monitoring whether or not the overcurrent state continues for the first period by the first monitoring circuit 130, the overcurrent state detected by the overcurrent state detection circuit 110 is caused by noise or short-circuited. It is possible to determine whether it is caused by an accident. Therefore, even when an overcurrent state caused by noise is detected, it is not necessary to stop the energization of the H-bridge circuit 11 during the mask period, so that a reduction in the operating rate of the motor can be suppressed.

  Further, when the energization of the H-bridge circuit 11 is stopped during the mask period, the on / off states of the transistors 1 to 4 when the first period has elapsed are stored in the register 125. Therefore, the transistors 1 to 4 can be smoothly returned to the on / off state when the first period elapses after the mask period elapses.

  In addition, when the overcurrent state caused by the short-circuit accident continues during the mask period, the transistors 1 to 4 that are turned off when the mask period elapses are returned to the on / off state when the overcurrent is detected. Since the short-circuit accident has not been solved at all, an overcurrent state occurs again. Therefore, a mechanism is provided for monitoring whether or not the overcurrent state has been continuously detected after the mask period has elapsed.

  Specifically, the determination is made based on the logic level of the signal S1 generated when the transistors 1 to 4 that have been turned off are returned to the on / off state. At this time, a second period set by the second monitoring circuit 170 is a period from when the transistors 1 to 4 are restored to the on / off state at the elapse of the first period until the logic level of the signal S1 is determined. Is provided. As a result, the logic level of the signal S1 is not judged during the second period in which the outputs of the transistors 1 to 4 are unstable immediately after the transistors 1 to 4 are restored to the on / off state at the time of the first period. Thus, it becomes possible to more reliably detect the overcurrent state.

  Further, when the signal S1 is at the H level even after the second period has elapsed, it is determined not to perform the overcurrent protection control for turning off all the transistors 1 to 4, and the transistors 1 to 1 by the energization control circuit 120 are determined. 4 on / off control is resumed. Specifically, when the H level of the signal S1 continues for the third period set by the third monitoring circuit 180, the on / off control of the transistors 1 to 4 is resumed. As a result, when the period during which the signal S1 is at the H level is momentary that is less than the third period, it is not necessary to erroneously restart the on / off control of the transistors 1 to 4, so that the overcurrent state can be detected. This can be performed more reliably.

  As mentioned above, although one embodiment concerning the present invention was described, explanation of the above-mentioned embodiment is for making an understanding of the present invention easy, and does not limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes the equivalents.

It is a figure which shows the structure of the motor drive circuit which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the motor drive circuit which concerns on one Embodiment of this invention. It is a wave form diagram of the main signal of the motor drive circuit concerning one embodiment of the present invention. FIG. 6 is another waveform diagram of main signals of the motor drive circuit according to the embodiment of the present invention. It is a figure which shows the structure of the conventional motor drive circuit. It is a wave form diagram of the main signal of the conventional motor drive circuit.

Explanation of symbols

1, 2 source transistor 3, 4 sink transistor 5 motor coil 6 capacitor 15 charge / discharge circuit 110 overcurrent state detection circuit 120 energization control circuit 125 register 130 first monitoring circuit 140 first control circuit 150 overcurrent protection circuit 160 second Second control circuit 170 Second monitoring circuit 180 Third monitoring circuit

Claims (5)

An energization control circuit for controlling on / off of a drive transistor connected to the motor coil to energize the motor coil;
An overcurrent state detection circuit for detecting whether or not the current flowing through the driving transistor is in an overcurrent state exceeding a predetermined threshold;
A charge / discharge circuit that starts charging the capacitor when the overcurrent state is detected by the overcurrent state detection circuit and then discharges the capacitor when the overcurrent state is no longer detected; ,
Until the charging period until the charging voltage of the capacitor exceeds a threshold voltage from a predetermined voltage, the on / off control of the driving transistor by the energization control circuit is stopped to turn off the driving transistor, and the charging An overcurrent protection control circuit for determining whether to perform overcurrent protection control for turning off the drive transistor by detecting the overcurrent state after a period of time has elapsed;
A motor drive circuit comprising: The motor drive circuit according to claim 1, comprising a first monitoring circuit that monitors whether or not the overcurrent state detected by the overcurrent state detection circuit continues for a first period,
The overcurrent protection control circuit is configured to control the energization control until the charging period elapses when it is monitored by the first monitoring circuit that the overcurrent state continues for the first period. An on / off control of the driving transistor by the circuit is stopped to turn off the driving transistor. In the motor drive circuit according to claim 2,
The overcurrent protection control circuit stores an on / off state of the driving transistor when the first monitoring circuit monitors that the overcurrent state continues for the first period, and the charging period is A motor drive circuit characterized by determining whether or not to perform the overcurrent protection control after restoring the stored on / off state from the off state when the drive transistor is turned off. In the motor drive circuit according to claim 3,
A second monitoring circuit for monitoring whether or not the overcurrent state detected by the overcurrent state detection circuit continues for a second period after returning the drive transistor to the stored on / off state. With
The overcurrent protection control circuit determines to perform the overcurrent protection control when the second monitoring circuit monitors that the overcurrent state continues for the second period. circuit. In the motor drive circuit according to claim 4,
A third monitoring circuit for monitoring whether or not the overcurrent state continues in the overcurrent state detection circuit for a third period after the second period has elapsed;
The overcurrent protection control circuit decides not to perform the overcurrent protection control when the third monitoring circuit monitors that the overcurrent state does not continue for the third period, and performs the energization control. A motor driving circuit, wherein the on / off control of the driving transistor by the circuit is resumed from an on / off state that has been restored.

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