JP2009135717A - DeltaSigma MODULATION DEVICE, CUTOFF METHOD, PROGRAM, AND RECORDING MEDIUM - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce pop noise occurring when muting a ΔΣ modulated signal. <P>SOLUTION: A ΔΣ-modulation digital amplifier 100 is provided with a selection circuit 140 for cutting off transmission of switching signals #51 and #52 being ΔΣ modulated signals. The selection circuit 140 cuts off transmission of the switching signals #51 and #52 by control of a mute control circuit 180 when a primary integral value calculated by an integrator circuit 110 is within a prescribed range including zero. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for reducing pop noise generated when a ΔΣ modulation signal is muted in a ΔΣ modulation device.

  In audio equipment, abnormal sounds such as “pops” or “bottoms” that occur during mute can be a problem that affects the evaluation of the equipment. Such abnormal sounds are called “pop sounds” or “pop noises”, and the generation factors include transient phenomena that occur in each part of the circuit as the transmission of the audio signal is interrupted.

  A ΔΣ modulation type digital amplifier that has been widely used in recent years may generate a pop sound when transmission of a ΔΣ modulation signal is cut off. Hereinafter, the pop sound generated by the ΔΣ modulation type digital amplifier will be briefly described for each of the cases where the single-bridge type switching circuit and the double-bridge type switching circuit are used as the amplifier circuit.

  FIG. 8 is a block diagram showing a typical configuration of a ΔΣ modulation type digital amplifier using a single-bridge type switching circuit as an amplifier circuit. The ΔΣ modulation digital amplifier 10 shown in FIG. 8 includes a ΔΣ modulation circuit 11, an LPF (low-pass filter) 13, and a capacitor 14 in addition to the amplifier circuit 12.

The ΔΣ modulation circuit 11 generates a ΔΣ modulation signal as a switching signal # 2 for driving the amplifier circuit 12 by performing ΔΣ modulation on the input signal # 1 that is an analog signal. The switching signal # 2 is a binary digital signal that takes a value of “0” or “1”, and is a PDM signal (pulse density modulation signal) that represents the level of the input signal # 1 by the pulse density. More specifically, the difference D−D ₀ between the pulse density D of the switching signal # 2 and the reference pulse density D ₀ is proportional to the level of the input signal # 1. In the case of the one-bridge type, generally, the reference pulse density D ₀ is 0.5 (the frequency at which the value “1” is taken matches the frequency at which the value “0” is taken).

  The amplifier circuit 12 is a one-bridge type switching circuit configured by two switching elements 12a and 12b connected in series. The switching signal # 2 is supplied to the switching element 12a, and the switching signal is supplied to the switching element 12b. An inverted switching signal 2b obtained by inverting # 2 is input.

  When the switching signal # 2 takes the value “1”, the switching element 12a is controlled to be in a conductive state, and the switching element 12b is controlled to be in a cutoff state. As a result, the output potential Vp of the amplifier circuit 12 matches the power supply voltage Vc. On the other hand, when the switching signal # 2 takes the value “0”, the switching element 12a is controlled to be in a cut-off state, and the switching element 12b is controlled to be in a conductive state. As a result, the output potential Vp of the amplifier circuit 12 matches the ground potential.

The LPF 13 includes the direct current component V ₀ corresponding to the reference pulse density D ₀ and the alternating current component obtained by substantially faithfully amplifying the input signal # 1 by smoothing the switching signal # 3 thus amplified. Output signal # 4 is obtained. For example, when the reference pulse density D ₀ is 0.5, the direct current component V ₀ is half the peak value of the switching pulse # 3. By removing the DC component V ₀ contained in the output signal # 4 by the capacitor 14, an analog signal obtained by substantially faithfully amplifying the input signal # 1 is obtained.

Incidentally, in the ΔΣ modulation digital amplifier 10 with an amplifier circuit 12, even after the input signal # 1 level becomes 0, the switching signal # 2 having a reference pulse density D ₀ is continuously supplied to the amplifier circuit 12 ing. Therefore, even after the input signal # 1 level reaches zero, the output signal # 4, includes a DC component V ₀ corresponding to the reference pulse density D ₀ (see FIG. 9 top), a capacitor 14 the charge is accumulated in proportion to the DC component V _0.

Therefore, when the transmission of the switching signal # 2 is cut off, the output potential V _{pLPF of the LPF 13} suddenly drops to the ground potential, and a reverse voltage proportional to the charge stored in the capacitor 14 is applied to the load 50 (FIG. 9). See below). This reverse voltage causes a loud pop sound.

  As a technique for reducing a pop sound generated by a ΔΣ modulation digital amplifier using a single-bridge switching circuit as an amplifier circuit, for example, the technique disclosed in Patent Document 1 is known.

  Patent Document 1 discloses a technique for switching and outputting a PDM signal obtained by subjecting an input signal to ΔΣ modulation and a PDM signal obtained by subjecting a transition signal to ΔΣ modulation during silencing. As the transition signal, an analog signal whose level smoothly decreases is used. As a result, the pulse density of the output PDM signal is smoothly reduced, and the direct current component is also smoothly reduced toward the ground potential, so that the pop sound generated during mute is reduced.

  FIG. 10 is a block diagram showing a typical configuration of a ΔΣ modulation type digital amplifier using a double-bridge type switching circuit as an amplifier circuit. The ΔΣ modulation type digital amplifier 20 shown in FIG. 10 includes a ΔΣ modulation circuit 21 and an LPF 23 in addition to the amplification circuit 22.

  The ΔΣ modulation circuit 21 performs ΔΣ modulation on the input signal # 1 that is an analog audio signal, thereby generating a ΔΣ modulation signal as a positive switching signal # 2a and a negative switching signal # 2b for driving the amplifier circuit 12. Is generated. The positive and negative switching signals # 2a and # 2b are digital signals each having a value of “0” or “1”, and are PDM signals that represent the level of the input signal # 1 by the difference in pulse density. More specifically, a pulse density difference obtained by subtracting the pulse density of the negative switching signal # 2b from the pulse density of the positive switching signal # 2a is proportional to the level of the input signal # 1.

The amplifier circuit 22 is a double-bridge type switching circuit including a single-bridge type switching circuit 22a driven by a positive switching signal # 2a and a single-bridge type switching circuit 22b driven by a negative switching signal # 2b. is there. Difference in these two load connected between single bridge switching circuit (LPF 23 and the load 50), the output potential V _p pieces bridge type switching circuit 22a, the output potential V _n pieces bridge type switching circuit 22b V _p −V _n is applied.

When the positive switching signal # 2a takes the value “1” and the negative switching signal # 2b takes the value “0”, the voltage V _p −V _n applied to the load matches the power supply voltage V _c . When both the positive and negative switching signals # 2a and # 2 take the value “0”, the voltage V _p −V _n applied to the load is 0V. Further, when the positive and negative switching signals # 2a and # 2b have the value “0” when the positive switching signal # 2a takes the value “1” and the negative switching signal # 2b takes the value “1”, the voltage V _p − applied to the load. V _n is equal to the -V _c.

  The LPF 23 obtains output signals # 4a and # 4b by smoothing the switching signals # 3a and # 3b thus amplified. As a difference between the output signal # 4a and the output signal # 4b, an analog signal obtained by substantially faithfully amplifying the input signal # 1 is obtained.

In such a ΔΣ modulation type digital amplifier 20, since the potential difference V _S = V _pLPF −V _nLPF between the output potentials V _pLPF and V _nLPF of the _{LPF 23} is applied to the load, the output signal # 4a and the output signal # 4b Even if the same DC components are included in each other, they cancel each other and do not have an effective effect on the load (see FIG. 11). For this reason, even if the transmission of the switching signals # 2a and # 2b is cut off, a loud pop sound is not generated unlike the case where the single bridge type switching circuit is used as the amplifier circuit.

As a ΔΣ modulation type digital amplifier using a double bridge type switching circuit as an amplifier circuit, for example, the one of Patent Document 2 is known. Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for satisfactorily performing output silencing with a simple configuration by appropriately controlling switching elements constituting both bridge type switching circuits.
JP 2006-109275 (April 20, 2006) JP 2004-135061 (April 30, 2004)

  However, the conventional ΔΣ modulation type digital amplifier has a problem that when a transmission of a ΔΣ modulation signal (switching signal) is cut off for the purpose of silencing, a pop sound is generated due to a quantization error of the ΔΣ modulation. It was. A more detailed explanation of this problem is as follows.

  In the case of a delta-sigma modulation type digital amplifier using both bridge type switching circuits in the amplifier circuit, the positive / negative switching signal (delta-sigma modulation signal) generated by the delta-sigma modulation is a PDM signal whose pulse density difference is proportional to the level of the input signal. is there. Therefore, if the level of the input signal is 0, the pulse density difference between the positive and negative switching signals is ideally 0. However, since ΔΣ modulation always involves a quantization error, even if the level of the input signal is 0, the pulse density difference between the positive and negative switching signals does not actually become 0. For this reason, even after the level of the input signal becomes 0, a voltage corresponding to the pulse density difference due to the quantization error is continuously applied to the load. Accordingly, when transmission of the switching signal is interrupted, a discontinuous change in the voltage applied to the load occurs, and a pop sound is generated.

  The problem of pop noise caused by the quantization error of ΔΣ modulation also exists in a ΔΣ modulation digital amplifier using a one-bridge switching circuit as an amplifier circuit. For example, even when a PDM signal obtained by ΔΣ modulation of a transition signal is used for silencing as in the technique described in Patent Document 1, a pop sound is generated when the PDM signal is finally stopped. End up. This means that no matter how small the level of the transition signal is, the generation of the switching pulse that occurs as a quantization error cannot be completely stopped, and therefore the DC voltage applied to the load may be completely 0V. This is because it cannot be done.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a ΔΣ modulator that can suppress a pop sound generated when the transmission of a ΔΣ modulation signal in the ΔΣ modulator is cut off to a certain level or less. Is to realize.

  In order to solve the above-described problem, the ΔΣ modulation apparatus according to the present invention includes a first-order integral value obtained by integrating a difference value between an input signal and a fed-back ΔΣ modulation signal, or a high-order value obtained by further integrating the first-order integral value. In a ΔΣ modulation device that generates a ΔΣ modulation signal by quantizing a quadratic integral value, when the first-order integral value is within a predetermined range including 0, a cutoff unit that cuts off transmission of the ΔΣ modulation signal is provided. It is characterized by that.

  In the above configuration, the difference value between the input signal and the fed back ΔΣ modulation signal represents a quantization error in ΔΣ modulation. Therefore, the primary integration value represents the magnitude of quantization error in ΔΣ modulation.

  Therefore, according to the above configuration, transmission of the ΔΣ modulation signal is blocked while the magnitude of the quantization error in ΔΣ modulation is below a certain level. Therefore, there is an effect that when the transmission of the ΔΣ modulation signal is cut off, the pop sound generated due to the quantization error in the ΔΣ modulation can be suppressed to a certain level or less.

  The predetermined range may be a numerical value range including a preset 0, that is, the upper limit value may be a positive value and the lower limit value may be a negative value. It is not necessary that the value and the absolute value of the lower limit coincide with each other. In addition, if the said range is set narrower, the upper limit level of the generated pop sound can be made smaller.

  The ΔΣ modulation apparatus according to the present invention further includes a cutoff period determining unit that determines a cutoff period in which transmission of the ΔΣ modulation signal is continuously blocked by the cutoff unit based on a given mute command and the first-order integral value. It is preferable that the start point of the shut-off period is a time point when the first-order integral value first falls within the range after the mute command is given.

  According to the above configuration, under the condition that the pop sound generated when the transmission of the ΔΣ modulation signal is interrupted is kept below a certain level, the transmission of the ΔΣ modulation signal starts to be interrupted after the mute command is given. The delay until it is done can be minimized. That is, there is a further effect of minimizing a decrease in response to the mute command.

  In the delta-sigma modulation apparatus according to the present invention, it is preferable that the end point of the cutoff period is a time point when the mute command is canceled.

  According to the above configuration, once transmission of the ΔΣ modulation signal is interrupted, transmission of the ΔΣ modulation signal continues to be interrupted until the mute command is canceled. For this reason, before the mute command is canceled, the transmission of the ΔΣ modulation signal is started again, and there is an additional effect that the useless operation of interrupting the transmission again is eliminated.

The cutoff period determining means as described above includes, for example, a calculation circuit that calculates the absolute value of the primary integral value, a comparison circuit that compares the absolute value and the absolute value with a preset threshold value, And a determination circuit that determines whether or not to block the ΔΣ modulation signal. If the threshold value (positive value) is expressed as W _th , the comparison circuit determines whether or not the primary integration value is included in a predetermined range including 0 (that is, a range from −W _th to + W _th ). Will be judged.

  The determination circuit includes an OR gate that obtains a logical sum of the previous decision result of the decision circuit and the comparison result of the comparison circuit, and an AND gate that obtains a logical product of the output of the OR gate and the mute command. And can be configured. Note that the determination circuit may include a D flip-flop that holds the previous determination result of the determination circuit.

  Further, the cutoff period determining means as described above includes, for example, a comparison circuit that determines whether or not the primary integration value is within the range, and a determination circuit that determines whether or not to block the ΔΣ modulation signal. It can also comprise. In this case, the determination circuit calculates an OR gate of the logical sum of the previous determination result of the determination circuit and the determination result of the comparison circuit, and the logical product of the output of the OR gate and the mute command. An AND gate can be used.

  In the ΔΣ modulation apparatus according to the present invention, the blocking means is a selection circuit that is provided on the transmission path of the ΔΣ modulation signal and selects and outputs either the ΔΣ modulation signal or the zero signal. It is preferable that the transmission of the ΔΣ modulation signal is blocked by selecting a signal.

  According to said structure, there exists the further effect that transmission of the said (DELTA) (SIGMA) modulation signal can be interrupted | blocked reliably.

  In order to solve the above-described problem, a blocking method according to the present invention includes a first-order integral value obtained by integrating a difference value between an input signal and a feedback ΔΣ modulation signal, or a higher-order order obtained by further integrating the first-order integral value. In a delta-sigma modulation device that generates a delta-sigma modulation signal by quantizing an integral value, a blocking method for blocking transmission of the generated delta-sigma modulation signal, wherein the primary integration value is within a predetermined range including zero A blocking step of blocking transmission of the ΔΣ modulation signal.

  According to the above configuration, similarly to the ΔΣ modulation device, when the transmission of the ΔΣ modulation signal is cut off, the pop sound generated due to the quantization error in the ΔΣ modulation is suppressed to a certain level or less. There is an effect that can be.

  The ΔΣ modulator may be realized as a digital signal processor (DSP). In this case, a program that causes the digital signal processor to function as each of the above-described means to cause the digital signal processor to operate as a ΔΣ modulator and a recording medium that records the program are also included in the scope of the present invention.

  The ΔΣ modulation apparatus according to the present invention provides the ΔΣ modulation signal when the first-order integration value obtained by integrating the difference value between the input signal and the fed back ΔΣ modulation signal is within a predetermined range including zero. Is provided with a blocking means for blocking the transmission of.

  Also, in the blocking method for blocking transmission of the ΔΣ modulation signal according to the present invention, the first-order integral value obtained by integrating the difference value between the input signal and the fed back ΔΣ modulation signal is a predetermined range including zero. A blocking step for blocking the transmission of the ΔΣ modulation signal.

  Therefore, when the transmission of the ΔΣ modulation signal is cut off, the pop sound generated due to the quantization error in the ΔΣ modulation can be suppressed to a certain level or less.

  A ΔΣ modulation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

  Since the ΔΣ modulation circuit according to the present embodiment is configured as a digital amplifier having an amplification function, the ΔΣ modulation circuit is hereinafter referred to as a “ΔΣ modulation digital amplifier”. Such a ΔΣ modulation circuit is sometimes called a “1-bit amplifier”.

(Basic configuration of ΔΣ modulation type digital amplifier)
First, the basic configuration of the ΔΣ modulation type digital amplifier 100 according to the present embodiment will be described with reference to FIG.

  FIG. 1 is a block diagram showing a configuration of a ΔΣ modulation type digital amplifier 100. Generally speaking, the ΔΣ modulation digital amplifier 100 is a digital amplifier that differentially drives a load such as a speaker by performing ΔΣ modulation on the input signal # 1 and amplifying the obtained ΔΣ modulation signal. The input signal # 1 may be an analog signal or a digital signal such as a PCM (Pulse Code Modulation) signal.

  As shown in FIG. 1, the ΔΣ modulation type digital amplifier 100 includes an integration circuit 110, a quantization circuit 120, a pulse width widening circuit 130, a selection circuit 140, a delay circuit 150, an amplification circuit 160, an LPF (low pass filter) 170, In addition, a mute control circuit 180 is provided.

  The integrating circuit 110 integrates a difference signal # 20 that is a difference value between the value of the input signal # 10 and the delayed switching signal # 60. The integration circuit 110 may calculate a primary integration value obtained by integrating the difference signal # 20, or may calculate a high-order integration value obtained by further integrating the primary integration value. The integration value output from the integrator 110 for each operation clock is supplied to the quantization circuit 120 as an integration signal # 30.

  The quantization circuit 120 compares the value of the integration signal # 30 with a preset threshold value Th, thereby generating a ΔΣ modulation signal as positive and negative switching signals # 41 and # 42 for driving both bridge type switching circuits. Generate. The positive switching signal # 41 is a digital signal (1-bit signal) that takes a logical value “1” when the value of the integral signal # 30 is larger than the threshold Th (> 0), and takes a logical value “0” otherwise. The negative switching signal # 42 is a digital signal (1-bit signal) that takes “1” when the value of the integral signal # 30 is smaller than the negative threshold −Th, and takes the logical value “0” otherwise.

  The positive and negative switching signals # 41 and # 42 generated by the quantization circuit 120 become PDM signals representing the level of the input signal # 1 due to the difference in pulse density. More specifically, a pulse density difference obtained by subtracting the pulse density of the negative switching signal 42 from the pulse density of the positive switching signal # 41 becomes proportional to the level of the input signal # 1.

  Note that as the switching signal for driving the amplifier circuit 160, various digital signals corresponding to the configuration of the amplifier circuit 160, such as a binary digital signal, a ternary digital signal, or a combination thereof, can be used. For example, when the amplifier circuit 160 is a single-bridge switching circuit, a switching signal that takes a value “1” when the value of the integral signal # 30 is greater than the threshold Th> 0 and a value “0” otherwise. May be. What is necessary is just to change suitably the specific structure of the quantization circuit 120 according to the mode of the switching signal to utilize.

  The pulse width widening circuit 130 corrects the values of the switching signals # 41 and # 42 so that the pulse width (and pulse interval) of each switching pulse does not fall below a preset lower limit pulse width W. In other words, correction is performed so that the number of times of continuously taking the same value does not fall below the lower limit value W. By setting the lower limit pulse width W of the pulse width widening circuit 130 to a value that is several times the operation clock, for example, the switching frequency of the amplifier circuit can be reduced to a fraction.

  Switching signals # 51 and # 52 corrected by the pulse width widening circuit 130 are supplied to the delay circuit 150 and the amplification circuit 160 via the selection circuit 140.

  The delay circuit 150 delays the corrected difference value between the switching signals # 51 and # 52 by N clocks and feeds it back to the integrating circuit 110. Here, the configuration in which the difference value between the corrected switching signals # 51 and # 52 is delayed and fed back to the integration circuit 110 has been described. However, the difference between the switching signals # 71 and # 72 amplified by the amplifier circuit 160 is described. A configuration in which the value is delayed and fed back to the integration circuit 110 may be employed.

  The amplifier circuit 160 is a double-bridge type switching composed of two single-bridge type switching circuits that amplify the corrected switching signals # 51 and # 52. Since the configuration of both bridge type switching circuits is the same as that shown in FIG. 10 as a conventional example, description thereof will not be repeated here. The pulse patterns of the switching signals # 71 and # 72 amplified by the amplifier circuit 160 are the same as the corrected pulse patterns of the switching signals # 51 and # 52, and their pulse density difference is the level of the input signal # 1. Is approximately proportional to

  The LPF 170 obtains output signals # 81 and # 82 by smoothing the amplified switching signals # 71 and # 72. Since the difference in pulse density between the amplified switching signals # 71 and # 72 is approximately proportional to the level of the input signal # 1, the input signal # 1 is substantially faithful as the difference between the smoothed output signals # 81 and # 82. Amplified analog signal can be obtained.

(Silent mechanism of ΔΣ modulation type digital amplifier)
Now, the ΔΣ modulation type digital amplifier 100 according to the present embodiment expects the timing when the magnitude of the primary integration value calculated by the integration circuit 110 becomes small in order to reduce the pop sound generated at the time of mute. It has a silencer mechanism that blocks transmission of the ΔΣ modulation signal output from the quantization circuit 120. The structure of the silencer mechanism will be described with reference to FIG. 1 again.

  The silencer mechanism in the ΔΣ modulation type digital amplifier 100 includes a selection circuit 140 and a silencer control circuit 180, as shown in FIG.

  The selection circuit 140 selects any one of the switching signals # 51 and # 52 or the zero signal, and outputs the selected signal to the amplification circuit 160. Selection of a signal to be output to the amplifier circuit 160 is performed based on an output switching command signal supplied from the mute control circuit 180. Specifically, when the value of the output switching command signal is “0”, the selection circuit 140 selects the switching signals # 51 and # 52, and when the value of the output switching command signal is “1”, the selection circuit 140 140 selects the zero signal. Here, the zero signal is a signal whose value is zero. That is, the selection circuit 140 functions as a blocking unit that blocks transmission of the switching signals # 51 and # 52 by selecting a zero signal during a period when the value of the output switching signal is “1”.

  The mute control circuit 180 determines a cut-off period for cutting off the switching signals # 51 and # 52 based on the given mute command and the primary integration value calculated by the integration circuit 110. In this cut-off period, An output switching command signal that takes the value “1” and the value “0” in other periods is generated.

The silencing control circuit 180 has a positive threshold value W _th set in advance. As a starting point of this shut-off period, the absolute value of the primary integrated value is the first threshold value after the silencing command is given, as will be described later. The point of time below _Wth is selected. That is, the time point at which the first-order integral value first falls within the range from −W _th to + W _th is selected. Further, the end point of the shut-off period is selected when the mute command is canceled.

Selection circuit 140, by selecting a zero signal on the basis of the output switching command signal, after the mute command is given, when the absolute value of the primary integral value falls below the first threshold value W _th, the switching signal Block transmission of # 51 and # 52.

As described above, when the mute command is given, the transmission of the switching signals # 51 and # 52 is not immediately interrupted but the switching signal is waited until the absolute value of the primary integral value falls below the threshold value _Wth. By blocking the transmission of # 51 and # 52, it is possible to reduce the pop noise caused by the quantization error that occurs when the transmission of the switching signals # 51 and # 52 is blocked.

  Note that the mute command given to the mute control circuit 180 may be generated within the ΔΣ modulation type digital amplifier 100, or another device (such as an audio device) connected to the ΔΣ modulation type digital amplifier 100. ) May be supplied from any source. Examples of the former include ΔΣ modulation type digital when the level of the input signal # 10 becomes 0 (or falls within a predetermined range including 0), or when a specific user operation is performed. Examples thereof include a mute command generated by the amplifier 100. Furthermore, it is assumed that a mute command is supplied from a microcomputer or a DSP provided in the ΔΣ modulation type digital amplifier 100 or another device connected to the ΔΣ modulation type digital amplifier 100.

  The silencer mechanism shown in FIG. 1 blocks the transmission of the switching signals # 51 and # 52 by the selection circuit 140 provided on the transmission path between the pulse width widening circuit 130 and the amplifier circuit 160. However, the configuration for blocking the transmission of the ΔΣ modulation signal is not limited to this.

  For example, the selection circuit 140 is provided on the transmission path between the quantization circuit 120 and the pulse width widening circuit 130 so as to block transmission of the switching signals # 41 and # 42 before the pulse width is widened. Alternatively, the selection circuit 140 may be provided on the transmission path between the amplifier circuit 160 and the LPF 170 to block transmission of the amplified switching signals # 71 and # 72. Also, the transmission of the switching signal is interrupted by stopping the power supply to the amplifier circuit 160 or by shorting the switching elements constituting the amplifier circuit 160 to mute the output of the amplifier circuit 160. May be. That is, transmission of the ΔΣ modulation signal (which may be any of switching signals # 41 and # 42, corrected switching signals # 51 and # 52, or amplified switching signals # 71 and # 72) is cut off. Any configuration can be used. Furthermore, when a circuit provided on the signal path, such as the integration circuit 110, the quantization circuit 120, and the pulse width widening circuit 130, is realized by a digital circuit, a reset signal is sent to a D flip-flop included in the digital circuit. As a result, the signal input to the amplifier circuit 160 may be zero.

Moreover, silencing mechanism shown in FIG. 1, as described in detail below, after the mute command is given, the switching signal # 51 and when the absolute value of the primary integral value falls below the first threshold value W _th The transmission of # 52 is interrupted, and thereafter the interruption is continued until the mute command is canceled. However, the time when the interruption starts and the time when the interruption ends are not limited to this.

  In other words, the time point when the interruption is started may be any time point in the period in which the primary integral value is within a predetermined range including 0, and the interruption is performed at any time point within the period. The pop sound caused by the quantization error that occurs when starting the operation can be suppressed to a certain level or less. Further, when the level of the input signal is equal to 0, the time point when the interruption is finished may be an arbitrary time point. For example, the interruption may be finished immediately after the interruption is started. That is, it may be performed only when there is an interruption. However, regardless of the level of the input signal # 10, the switching signals # 51 and # 52 can be reliably interrupted while the silencing command is given until the silencing command is canceled as described above. It is preferable to continue blocking.

(Details of integration circuit and mute control circuit)
Hereinafter, the integration circuit 110 for calculating the primary integration value referred to for determining the silencing timing and the silencing control circuit 180 for determining the silencing timing based on the primary integration value will be described with reference to FIGS. A little more detail based on this.

  FIG. 2 is a circuit block diagram illustrating a configuration example of the integration circuit 110. As described above, the integration circuit 110 may calculate a primary integration value or may calculate a high-order integration value obtained by further integrating the primary integration value. As shown, a fifth-order integration circuit including an integrator group including five integrators 111 to 115 is shown.

  Among the five integrators 111 to 115 shown in the figure, the integrator 111 arranged on the most upstream side is called a “first-order integrator”, and integrates the value of the difference signal # 20 itself, thereby integrating the first-order integration. The value is calculated. The value of the difference signal 20 represents a quantization error in ΔΣ modulation, and the primary integration value represents an integral value obtained by integrating the quantization error in ΔΣ modulation.

  FIG. 3 is a graph showing temporal changes of the difference signal # 20 (that is, the quantization error) and its primary integration value (that is, the integration value of the quantization error). As shown in FIG. 3, the quantization error oscillates in small increments, whereas the primary integration value shows a piecewise substantially linear change, and the magnitude of the primary integration value at each time point is It reflects the magnitude of the quantization error before and after, particularly the magnitude of the error near the DC component.

Therefore, by reducing the threshold value _Wth , it is possible to reduce the quantization error as much as possible when the transmission of the switching signals # 51 and # 52 is cut off. That is, by reducing the threshold value _Wth , it is possible to reduce the pop sound generated when the transmission of the switching signals # 51 and # 52 is interrupted.

However, as the threshold value _Wth is decreased, the probability that the absolute value of the first-order integral value is lower than the threshold value _Wth also decreases. Therefore, the switching signals # 51 and # 52 are transmitted after the mute command is given. The time until it is blocked becomes longer. That is, the response to the mute command is reduced. Therefore, it is desirable to set the threshold value W _th as small as possible within a range that allows a decrease in response to the mute command. For example, when the maximum swing width of the primary integral value is 1, it is desirable to set the swing width to a magnitude of about 0.05% to 0.5%.

  FIG. 4 is a circuit block diagram illustrating a configuration example of the mute control circuit 180. As shown in FIG. 4, the mute control circuit 180 includes a calculation circuit 181, a comparison circuit 182, and a determination circuit 183.

The calculation circuit 181 is a circuit that calculates the absolute value | W | of the primary integration value W for each clock. The comparison circuit 182 compares the calculated absolute value | W | and the threshold value W _th for each clock, and if the absolute value | W | is equal to or less than W _th , the value “1” is set. Otherwise, the value “0” is set. Is output to the determination circuit 183 as a comparison result.

  The decision circuit 183 is a circuit for deciding whether to cut off the switching signals # 51 and # 52 for each clock, and includes an OR gate 183a, an AND gate 183b, and a DFF (D flip-flop) 183c. Has been. The mute control circuit 180 supplies the determination result sequence obtained by the determination circuit 183 to the selection circuit 140 as an output switching command signal.

  The OR gate 183a receives the determination result of the previous clock stored in the DFF (D flip-flop) 183c and the comparison result by the comparison circuit 182. The output value of the OR gate 183a and the value of the mute command signal are input to the AND gate 183b. The output value of the AND gate 183b is input to the DFF 183c.

  FIG. 5 shows a primary integration value input to the calculation circuit 181, a comparison result obtained by the comparison circuit 182, a mute command signal input to the decision circuit 183, and an output switching command signal obtained by the decision circuit 183. 6 is a timing chart showing a change in the value of.

  While the value of the mute command signal is “0”, the AND gate 183b continues to output “0” regardless of the output value of the OR gate 183a (as shown in FIG. 5, the comparison result at time T0). Even if becomes “1”, the AND gate 183b outputs “0”). Therefore, as shown in FIG. 5, the value of the output switching command signal is “0” until the time T <b> 1 when the mute command is given.

Even if the value of the mute command signal becomes “1”, the AND gate 183b continues to output “0” until the output value of the OR gate 183a becomes “1”. The output value of the OR gate 183b first becomes “1” at time T2 when the comparison result becomes “1”. Therefore, as shown in FIG. 5, after the mute command is given, at the time T2 when the magnitude of the primary integration value | W | first falls below the threshold value _Wth , the value of the output switching command signal is “ It rises from “0” to “1”.

  Once the output value of the AND gate 183b becomes “1”, the AND gate 183b continues to output “1” until the value of the mute command signal becomes “0”. This is because since the output value of the previous clock of the AND gate 183b is input to the OR gate 183b, the OR gate 183b continues to output “1” regardless of the comparison result. Therefore, as shown in FIG. 5, the value of the output switching command signal is “1” uniformly until time T3 when the mute command is canceled.

  When the value of the mute command signal becomes “0”, the AND gate 183b outputs “0”. Therefore, at time T3 when the mute command is canceled, the value of the output switching command signal rises from “1” to “0”. Go down.

As described above, after the silencing command is given, the output switching is performed during a period from time T2 when the magnitude of the primary integration value | W | first falls below the threshold value _Wth to time T3 when the silencing command is canceled. The value of the command signal becomes “1”, and the transmission of the switching signals # 51 and # 52 is blocked by the selection circuit 140.

Note that the silencing control circuit 180 shown in FIG. 4 blocks the switching signals # 51 and # 52 because the primary integration value falls within the range from −W _th to + W _th , but is negative. A configuration in which the threshold value W _th1 and the positive threshold value W _th2 are individually set and the switching signals # 51 and # 52 are cut off after the primary integration value falls within the range from W _th1 to W _th2 It may be adopted.

FIG. 6 is a block diagram showing a modification of the mute control circuit 180. The mute control circuit 180 shown in FIG. 6 includes a calculation circuit 181 that calculates the absolute value | W | of the primary integration value W shown in FIG. 4 and a comparison circuit that compares the absolute value | W | with a threshold value W _th. Instead of 182, a window comparator (comparison circuit) 184 that compares the primary integration value W with a negative threshold value W _th1 and a positive threshold value W _th2 is provided.

The window comparator 184 indicates “1” when the primary integration value W is equal to or greater than a preset negative threshold value W _th1 and equal to or less than a preset positive threshold value W _th2 , otherwise “1”. 0 "is output. That is, according to the silencing control circuit 180 shown in FIG. 6, when the primary integration value W first falls below the positive threshold value W _th2 , or when the primary integration value W first exceeds the negative threshold value W _th1 . The value of the output switching command signal becomes “1” during the period from when the mute command is released to when the mute command is canceled, and the transmission of the switching signals # 51 and # 52 can be blocked by the selection circuit 140.

(simulation result)
Finally, when the mute command is given, the switching signal transmission is immediately interrupted, and when the switching signal transmission is interrupted after the primary integration value first falls below the threshold. FIG. 7 shows a simulation result comparing the magnitudes of pop sounds generated.

In the figure, a graph O shows a time change of the primary integral value W. The graph P1 shows a switching signal that is immediately interrupted when a mute command is given, and the graph P2 shows that the absolute value of the primary integral value W is a threshold value W _th (set to 2 ²³ × 10 ⁻¹⁰ ). It shows a switching signal whose transmission has been cut off after waiting below. Graph Q1 shows the potential difference between the output signals obtained by smoothing the switching signal shown in graph P1 with LPF. Graph Q2 is obtained by smoothing the switching signal shown in graph P2 with LPF. The potential difference between output signals is shown.

  As is apparent from the simulation results, if the transmission of the switching signal is interrupted while ignoring the magnitude of the first-order integral value (quantization error), a large jump R1 occurs in the potential difference between the output signals, and a large pop sound is generated. generate. On the other hand, when the transmission of the switching signal is interrupted after waiting for the primary integral value (quantization error) to fall within a predetermined range including 0, the jump R2 of the potential difference between the output signals becomes small, and a pop sound is generated. Almost no generation.

(Additional notes)
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  For example, the present invention provides a “ΔΣ modulator (consisting of an integrator group (integrator circuit) including a plurality of integrators, a quantizer (quantizer circuit), and a pulse width controller (pulse width widening circuit) ( ΔΣ modulation type digital amplifier) includes an absolute value calculator (calculation circuit) for calculating the absolute value of the primary integrator output, a comparator (comparison circuit), and a silenced state holding circuit (decision circuit). In other words, it may be expressed as a “ΔΣ modulation device characterized in that when the output of the first integrator falls within a specified range, a transition is made to a state in which no pulse is output”.

  Further, in this embodiment, the ΔΣ modulation device realized as a ΔΣ modulation type digital amplifier has been described. However, the ΔΣ modulation device of the present invention is not limited to this, and is realized, for example, as an AD / DA conversion device. It may be.

  Finally, the ΔΣ modulation digital amplifier 100 may be configured by hardware logic as described above, but can also be realized by a digital signal processor. That is, the ΔΣ modulation type digital amplifier 100 carries an arithmetic unit such as a high-speed product-sum operation unit or an ALU (arithmetic logical unit) and a control program that functions as each block (circuit) included in the ΔΣ modulation type digital amplifier 100. It can be configured as a digital signal processor including a storage device such as a program memory. The same applies to the ΔΣ modulation digital amplifier 100 ′.

  The object of the present invention is not limited to the case where the control program is fixedly held in the program memory of the digital signal processor, but the program code of the control program (executable program, intermediate code program, or source program) ) To a general-purpose digital signal processor and the digital signal processor executes the program code, or a recording medium on which the program code is recorded is supplied to the ΔΣ modulation type digital amplifier 100 and ΔΣ modulation is performed. This can also be achieved by reading and executing the program code recorded on the recording medium by a general-purpose digital signal processor provided in the digital amplifier 100.

  Examples of the recording medium include a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  Further, a digital signal processor (or a ΔΣ modulation type digital amplifier 100 including a digital signal processor) is configured to be connectable to a communication network, and the program code is supplied to the digital signal processor via the communication network. Good. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave, in which the program code is embodied by electronic transmission.

  The present invention can be applied to any ΔΣ modulation apparatus that generates a ΔΣ modulation signal, and can be suitably used particularly for a ΔΣ modulation digital amplifier.

1, showing an embodiment of the present invention, is a block diagram showing a configuration of a ΔΣ modulation type digital amplifier (ΔΣ modulation device). FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a configuration example of an integration circuit. FIG. 4 is a graph showing an embodiment of the present invention, showing a time variation of a differential signal corresponding to a quantization error and a primary integration value obtained by integrating the quantization error. FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a configuration example of a mute control circuit. FIG. FIG. 6 is a timing chart illustrating an embodiment of the present invention and illustrating changes in values of a primary integral value, a comparison result, a mute command signal, and an output switching command signal. FIG. 7 is a block diagram illustrating a modification of the mute control circuit according to the embodiment of the present invention. 4 shows an embodiment of the present invention, when a mute command is given, when switching signal transmission is interrupted immediately, and after waiting for the primary integral value to fall within a predetermined range including zero It is a figure which shows the simulation result which compared the magnitude | size of the pop sound to generate | occur | produce with the case where transmission of a signal is interrupted | blocked. FIG. 9 is a block diagram illustrating a conventional technique and illustrating a schematic configuration of a ΔΣ modulation digital amplifier including a single-bridge switching circuit as an amplifier circuit. 9 is a graph showing changes over time in the output voltage of the amplifier circuit, the output voltage of the LPF, and the voltage applied to the load in the ΔΣ modulation digital amplifier shown in FIG. 8. FIG. 9 is a block diagram illustrating a conventional technique and illustrating a schematic configuration of a ΔΣ modulation digital amplifier including a double-bridge switching circuit as an amplifier circuit. 11 is a graph showing changes over time in the output voltage of the amplifier circuit, the output voltage of the LPF, and the voltage applied to the load in the ΔΣ modulation digital amplifier shown in FIG. 10.

Explanation of symbols

100 ΔΣ modulation type digital amplifier (ΔΣ modulator)
110 Integration circuit 120 Quantization circuit 130 Pulse width widening circuit 140 Selection circuit (cut-off means)
150 Delay Circuit 160 Amplifier Circuit (Switching Circuit)
170 Low-pass filter 180 Silencing control circuit (cut-off period determining means)
181 Calculation circuit 182 Comparison circuit 183 Determination circuit 183a OR gate 183
183b AND gate 183
183c D flip-flop

Claims (9)

ΔΣ modulation that generates a ΔΣ modulation signal by quantizing a first-order integral value obtained by integrating the difference value between the input signal and the fed back ΔΣ-modulated signal, or a higher-order integral value obtained by further integrating the first-order integral value. In the device
A cutoff means for cutting off transmission of the ΔΣ modulation signal when the primary integration value is within a predetermined range including 0;
A ΔΣ modulator characterized by that. Further comprising a cutoff period determining means for determining a cutoff period for continuing to block transmission of the ΔΣ modulation signal by the cutoff means based on a given mute command and the primary integral value;
The start point of the shut-off period is the time when the primary integration value first falls within the range after the mute command is given.
The ΔΣ modulation apparatus according to claim 1. The end point of the blocking period is the time when the mute command is canceled,
The ΔΣ modulator according to claim 2. The cutoff period determining means determines a calculation circuit for calculating an absolute value of the primary integral value, a comparison circuit for comparing the absolute value with a preset threshold value, and whether to cut off the ΔΣ modulation signal. And a decision circuit to
The determination circuit includes an OR gate that calculates a logical sum of the previous determination result of the determination circuit and the comparison result of the comparison circuit, and an AND gate that calculates a logical product of the output of the OR gate and the mute command. Contains,
The ΔΣ modulator according to claim 3. The cutoff period determining means includes a comparison circuit that determines whether or not the primary integration value is within the range, and a determination circuit that determines whether or not to block the ΔΣ modulation signal.
The determination circuit includes an OR gate that calculates a logical sum of the previous determination result of the determination circuit and the determination result of the comparison circuit, and an AND gate that calculates a logical product of the output of the OR gate and the mute command. Contains,
The ΔΣ modulator according to claim 3. The shut-off means is a selection circuit provided on the transmission path of the ΔΣ modulation signal to select and output either the ΔΣ modulation signal or the zero signal, and the ΔΣ modulation is selected by selecting the zero signal. Block signal transmission,
The ΔΣ modulator according to any one of claims 1 to 5, wherein ΔΣ modulation that generates a ΔΣ modulation signal by quantizing a first-order integral value obtained by integrating the difference value between the input signal and the fed back ΔΣ-modulated signal, or a higher-order integral value obtained by further integrating the first-order integral value. In the apparatus, a blocking method for blocking transmission of the generated ΔΣ modulation signal,
Including a blocking step of blocking transmission of the ΔΣ modulation signal when the first-order integral value is within a predetermined range including zero.
A blocking method characterized by that. A program for operating a digital signal processor as a ΔΣ modulator according to any one of claims 1 to 3,
A program for causing the digital processor to function as each means included in the ΔΣ modulator.   A digital signal processor-readable recording medium in which the program according to claim 8 is recorded.

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