JP2009130002A - Jbs and mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To limit the injection dose of holes injected to an N-epitaxial layer 2. <P>SOLUTION: In the JBS with active regions A1 and A2 wherein a Schottky junction C1 and a pn junction C2 coexist and a guard ring region A3 arranged on the outer side, by introducing and diffusing P type impurities to the N- type epitaxial layer 2 through the side and bottom surfaces of trenches 4a, 4b, 4c, 4d, 4e and 4f, P type layers 5a, 5b, 5c, 5d, 5e and 5f whose diffusion depth in a longitudinal direction and a lateral direction is about 0.1 to 0.2 μm and concentration is 10<SP>16</SP>/cm<SP>3</SP>order are formed. An opening is formed on an oxide film 6 at the bottom surface of the trenches 4a, 4b, 4c, 4d, 4e and 4f, P+ type polysilicon layers 7a, 7b, 7c, 7d, 7e and 7f whose concentration is ≥10<SP>18</SP>/cm<SP>3</SP>order are formed inside the trenches 4a, 4b, 4c, 4d, 4e and 4f, and a heavy metal is diffused to the P type layers 5a, 5b, 5c, 5d, 5e and 5f and the N- type epitaxial layer 2 through the P+ type polysilicon layers 7a, 7b, 7c, 7d, 7e and 7f and the opening of the oxide film 6 on the bottom surface of the trenches 4a, 4b, 4c, 4d, 4e and 4f. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a JBS including a semiconductor chip including an active region in which a Schottky junction and a PN junction coexist, and a guard ring region disposed outside the active region, and more particularly to an N-epitaxial layer. The present invention relates to a JBS capable of limiting the amount of holes injected as carriers to be injected.

  Furthermore, the present invention relates to a MOSFET constituted by a semiconductor chip having an active region and a guard ring region arranged outside the active region, and in particular, a hole as a carrier injected into an N-epitaxial layer. The present invention relates to a MOSFET capable of limiting the injection amount.

  Conventionally, a semiconductor element having a guard ring is known. For example, in the semiconductor element described in FIG. 11 and FIG. 12 of Japanese Patent Laid-Open No. 5-190831, the guard ring is constituted by a P-type region. In the semiconductor element described in FIG. 11 and FIG. 12 of Japanese Patent Laid-Open No. 5-190831, it is considered that the P-type region of the guard ring is formed by planar diffusion. In order to increase the breakdown voltage of the peripheral portion of the semiconductor chip, it is preferable to deepen the PN junction interface of the P-type region of the guard ring, but when the P-type region of the guard ring is formed by planar diffusion, When the PN junction interface of the P-type region of the guard ring is deepened, P-type impurities for forming the P-type region of the guard ring are diffused widely in the lateral direction, which increases the lateral dimension of the semiconductor chip. End up.

  In view of the above, the P-type region is not formed by planar diffusion, but a trench (recess) is formed in the N− type epitaxial layer on the N + type substrate, and the P type is formed via the side surface of the trench (recess). A P-type layer is formed along the side surface of the trench (recess) by introducing and diffusing impurities, and a bottom surface of the trench (recess) is introduced and diffused through the bottom surface of the trench (recess). Conventionally, a semiconductor element in which a P-type layer is formed along the line is known. Examples of this type of semiconductor element include, for example, FIG. 3 of JP-A-4-321274, FIG. 2 of JP-A-5-29635, FIG. 4 of JP-A-5-48081, and JP-A-5-90565. There are those described in FIG. 2 of the publication, FIG. 2 of JP-A-5-110061, and the like.

  FIG. 3 of Japanese Patent Laid-Open No. 4-321274, FIG. 2 of Japanese Patent Laid-Open No. 5-29635, FIG. 4 of Japanese Patent Laid-Open No. 5-48081, FIG. In the semiconductor device described in FIG. 2 of Japanese Patent No. 110061, a P-type layer is formed along the bottom surface of the trench (recess) by introducing and diffusing P-type impurities through the bottom surface of the trench (recess). Therefore, the PN junction interface between the P-type layer and the N-type epitaxial layer can be formed at a deep position without increasing the lateral dimension of the semiconductor chip.

  Incidentally, FIG. 3 of JP-A-4-321274, FIG. 2 of JP-A-5-29635, FIG. 4 of JP-A-5-48081, FIG. 2 of JP-A-5-90565, and In the semiconductor device described in FIG. 2 of Japanese Patent No. 5-110061, electrode metal is formed on the surface of the P-type layer formed along the side surface of the trench (recess) by vapor deposition or sputtering, and the trench (recess The electrode metal is formed by vapor deposition or sputtering on the surface of the P-type layer formed along the bottom surface.

Specifically, FIG. 3 of Japanese Patent Laid-Open No. 4-321274, FIG. 2 of Japanese Patent Laid-Open No. 5-29635, FIG. 2 of Japanese Patent Laid-Open No. 5-90565, and FIG. In the semiconductor element described, the inside of the trench (recess) is not filled and remains as a recess. On the other hand, in the semiconductor device described in FIG. 4 of Japanese Patent Laid-Open No. 5-48081, polycrystalline or amorphous silicon mainly containing silicon, which is a constituent atom of a silicon substrate, is provided inside a trench (recess). And a solid material containing boron, aluminum, or phosphorus atoms as impurities. Further, in the semiconductor element described in FIG. 4 of Japanese Patent Laid-Open No. 5-48081, the solid material layer formed inside the trench (recess) is a structure deposited by the CVD method. It is polycrystalline or amorphous silicon containing aluminum or phosphorus in an amount of 10 ¹⁸ to 10 ²² / cm ³ or more, and becomes an alloy that strongly shows metallic properties, and forms a low resistance electrode.

  Further, FIG. 3 of JP-A-4-321274, FIG. 2 of JP-A-5-29635, FIG. 4 of JP-A-5-48081, FIG. 2 of JP-A-5-90565, and JP-A-5-29565. In the semiconductor device described in FIG. 2 of Japanese Patent No. 5-110061, the bottom surface of the trench (recess) is formed with respect to the P-type layer formed along the bottom surface of the trench (recess) and the N-type epitaxial layer immediately below the P-type layer. The heavy metal is not diffused through.

  Further, a P-type region is not formed by planar diffusion as in the semiconductor device described in FIGS. 11 and 12 of Japanese Patent Laid-Open No. 5-190831, but a trench is formed in an N− type epitaxial layer on an N + type substrate. A semiconductor element has been conventionally known in which a P-type layer is formed along the bottom surface of a trench by forming a P-type impurity vertically and a P-type layer is not formed along a side surface of the trench. Examples of this type of semiconductor element include those described in FIG. 3 of Japanese Patent Laid-Open No. 5-63184, for example.

  In the semiconductor element described in FIG. 3 of Japanese Patent Laid-Open No. 5-63184, an oxide film is formed on the side and bottom surfaces of the trench after the P-type layer is formed only along the bottom surface of the trench. Further, in the semiconductor device described in FIG. 3 of Japanese Patent Laid-Open No. 5-63184, the oxide film only on the bottom surface of the trench is removed to expose the P-type layer, and the oxide film on the side surface of the trench is left. Next, in the semiconductor device described in FIG. 3 of JP-A-5-63184, a metal film is formed on the P-type layer on the bottom surface of the trench and a metal film is formed on the oxide film on the side surface of the trench. The

  Incidentally, in the semiconductor element described in FIG. 3 of Japanese Patent Laid-Open No. 5-63184, the inside of the trench is not filled and remains as a recess.

  Further, in the semiconductor device described in FIG. 3 of Japanese Patent Laid-Open No. 5-63184, the P-type layer formed along the bottom surface of the trench and the N-type epitaxial layer directly below the P-type layer are interposed via the bottom surface of the trench. There is no diffusion of heavy metals.

  Further, a P-type region is not formed by planar diffusion as in the semiconductor device described in FIGS. 11 and 12 of Japanese Patent Laid-Open No. 5-190831, but a trench is formed in an N− type epitaxial layer on an N + type substrate. Conventionally, a semiconductor element in which a P-type layer along only the bottom surface of the trench is formed using a hydrocarbon chlorine fluoropolymer wall on the side surface of the trench and no P-type layer along the side surface of the trench is formed. Are known. As an example of this type of semiconductor element, there is one described in, for example, FIG. 2 of JP-A-5-110062.

  In the semiconductor device described in FIG. 2 of Japanese Patent Laid-Open No. 5-110062, after a P-type layer is formed only along the bottom surface of the trench, a metal film is formed on the P-type layer on the bottom surface of the trench. A metal film is also formed on the side surface of the trench.

  By the way, in the semiconductor element described in FIG. 2 of Japanese Patent Laid-Open No. 5-110062, the inside of the trench is not filled and remains as a recess.

  Further, in the semiconductor device described in FIG. 2 of JP-A-5-110062, the P-type layer formed along the bottom surface of the trench and the N-type epitaxial layer immediately below the P-type layer are interposed via the bottom surface of the trench. There is no diffusion of heavy metals.

That is, conventionally, if a trench (concave portion) is formed in the N− type epitaxial layer and the trench (concave portion) is left as it is without filling the inside of the trench (concave portion), two adjacent trenches ( In view of the fact that the strength of the portion (convex portion) between the concave portions is reduced, for example, in the semiconductor element described in FIG. 4 of Japanese Patent Laid-Open No. 5-48081, for example, boron, aluminum, or phosphorus is 10 ¹⁸ to Polycrystalline or amorphous silicon containing 10 ²² / cm ³ or more was disposed inside the trench (recess).

However, in the semiconductor element described in FIG. 4 of JP-A-5-48081, for example, polycrystalline or amorphous silicon containing 10 ¹⁸ to 10 ²² / cm ³ or more of boron, aluminum, or phosphorus is a trench (recess). Before being placed inside, the electrode metal is formed on the surface of the P-type layer along the side and bottom surfaces of the trench (recess) by vapor deposition or sputtering.

  Therefore, in the semiconductor element described in FIG. 4 of Japanese Patent Application Laid-Open No. 5-48081, the trench (recessed portion) is formed through the polycrystalline or amorphous silicon disposed inside the trench (recessed portion) and the bottom surface of the trench (recessed portion). It is not possible to introduce heavy metal as a lifetime killer into the P-type layer just below the bottom of the recess.

11 and 12 of Japanese Patent Laid-Open No. 5-190831. FIG. 3 of Japanese Patent Laid-Open No. 4-321274 FIG. 2 of JP-A-5-29635 FIG. 4 of JP-A-5-48081 FIG. 2 of JP-A-5-90565 FIG. 2 of JP-A-5-110061 FIG. 3 of JP-A-5-63184 FIG. 2 of JP-A-5-110062

  In view of the above problems, the present invention provides a lifetime killer for a high-concentration P + type polysilicon layer formed inside a trench and a P-type layer just below the bottom of the trench through an oxide film opening on the bottom of the trench. It is an object of the present invention to provide a JBS capable of limiting the amount of holes injected as carriers injected into an N-epitaxial layer, compared to the case where no heavy metal is introduced.

  Furthermore, the present invention provides a carrier life of the P-type layer and N-type epitaxial layer on the side of the trench side rather than the carrier lifetime of the P-type layer and N-type epitaxial layer near the bottom of the trench. An object is to provide a JBS capable of extending the time.

  Further, according to the present invention, it is possible to extend the sky layer at the time of reverse bias to the peripheral side of the semiconductor chip as compared with the case where the field plate is not formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. The purpose is to provide.

  Furthermore, the present invention provides a residual hole (hole) existing between the lower end of the vacant layer just below the N-type Schottky junction interface between two adjacent trenches and the N + type substrate during reverse bias. ) At the time of switching from the reverse bias to the forward bias, the N-type epitaxial layer and the P-type layer immediately below the oxide film opening at the bottom of the trench where the heavy metal is locally distributed, and the anode electrode metal An object of the present invention is to provide a JBS that can be quickly returned to the anode electrode metal through a high-concentration P + type polysilicon layer inside a trench having a potential close to that of the anode.

  In addition, the present invention provides a high-concentration P + type polysilicon layer formed inside the first trench and a P-type layer directly below the bottom surface of the first trench through the opening of the oxide film on the bottom surface of the first trench. It is an object of the present invention to provide a MOSFET capable of limiting the amount of holes injected as carriers injected into an N-epitaxial layer, compared to a case where heavy metal as a time killer is not introduced.

  Furthermore, the present invention provides a P-type layer and an N-type epitaxial layer on the lateral side of the first trench rather than the carrier lifetime of the P-type layer and the N-type epitaxial layer near the bottom of the first trench. An object of the present invention is to provide a MOSFET capable of extending the lifetime of the carrier.

  Further, according to the present invention, it is possible to extend the vacant layer at the time of reverse bias to the peripheral side of the semiconductor chip as compared with the case where the guard ring electrode metal is not formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. An object of the present invention is to provide a MOSFET that can be used.

  Furthermore, the present invention eliminates residual holes (holes) existing between the lower end of the vacant layer just below the junction interface between two adjacent first trenches and the N + type substrate during reverse bias. When switching from the reverse bias to the forward bias, the N− type epitaxial layer and the P type layer immediately below the opening of the oxide film at the bottom of the first trench where the heavy metal is locally distributed, and the source electrode metal An object of the present invention is to provide a MOSFET that can be quickly returned to the source electrode metal via a high-concentration P + type polysilicon layer inside the first trench that is close to the potential of the first trench.

According to the first aspect of the present invention, in a JBS configured by a semiconductor chip including an active region in which a Schottky junction and a PN junction coexist, and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a plurality of trench formation openings in the first oxide film of the active region and the guard ring region;
A plurality of trenches are formed in the active region and the guard ring region through a plurality of trench formation openings,
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm and the concentration Forming a P-type layer of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of trenches,
Forming a second oxide film on the side and bottom surfaces of the plurality of trenches;
Forming openings in the second oxide film on the bottom surfaces of the plurality of trenches;
P + type polysilicon having a concentration of 10 ¹⁸ / cm ³ or more is formed by filling polysilicon into the plurality of trenches and doping the polysilicon filled in the plurality of trenches with P type impurities. Forming a layer inside a plurality of trenches;
Depositing and diffusing heavy metal into the P-type layer and the N-type epitaxial layer through the P + type polysilicon layer formed inside the plurality of trenches and the opening of the second oxide film on the bottom surface of the plurality of trenches;
Forming a third oxide film on the surface of the P + type polysilicon layer formed in the plurality of trenches;
Forming an opening for N + type layer formation in the oxide film at the periphery of the semiconductor chip;
Forming an N + type layer on the periphery of the semiconductor chip through the N + type layer forming opening;
An opening for forming a barrier metal is formed in the oxide film in the active region of the semiconductor chip,
An opening for the field plate is formed in the oxide film on the P + type polysilicon layer in the guard ring region of the semiconductor chip,
A barrier metal is formed in the active region of the semiconductor chip through the opening for forming the barrier metal,
An anode electrode metal is formed on the barrier metal,
A field plate is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip through the field plate opening,
An EQR electrode metal is formed on the N + type layer at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
A contact opening for connecting to the anode electrode metal is formed in the final protective film,
A JBS is provided in which a cathode electrode metal is formed on the back surface of a semiconductor chip.

According to the invention described in claim 2, in a MOSFET constituted by a semiconductor chip comprising an active region and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a P-type layer forming opening in the first oxide film of the active region;
A P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening,
Forming a second oxide film on the surface of the P-type layer during the diffusion of the P-type impurities;
Forming a plurality of first trench formation openings in the oxide film of the active region and the guard ring region;
Forming a plurality of first trenches in the active region and the guard ring region through a plurality of first trench formation openings;
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm. Forming a P-type layer with a concentration of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of first trenches,
Forming a third oxide film on the side and bottom surfaces of the plurality of first trenches;
Forming an opening in the third oxide film on the bottom surface of the plurality of first trenches;
By filling polysilicon into the plurality of first trenches and doping the polysilicon filled in the plurality of first trenches with a P-type impurity, the concentration becomes 10 ¹⁸ / cm ³ or more. Forming a P + type polysilicon layer inside the first trenches;
Heavy metal is deposited on the P + type polysilicon layer formed in the plurality of first trenches and the P-type layer and the N− type epitaxial layer immediately below the third oxide film through the openings of the third oxide films on the bottom surfaces of the plurality of first trenches.・ Diffusion,
Forming a fourth oxide film on the surface of the P + type polysilicon layer formed in the plurality of first trenches;
N + type layer forming openings are formed in the oxide film at the peripheral portion of the semiconductor chip and the oxide film in the central portion of the active region of the semiconductor chip excluding the first trench,
Forming an N + type layer on the periphery of the semiconductor chip through the N + type layer forming opening and a portion excluding the first trench in the central part of the active region of the semiconductor chip;
Forming a fifth oxide film on the surface of the N + type layer;
Forming a plurality of second trench formation openings in the oxide film in the center of the active region;
Forming a plurality of second trenches in the central portion of the active region through the plurality of second trench formation openings;
Forming a thermal oxide film to be a gate oxide film of the MOSFET on the side and bottom surfaces of the plurality of second trenches;
The polysilicon is filled in the plurality of second trenches and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the polysilicon and the semiconductor chip filled in the plurality of second trenches are activated. By doping the polysilicon deposited on a part of the peripheral portion of the region with an N-type impurity, the N + -type polysilicon layer is formed inside the second trenches and on the peripheral portion of the active region of the semiconductor chip. Formed in the part,
Forming a sixth oxide film over the entire surface of the semiconductor chip;
Of the central portion of the active region, a portion of the oxide film excluding the second trench, a portion of the oxide film on the N + type polysilicon layer at the peripheral portion of the active region, and a portion of the guard ring region on the P + type polysilicon layer An opening for forming an electrode metal is formed in the oxide film and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip,
Electrode metal is formed on the entire surface of the semiconductor chip,
The electrode metal on the entire surface of the semiconductor chip is divided into a source electrode metal at the center of the active region, a gate wiring routing electrode metal at the peripheral portion of the active region, and a source electrode metal positioned on the peripheral side of the gate wiring routing electrode metal. And electrically separating the guard ring electrode metal and the EQR electrode metal at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
Electrically connecting the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal;
A source electrode metal located above the N + type polysilicon layer at the periphery of the active region, and a P + type polysilicon layer inside the first trench located below the N + type polysilicon layer at the periphery of the active region; Electrically connect
There is provided a MOSFET characterized in that a drain electrode metal is formed on the back surface of a semiconductor chip.

According to the invention described in claim 3, in a MOSFET constituted by a semiconductor chip comprising an active region and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a P-type layer forming opening in the first oxide film of the active region;
A P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening,
Forming a second oxide film on the surface of the P-type layer during the diffusion of the P-type impurities;
Forming a plurality of first trench formation openings in the oxide film of the active region and the guard ring region;
Forming a plurality of first trenches in the active region and the guard ring region through a plurality of first trench formation openings;
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm. Forming a P-type layer with a concentration of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of first trenches,
Forming a third oxide film on the side and bottom surfaces of the plurality of first trenches;
Forming an opening in the third oxide film on the bottom surface of the plurality of first trenches;
By filling polysilicon into the plurality of first trenches and doping the polysilicon filled in the plurality of first trenches with a P-type impurity, the concentration becomes 10 ¹⁸ / cm ³ or more. Forming a P + type polysilicon layer inside the first trenches;
Heavy metal is deposited on the P + type polysilicon layer formed in the plurality of first trenches and the P-type layer and the N− type epitaxial layer immediately below the third oxide film through the openings of the third oxide films on the bottom surfaces of the plurality of first trenches.・ Diffusion,
Forming a fourth oxide film on the surface of the P + type polysilicon layer formed in the plurality of first trenches;
The N + type layer forming opening is a portion excluding the oxide film at the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip, excluding the portion adjacent to the peripheral portion of the active region, and excluding the first trench Formed with the oxide film,
Of the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip through the N + type layer forming opening, the portion excluding the portion adjacent to the peripheral portion of the active region, excluding the first trench And an N + type layer is formed on
Forming a fifth oxide film on the surface of the N + type layer;
Forming a plurality of second trench formation openings in the oxide film in the center of the active region;
Forming a plurality of second trenches in the central portion of the active region through the plurality of second trench formation openings;
Forming a thermal oxide film to be a gate oxide film of the MOSFET on the side and bottom surfaces of the plurality of second trenches;
The polysilicon is filled in the plurality of second trenches and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the polysilicon and the semiconductor chip filled in the plurality of second trenches are activated. By doping the polysilicon deposited on a part of the peripheral portion of the region with an N-type impurity, the N + -type polysilicon layer is formed inside the second trenches and on the peripheral portion of the active region of the semiconductor chip. Formed in the part,
Forming a sixth oxide film over the entire surface of the semiconductor chip;
Of the central portion of the active region, a portion of the oxide film excluding the second trench, a portion of the oxide film on the N + type polysilicon layer at the peripheral portion of the active region, and a portion of the guard ring region on the P + type polysilicon layer An opening for forming an electrode metal is formed in the oxide film and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip,
Electrode metal is formed on the entire surface of the semiconductor chip,
The electrode metal on the entire surface of the semiconductor chip is divided into a source electrode metal at the center of the active region, a gate wiring routing electrode metal at the peripheral portion of the active region, and a source electrode metal positioned on the peripheral side of the gate wiring routing electrode metal. And electrically separating the guard ring electrode metal and the EQR electrode metal at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
Electrically connecting the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal;
A source electrode metal located above the N + type polysilicon layer at the periphery of the active region, and a P + type polysilicon layer inside the first trench located below the N + type polysilicon layer at the periphery of the active region; Electrically connect
There is provided a MOSFET characterized in that a drain electrode metal is formed on the back surface of a semiconductor chip.

  In the JBS according to the first aspect, the N− type epitaxial layer is formed on the N + type substrate, and the first oxide film (field oxide film) is formed on the entire surface of the N− type epitaxial layer. Further, a plurality of trench formation openings are formed in the first oxide film in the active region and the guard ring region, and a plurality of trenches are formed in the active region and the guard ring region through the plurality of trench formation openings, for example, reactive ion etching. It is formed by law.

  Preferably, in the JBS according to the first aspect, the width dimension of the trench in the peripheral portion of the active region of the semiconductor chip is made larger than the width dimension of other trenches in the active region of the semiconductor chip.

  Further preferably, in the JBS according to the first aspect, two annular trenches are formed in the guard ring region of the semiconductor chip.

  Preferably, in the JBS according to the first aspect, after the plurality of trenches are formed in the active region and the guard ring region of the semiconductor chip, the surface smoothing process is performed on the side surface and the bottom surface of each trench. In the surface smoothing process, an oxide film is formed on the side and bottom surfaces of each trench by, for example, a sacrificial oxidation process at a low temperature, and then the oxide film is peeled off. By performing this surface smoothing treatment, the leakage current can be reduced as compared with the case where the side and bottom surfaces of each trench are rough.

In the JBS according to claim 1, by introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of trenches, the lateral and vertical diffusion depths are reduced to about P-type layers of 0.1 to 0.2 μm and a concentration of the order of 10 ¹⁶ / cm ³ are formed along the side and bottom surfaces of the plurality of trenches. Specifically, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentration of the P-type layer formed by introducing and diffusing P-type impurities is set to the order of 10 ¹⁶ / cm ³ .

Further, in the JBS according to claim 1, the second oxide film is formed on the side surface and the bottom surface of the plurality of trenches, and the opening is formed on the second oxide film on the bottom surface of the plurality of trenches. A second oxide film is left. Specifically, only the second oxide film on the bottom surface of the trench is removed by etching, for example, by a reactive ion etching method or the like. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

In the JBS according to claim 1, the polysilicon is filled in the plurality of trenches, and the polysilicon filled in the plurality of trenches is doped with a P-type impurity to have a concentration of 10 A P + type polysilicon layer of the order of ¹⁸ / cm ³ or more is formed inside the plurality of trenches.

  Preferably, in the JBS according to claim 1, the polysilicon is not selectively filled in each trench, but is deposited on the entire surface of the semiconductor chip, and then in the trenches. The polysilicon is filled into the trenches by etching back the excess polysilicon so that only the polysilicon remains.

  Furthermore, in the JBS according to claim 1, the P + type polysilicon layer formed in the plurality of trenches and the P type layer and the N− type epitaxial layer through the opening of the second oxide film on the bottom surface of the plurality of trenches. For example, a heavy metal as a lifetime killer such as platinum is deposited and diffused.

  In the JBS of the first aspect, the third oxide film is formed on the surface of the P + type polysilicon layer formed inside the plurality of trenches.

  Preferably, in the JBS according to claim 1, when the third oxide film is formed on the surface of the P + type polysilicon layer inside the trench, the third oxide is applied only on the surface of the P + type polysilicon layer inside the trench. Instead of forming a film, a third oxide film is formed on the entire surface of the semiconductor chip. Specifically, the third oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Further, in the JBS according to claim 1, the N + type layer forming opening is formed in the oxide film at the peripheral portion of the semiconductor chip, and the N + type layer is formed at the peripheral portion of the semiconductor chip through the N + type layer forming opening. Is done.

  In the JBS according to claim 1, the barrier metal forming opening is formed in the oxide film in the active region of the semiconductor chip, and the field plate opening is formed in the oxide film on the P + type polysilicon layer in the guard ring region of the semiconductor chip. Formed.

  Furthermore, in the JBS according to the first aspect, the barrier metal is formed in the active region of the semiconductor chip through the opening for forming the barrier metal, for example, by a sputtering method, a vapor deposition method or the like.

  Further, in the JBS according to claim 1, the anode electrode metal is formed on the barrier metal by, for example, a sputtering method, a vapor deposition method or the like, and is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip through the field plate opening. The field plate is formed by, for example, sputtering or vapor deposition, and the EQR electrode metal is formed on the N + type layer on the periphery of the semiconductor chip by, for example, sputtering or vapor deposition.

  In the JBS according to claim 1, the final protective film is formed on the entire surface of the semiconductor chip, the contact opening for connecting to the anode electrode metal is formed in the final protective film, and the cathode electrode metal is formed on the back surface of the semiconductor chip. Formed.

  Preferably, in the JBS according to the first aspect, the sintering process for ensuring the ohmic contact is appropriately performed in an inert gas of about 400 ° C., for example.

  In other words, in the JBS according to claim 1, in the active region of the semiconductor chip, the Schottky junction by the barrier metal and the N− type epitaxial layer and the PN junction by the P type layer and the N− type epitaxial layer coexist. is doing. Furthermore, a guard ring region is disposed outside the active region.

  Specifically, in the JBS according to claim 1, the trench in the peripheral portion of the active region of the semiconductor chip, the trench in the guard ring region outside the active region of the semiconductor chip, and the N− type epitaxial layer outside the guard ring region. A breakdown voltage maintaining structure is formed by the layer and the N + type layer at the periphery of the semiconductor chip.

  Furthermore, since the JBS according to claim 1 employs a trench structure, according to the JBS according to claim 1, the lateral dimensions of the semiconductor chip can be made smaller than when the trench structure is not employed. can do.

  In the JBS according to the first aspect, a field plate is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. Therefore, according to the JBS of the first aspect, the vacant layer at the time of reverse bias is formed in the peripheral portion of the semiconductor chip as compared with the case where the field plate is not formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. Can be extended to the side.

Furthermore, in the JBS according to the first aspect, the concentration of the P + type polysilicon layer inside the plurality of trenches is set to the order of 10 ¹⁸ / cm ³ or more. Therefore, according to the JBS of the first aspect, the P + type polysilicon layer in the active region of the semiconductor chip and the barrier metal can be brought into ohmic contact, and as a result, the potential of the anode electrode metal can be set during forward bias. It can be transmitted to the P + type polysilicon layer inside the trench faster than the P type layer formed along the side surface of the trench.

  In other words, in the JBS according to the first aspect, a high concentration P + type polysilicon layer is formed inside the plurality of trenches. Therefore, according to the JBS of the first aspect, when the forward bias is applied, the lower side of the P + type polysilicon layer is lower than the case where the high concentration P + type polysilicon layer is not formed inside the plurality of trenches. The sky layer can be extended to the cathode electrode side, and as a result, the N-type epitaxial layer space between two adjacent trenches can be easily pinched off.

  In particular, in the JBS according to claim 1, in the forward bias, in the N− type epitaxial layer space pinched off between two adjacent trenches, the electric field and the barrier metal and the N− type in the horizontal direction are reversed. The electric fields pushed downward from the N-type Schottky junction interface with the epitaxial layer cancel each other, and the Resurf effect occurs, and the electric field at the N-type Schottky junction interface between the barrier metal and the N-type epitaxial layer is greatly increased. Go down. Therefore, according to the JBS according to claim 1, the leakage current increases as the electric field at the N-type Schottky junction interface between the barrier metal and the N-type epitaxial layer increases during forward bias, It is possible to suppress a decrease in carrier mobility and to drive the JBS safely.

  The diffusion rate of heavy metals in the polysilicon layer is faster than the diffusion rate of heavy metals in the N− type epitaxial layer, and the diffusion rate of heavy metals in the oxide film is slower than the diffusion rate of heavy metals in the N− type epitaxial layer. In view of the above, in the JBS of the first aspect, as described above, the P + type polysilicon layer formed inside the plurality of trenches and the P type layer through the opening of the second oxide film on the bottom surface of the plurality of trenches, and Heavy metal is diffused into the N-type epitaxial layer. Therefore, according to the JBS of the first aspect, heavy metal can be locally diffused in the P-type layer and the N − -type epitaxial layer near the opening of the second oxide film on the bottom surface of the trench. In other words, according to the JBS of the first aspect, the carrier lifetime of the P-type layer and the N− type epitaxial layer on the side of the second oxide film on the side surface of the trench can be maintained long.

  In the JBS according to the first aspect, as described above, a high-concentration P + type polysilicon layer is formed inside the plurality of trenches. That is, in the JBS according to claim 1, holes serving as majority carriers are not sufficiently activated in a plurality of trenches in which high-concentration P + type polysilicon layers are formed. Mobility is not high enough. Therefore, according to the JBS of the first aspect, as carriers injected into the N − type epitaxial layer through the opening of the second oxide film at the bottom of the trench, and the P type layer directly below the trench, The amount of holes injected can be limited.

  Furthermore, in the JBS according to the first aspect, as described above, heavy metal as a lifetime killer is introduced into the P-type layer immediately below the second oxide film opening at the bottom of the trench. That is, in the JBS according to the first aspect, the lifetime of holes as carriers is shortened in the P-type layer immediately below the opening of the second oxide film on the bottom surface of the trench. Therefore, according to the JBS of the first aspect, as carriers injected into the N − type epitaxial layer through the opening of the second oxide film at the bottom of the trench, and the P type layer directly below the trench, The amount of holes injected can be limited.

  Moreover, in JBS of Claim 1, as above-mentioned, the 2nd oxide film is left on the side surface of a trench. That is, in the JBS according to claim 1, holes as carriers are injected into the N− type epitaxial layer through the second oxide film on the side of the trench, the side surface of the trench, and the P type layer on the side thereof. Never happen.

  Further, in the JBS according to the first aspect, the interface between the P-type layer formed along the side surface of the trench and the barrier metal above it forms a P-type Schottky junction interface. That is, in the JBS according to the first aspect, at the time of forward bias, the P-type Schottky junction interface between the P-type layer formed along the side surface of the trench and the upper barrier metal is connected in the opposite direction. Functions as a P-type Schottky barrier diode. Therefore, according to the JBS of the first aspect, the injection amount of holes as carriers injected into the N− type epitaxial layer via the P type layer formed along the side surfaces of the barrier metal and the trench is limited. can do.

That is, according to the JBS of the first aspect, when the concentration of the P + type polysilicon layer in the trench is less than the order of 10 ¹⁸ / cm ^3, or when heavy metal as a lifetime killer is generated from the bottom of the trench. When not introduced, when the oxide film is not formed on the side surface of the trench, or when the P-type Schottky junction interface is not configured by the P-type layer and the barrier metal formed along the side surface of the trench Rather, the amount of holes injected as carriers into the N − type epitaxial layer can be limited.

  In the JBS according to the first aspect, an N− type epitaxial layer constituting an interface between the barrier metal and the N type Schottky junction is disposed between two adjacent trenches. Therefore, in the JBS according to claim 1, when the reverse bias is applied, the airborne layer below the N-type Schottky junction interface between two adjacent trenches is lower than the lower end of the airborne layer directly below the trench. The lower end is located at a high position. As a result, according to the JBS of the first aspect, when the reverse bias is applied, the gap between the lower end of the vacant layer just below the N-type Schottky junction interface between two adjacent trenches and the N + type substrate. Residual holes can be present.

  Further, in the JBS according to the first aspect, as described above, a high-concentration P + type polysilicon layer is formed inside the trench, and holes serving as majority carriers are sufficiently activated inside the trench. Not. Further, the heavy metal diffused in the P + type polysilicon layer inside the trench is locally distributed in the P type layer and the N− type epitaxial layer directly below the opening of the oxide film at the bottom of the trench. .

  Therefore, in the JBS according to the first aspect, when the reverse bias is applied, the JBS exists between the lower end of the empty layer immediately below the N-type Schottky junction interface between two adjacent trenches and the N + type substrate. N-type epitaxial layer and P-type layer immediately below the oxide film opening at the bottom of the trench where heavy metals are locally distributed when the residual holes (holes) are switched from reverse bias to forward bias; At the same time, it is quickly returned to the anode electrode metal through the high-concentration P + type polysilicon layer inside the trench that is close to the potential of the anode electrode metal.

That is, according to the JBS of the first aspect, when heavy metal is not locally distributed in the P-type layer and the N− type epitaxial layer directly below the bottom surface of the trench, or in the inside of the trench, 10 ¹⁸ / cm ^3. The reverse recovery time (trr) can be shortened and soft recovery can be achieved as compared with the case where a high-concentration P + type polysilicon layer is not formed.

By the way, in the JBS according to claim 1, it exists between the lower end of the empty layer immediately below the N-type Schottky junction interface between two adjacent trenches and the N + type substrate at the time of reverse bias. A portion of residual holes (holes) is a low concentration of the order of 10 ¹⁶ / cm ³ formed along the side surface of the trench at the time of switching from the reverse bias to the forward bias. The layer is returned to the anode electrode metal via the P-type Schottky junction interface between the P-type layer and the barrier metal.

  In the MOSFET according to claim 2, the N− type epitaxial layer is formed on the N + type substrate, and the first oxide film (field oxide film) is formed on the entire surface of the N− type epitaxial layer. Further, a P-type layer forming opening is formed in the first oxide film of the active region, and a P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening. .

  Preferably, in the MOSFET according to claim 2, considering that the diffusion depth of the P-type impurity is increased by the subsequent heat treatment, the diffusion depth of the P-type impurity at this stage is set to be shallower than the target diffusion depth. Is done.

  Furthermore, in the MOSFET according to claim 2, the second oxide film is formed on the surface of the P-type layer during the diffusion of the P-type impurity. A plurality of first trench formation openings are formed in the oxide film of the active region and the guard ring region, and a plurality of first trenches are formed in the active region and the guard ring region through the plurality of first trench formation openings, for example, It is formed by a reactive ion etching method or the like.

  Preferably, in the MOSFET according to claim 2, the width dimension of the trench in the peripheral portion of the active region of the semiconductor chip is made larger than the width dimension of other trenches in the active region of the semiconductor chip.

  Preferably, in the MOSFET according to claim 2, one annular first trench is formed in a guard ring region of the semiconductor chip.

  Furthermore, preferably, in the MOSFET according to claim 2, after the plurality of first trenches are formed in the active region and the guard ring region of the semiconductor chip, the surface smoothing process is performed on the side surface and the bottom surface of each first trench. Is called. In the surface smoothing process, for example, an oxide film is formed on the side surface and the bottom surface of each first trench by a sacrificial oxidation process at a low temperature, and then the oxide film is peeled off. By performing the surface smoothing process, it is possible to reduce the leakage current as compared with the case where the side surface and the bottom surface of each first trench are rough.

In the MOSFET according to claim 2, lateral and vertical diffusion depths are obtained by introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches. Is about 0.1 to 0.2 μm and a P-type layer having a concentration of the order of 10 ¹⁶ / cm ³ is formed along the side and bottom surfaces of the plurality of first trenches. Specifically, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentration of the P-type layer formed by introducing and diffusing P-type impurities is set to the order of 10 ¹⁶ / cm ³ .

Furthermore, in the MOSFET according to claim 2, the third oxide film is formed on the side surface and the bottom surface of the plurality of first trenches, and the opening is formed on the third oxide film on the bottom surface of the plurality of first trenches. A third oxide film is left on the side surface of one trench. Specifically, for example, only the third oxide film on the bottom surface of the first trench is etched away by, for example, reactive ion etching. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

In the MOSFET according to claim 2, the polysilicon is filled in the plurality of first trenches, and the polysilicon filled in the plurality of first trenches is doped with a P-type impurity. A P + type polysilicon layer having a concentration of 10 ¹⁸ / cm ³ or more is formed in the plurality of first trenches.

  Preferably, in the MOSFET according to claim 2, the polysilicon is not selectively filled in each first trench, but is deposited on the entire surface of the semiconductor chip, and then the plurality of first The polysilicon is filled into the plurality of first trenches by etching back the excess polysilicon so that the polysilicon remains only in the trench.

  Furthermore, in the MOSFET according to claim 2, a P + type polysilicon layer formed inside the plurality of first trenches and a P type just below the P + type polysilicon layer and the openings of the third oxide films on the bottom surfaces of the plurality of first trenches. Heavy metal as a lifetime killer such as platinum is deposited and diffused on the layer and the N− type epitaxial layer.

  In the MOSFET according to claim 2, the fourth oxide film is formed on the surface of the P + type polysilicon layer formed in the plurality of first trenches.

  Preferably, in the MOSFET according to claim 2, when the fourth oxide film is formed on the surface of the P + type polysilicon layer inside the first trench, only the surface of the P + type polysilicon layer inside the first trench is formed. In addition, the fourth oxide film is not selectively formed, but the fourth oxide film is formed on the entire surface of the semiconductor chip. Specifically, the fourth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Further, in the MOSFET according to claim 2, the N + type layer forming opening is formed in the oxide film in the peripheral portion of the semiconductor chip and the oxide film in the portion excluding the first trench in the central portion of the active region of the semiconductor chip. It is formed.

  In the MOSFET according to claim 2, the N + type layer is formed in the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip excluding the first trench through the N + type layer formation opening. Is done. Specifically, in the MOSFET according to claim 2, the N + type layer formed in the central portion of the active region of the semiconductor chip functions as a MOSFET cell.

  In the MOSFET according to claim 2, a fifth oxide film is formed on the surface of the N + type layer. Specifically, the fifth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Further, in the MOSFET according to claim 2, a plurality of second trench formation openings are formed in the oxide film in the central portion of the active region, and a plurality of openings are formed in the central portion of the active region via the plurality of second trench formation openings. The second trench is formed by, for example, reactive ion etching.

  Preferably, in the MOSFET according to claim 2, after the plurality of second trenches are formed in the central portion of the active region of the semiconductor chip, the surface smoothing process is performed on the side surfaces and the bottom surface of each second trench. In the surface smoothing process, an oxide film is formed on the side surface and the bottom surface of each second trench by, for example, a sacrificial oxidation process at a low temperature, and then the oxide film is peeled off. By performing this surface smoothing treatment, it is possible to reduce the leakage current and to obtain a high-quality gate oxide film as compared with the case where the side surface and the bottom surface of each second trench are rough. More specifically, the surface of the side surfaces of the second trenches that become the channel portions of the MOSFET is subjected to the surface smoothing process, so that the channel of electrons that are the majority carriers passing through the channel than when the surface smoothing process is not performed. Mobility (μch) can be improved.

  According to a second aspect of the present invention, the thermal oxide film that becomes the gate oxide film of the MOSFET is formed on the side and bottom surfaces of the plurality of second trenches.

  Preferably, in the MOSFET according to claim 2, the thermal oxide film that becomes the gate oxide film of the MOSFET is formed under an extremely clean atmosphere gas.

  Furthermore, in the MOSFET according to claim 2, polysilicon is filled in the plurality of second trenches and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the inside of the plurality of second trenches The N + type polysilicon layer is formed in the plurality of second trenches by doping N type impurities into the polysilicon filled in and the polysilicon deposited in a part of the peripheral portion of the active region of the semiconductor chip. And formed on a part of the peripheral edge of the active region of the semiconductor chip. The N + type polysilicon layer formed on a part of the peripheral edge of the active region of the semiconductor chip is used later for routing the gate wiring.

  Preferably, in the MOSFET according to claim 2, the polysilicon is selectively filled in each second trench and is selectively deposited on a part of the peripheral portion of the active region of the semiconductor chip. Instead, the polysilicon is deposited on the entire surface of the semiconductor chip, and then the excess polysilicon is etched back so that the polysilicon remains inside the second trenches and part of the periphery of the active region of the semiconductor chip. Is done.

  In the MOSFET according to claim 2, the sixth oxide film is formed on the entire surface of the semiconductor chip. Specifically, the sixth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Furthermore, in the MOSFET according to claim 2, an oxide film in a portion excluding the second trench in a central portion of the active region, a partial oxide film on the N + type polysilicon layer in a peripheral portion of the active region, a guard ring region Electrode metal forming openings are formed in a part of the oxide film on the P + type polysilicon layer and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip.

  In the MOSFET according to claim 2, the electrode metal is formed on the entire surface of the semiconductor chip by, for example, a sputtering method, a vapor deposition method, or the like.

  Furthermore, in the MOSFET according to claim 2, the electrode metal on the entire surface of the semiconductor chip includes a source electrode metal at a central portion of the active region, a gate wiring routing electrode metal at a peripheral portion of the active region, and a gate wiring routing electrode metal. The source electrode metal, guard ring electrode metal, and EQR electrode metal at the peripheral part of the semiconductor chip are electrically separated and patterned.

  As a result, in the MOSFET according to claim 2, the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal are electrically connected.

  Furthermore, in the MOSFET according to claim 2, the source electrode metal positioned above the N + type polysilicon layer at the peripheral portion of the active region and the first electrode positioned below the N + type polysilicon layer at the peripheral portion of the active region. A P + type polysilicon layer inside one trench is electrically connected.

  In the MOSFET of the second aspect, the drain electrode metal is formed on the back surface of the semiconductor chip.

  Preferably, in the MOSFET according to the second aspect, the sintering process for ensuring the ohmic contact is appropriately performed in an inert gas of about 400 ° C., for example.

  That is, in the MOSFET according to the second aspect, the guard ring region is disposed outside the active region.

  Specifically, in the MOSFET according to claim 2, the first trench in the peripheral portion of the active region of the semiconductor chip, the first trench in the guard ring region outside the active region of the semiconductor chip, and the outside of the guard ring region. A breakdown voltage maintaining structure is formed by the N− type epitaxial layer and the N + type layer at the periphery of the semiconductor chip.

  Furthermore, since the MOSFET according to claim 2 employs a trench structure, according to the MOSFET according to claim 2, the lateral dimension of the semiconductor chip is made smaller than when the trench structure is not employed. can do.

  In the MOSFET according to claim 2, the guard ring electrode metal is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. Therefore, according to the MOSFET of the second aspect, the vacant layer at the time of the reverse bias is formed on the semiconductor chip as compared with the case where the guard ring electrode metal is not formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. It can be extended to the peripheral side.

Furthermore, in the MOSFET according to claim 2, the concentration of the P + type polysilicon layer inside the plurality of first trenches is set to the order of 10 ¹⁸ / cm ³ or more. Therefore, according to the MOSFET of the second aspect, the P + type polysilicon layer in the active region of the semiconductor chip and the source electrode metal can be brought into ohmic contact. As a result, the potential of the source electrode metal can be obtained during forward bias. Can be transmitted to the P + type polysilicon layer inside the first trench faster than the P type layer formed along the side surface of the first trench.

  In other words, in the MOSFET according to claim 2, a high-concentration P + type polysilicon layer is formed inside the plurality of first trenches. Therefore, according to the MOSFET of the second aspect, the lower portion of the P + type polysilicon layer is more forward biased than in the case where the high concentration P + type polysilicon layer is not formed in the plurality of first trenches. The side empty layer can be extended to the drain electrode side, and as a result, the space between two adjacent first trenches can be easily pinched off.

  Specifically, in the MOSFET according to claim 2, since a high concentration P + type polysilicon layer is formed inside the plurality of first trenches, in the MOSFET according to claim 2, the P + type polysilicon layer is formed. The empty layer extending to the lower N− type epitaxial layer quickly reaches the N + type substrate side. As a result, the electric field strength is maximum in the lower portion of the first trench compared to the other portions. That is, in the MOSFET according to the second aspect, the electric field strength at the lower portion of the second trench is relatively low, and the electric field strength applied to the gate oxide film on the side surface of the second trench is kept low. Therefore, according to the MOSFET of the second aspect, the gate oxide film on the side surface of the second trench is made safer than the case where the electric field strength applied to the gate oxide film on the side surface of the second trench is increased. Can be protected.

  Specifically, according to the MOSFET of the second aspect, the electric field intensity below the second trench can be made lower than the MOSFET in which the first trench is not provided and only the second trench is provided. .

  The diffusion rate of heavy metals in the polysilicon layer is faster than the diffusion rate of heavy metals in the N− type epitaxial layer, and the diffusion rate of heavy metals in the oxide film is slower than the diffusion rate of heavy metals in the N− type epitaxial layer. In view of the above, in the MOSFET according to claim 2, as described above, the P + type polysilicon layer formed inside the plurality of first trenches and the oxide film opening at the bottom surface of the plurality of first trenches are used to form the P type. Heavy metal is diffused into the layer and the N-type epitaxial layer. Therefore, according to the MOSFET of the second aspect, heavy metal can be locally diffused in the P-type layer and the N − -type epitaxial layer near the opening of the oxide film on the bottom surface of the first trench. That is, according to the MOSFET of the second aspect, the carrier lifetimes of the P-type layer and the N− type epitaxial layer on the side of the oxide film on the side surface of the first trench can be maintained long.

  In the MOSFET of the second aspect, as described above, a high-concentration P + type polysilicon layer is formed inside the plurality of first trenches. That is, in the MOSFET according to claim 2, holes serving as majority carriers are not sufficiently activated inside the plurality of first trenches where the high-concentration P + type polysilicon layer is formed, and the positive The hole mobility is not high enough. Therefore, according to the MOSFET of the second aspect, the N-type epitaxial layer is implanted through the inside of the first trench, the opening of the oxide film on the bottom surface of the first trench, and the P-type layer immediately below the opening. The amount of holes injected as carriers can be limited.

  Furthermore, in the MOSFET according to the second aspect, as described above, heavy metal as a lifetime killer is introduced into the P-type layer directly below the opening of the oxide film on the bottom surface of the first trench. That is, in the MOSFET according to claim 2, the lifetime of holes as carriers is shortened in the P-type layer immediately below the opening of the oxide film on the bottom surface of the first trench. Therefore, according to the MOSFET of the second aspect, the N-type epitaxial layer is implanted through the inside of the first trench, the opening of the oxide film on the bottom surface of the first trench, and the P-type layer immediately below the opening. The amount of holes injected as carriers can be limited.

  In the MOSFET according to claim 2, as described above, the oxide film is left on the side surface of the first trench. That is, in the MOSFET according to claim 2, holes as carriers are introduced into the N− type epitaxial layer through the oxide film on the side of the first trench, the side surface of the first trench, and the P type layer on the side thereof. It is never injected.

That is, according to the MOSFET of the second aspect, when the concentration of the P + type polysilicon layer inside the first trench is made less than 10 ¹⁸ / cm ³ order, or from the bottom surface of the first trench, the lifetime killer As compared with the case where no heavy metal is introduced or the case where no oxide film is formed on the side surface of the first trench, the amount of holes injected as carriers into the N − -type epitaxial layer can be limited.

  Furthermore, in the MOSFET according to claim 2, as described above, a high-concentration P + type polysilicon layer is formed inside the first trench, and there are sufficient holes serving as majority carriers inside the first trench. Not activated. Further, the heavy metal diffused in the P + type polysilicon layer inside the first trench is locally applied to the P type layer and the N− type epitaxial layer directly below the oxide film opening at the bottom of the first trench. Distributed.

  Therefore, in the MOSFET according to claim 2, the residual holes existing between the lower end of the vacant layer immediately below the portion between the two adjacent first trenches and the N + type substrate at the time of reverse bias. An N-type epitaxial layer and a P-type layer directly below the opening of the oxide film at the bottom of the first trench in which heavy metal is locally distributed when switching from reverse bias to forward bias, Then, it is quickly returned to the source electrode metal through the high-concentration P + type polysilicon layer inside the first trench, which has a potential close to that of the source electrode metal.

That is, according to the MOSFET of the second aspect, when heavy metal is not locally distributed in the P-type layer and the N− type epitaxial layer directly below the bottom surface of the first trench, or in the interior of the first trench, The reverse recovery time (trr) of the anti-parallel connected diode built in the MOSFET can be shortened compared with the case where a high-concentration P + type polysilicon layer of ¹⁸ / cm ³ or more is not formed, and soft recovery can be performed. Can be achieved.

  Furthermore, in the MOSFET according to the second aspect, the N + type layer is formed above the P type layer in a portion adjacent to the peripheral portion of the active region in the central portion of the active region. Therefore, according to the MOSFET of the second aspect, the N + type layer above the P type layer in the portion adjacent to the peripheral portion of the active region in the central portion of the active region can be used as the MOSFET cell.

  Preferably, in the MOSFET according to claim 2, two first trenches are arranged adjacent to each other at a central portion of the active region and a peripheral portion of the active region, and are shallower than the depth of the first trench therebetween. A P-type layer is formed, but instead of the two first trenches and the P-type layer between them, one first trench spanning the central part of the active region and the peripheral part of the active region is provided. It is also possible to form.

  In the MOSFET according to claim 2, two first trenches are disposed adjacent to each other at the central portion of the active region and the peripheral portion of the active region, and a P + type polysilicon layer is formed inside each first trench. Therefore, according to the MOSFET of the second aspect, the amount of holes injected as carriers into the N − type epitaxial layer can be limited, and the influence of the parasitic diode generated in this portion can be reduced. it can.

  In the MOSFET according to claim 3, the N− type epitaxial layer is formed on the N + type substrate, and the first oxide film (field oxide film) is formed on the entire surface of the N− type epitaxial layer. Further, a P-type layer forming opening is formed in the first oxide film of the active region, and a P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening. .

  Preferably, in the MOSFET according to claim 3, the diffusion depth of the P-type impurities is increased by the subsequent heat treatment, and the diffusion depth of the P-type impurities at this stage is set to be shallower than the target diffusion depth. Is done.

  Furthermore, in the MOSFET according to the third aspect, the second oxide film is formed on the surface of the P-type layer during the diffusion of the P-type impurity. A plurality of first trench formation openings are formed in the oxide film of the active region and the guard ring region, and a plurality of first trenches are formed in the active region and the guard ring region through the plurality of first trench formation openings, for example, It is formed by a reactive ion etching method or the like.

  Preferably, in the MOSFET according to claim 3, the width dimension of the trench in the peripheral portion of the active region of the semiconductor chip is made larger than the width dimension of other trenches in the active region of the semiconductor chip.

  Preferably, in the MOSFET according to claim 3, one annular first trench is formed in the guard ring region of the semiconductor chip.

  Furthermore, preferably, in the MOSFET according to claim 3, after the plurality of first trenches are formed in the active region and the guard ring region of the semiconductor chip, the surface smoothing process is performed on the side surface and the bottom surface of each first trench. Is called. In the surface smoothing process, for example, an oxide film is formed on the side surface and the bottom surface of each first trench by a sacrificial oxidation process at a low temperature, and then the oxide film is peeled off. By performing the surface smoothing process, it is possible to reduce the leakage current as compared with the case where the side surface and the bottom surface of each first trench are rough.

In the MOSFET according to claim 3, lateral and vertical diffusion depths are obtained by introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches. Is about 0.1 to 0.2 μm and a P-type layer having a concentration of the order of 10 ¹⁶ / cm ³ is formed along the side and bottom surfaces of the plurality of first trenches. Specifically, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentration of the P-type layer formed by introducing and diffusing P-type impurities is set to the order of 10 ¹⁶ / cm ³ .

Furthermore, in the MOSFET according to claim 3, the third oxide film is formed on the side surface and the bottom surface of the plurality of first trenches, and the opening is formed on the third oxide film on the bottom surface of the plurality of first trenches. A third oxide film is left on the side surface of one trench. Specifically, for example, only the third oxide film on the bottom surface of the first trench is etched away by, for example, reactive ion etching. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

In the MOSFET according to claim 3, the polysilicon is filled in the plurality of first trenches, and the polysilicon filled in the plurality of first trenches is doped with a P-type impurity. A P + type polysilicon layer having a concentration of 10 ¹⁸ / cm ³ or more is formed in the plurality of first trenches.

  Preferably, in the MOSFET according to claim 3, the polysilicon is not selectively filled into each first trench, but is deposited on the entire surface of the semiconductor chip, and then the plurality of first The polysilicon is filled into the plurality of first trenches by etching back the excess polysilicon so that the polysilicon remains only in the trench.

  Furthermore, in the MOSFET according to claim 3, the P + type polysilicon layer formed inside the plurality of first trenches and the P type directly below the P + type polysilicon layer and the openings of the third oxide films on the bottom surfaces of the plurality of first trenches. Heavy metal as a lifetime killer such as platinum is deposited and diffused on the layer and the N− type epitaxial layer.

  In the MOSFET according to claim 3, the fourth oxide film is formed on the surface of the P + type polysilicon layer formed inside the plurality of first trenches.

  Preferably, in the MOSFET according to claim 3, when the fourth oxide film is formed on the surface of the P + type polysilicon layer inside the first trench, only the surface of the P + type polysilicon layer inside the first trench is formed. In addition, the fourth oxide film is not selectively formed, but the fourth oxide film is formed on the entire surface of the semiconductor chip. Specifically, the fourth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Furthermore, in the MOSFET according to claim 3, the N + type layer forming opening has a portion adjacent to the peripheral portion of the active region among the oxide film on the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip. The oxide film is formed in a portion excluding the first trench and excluding the first trench.

  In the MOSFET according to claim 3, a portion adjacent to the peripheral portion of the active region is excluded from the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip through the N + type layer forming opening. An N + type layer is formed in the portion except for the first trench. Specifically, in the MOSFET according to claim 3, the N + type layer is not formed in a portion adjacent to the peripheral portion of the active region in the central portion of the active region of the semiconductor chip, and the P type layer is formed in that portion. Left behind. Further, the P-type layer left in that portion functions as a diode connected in reverse parallel to the MOSFET together with the P-type (PB) layer located below the N + type layer in the central portion (cell region) of the active region. .

  More specifically, when an N + type layer is formed in a portion adjacent to the periphery of the active region in the central portion of the active region of the semiconductor chip, a parasitic npn transistor is formed in that portion, and the periphery of the active region is formed. When the holes and residual holes injected into the lower part of the part and the guard ring region return to the source electrode metal at the time of reverse bias, this parasitic npn transistor may be operated. In view of this point, in the MOSFET according to claim 3, as described above, the N + type layer is not formed in the portion adjacent to the peripheral portion of the active region in the central portion of the active region of the semiconductor chip. The P-type layer is left in the part.

  Preferably, in the MOSFET according to claim 3, a portion of the central portion of the active region of the semiconductor chip where the N + type layer adjacent to the peripheral portion of the active region is not formed, that is, as a diode connected in reverse parallel to the MOSFET. The width of the functioning part is set to half the width of the cell, but instead, the width of that part is set to the width of one cell, or the width of that part is set to 1.5 cells. Set the width of the part, set the width of the part to the width of two cells, set the width of the part to the width of 2.5 cells, or the width of the part described above It is also possible to set an arbitrary width other than the width.

  In the MOSFET according to claim 3, a fifth oxide film is formed on the surface of the N + type layer. Specifically, the fifth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Furthermore, in the MOSFET according to claim 3, a plurality of second trench formation openings are formed in the oxide film in the central portion of the active region, and a plurality of openings are formed in the central portion of the active region via the plurality of second trench formation openings. The second trench is formed by, for example, reactive ion etching.

  Preferably, in the MOSFET according to the third aspect, after the plurality of second trenches are formed in the central portion of the active region of the semiconductor chip, the surface smoothing process is performed on the side surface and the bottom surface of each second trench. In the surface smoothing process, an oxide film is formed on the side surface and the bottom surface of each second trench by, for example, a sacrificial oxidation process at a low temperature, and then the oxide film is peeled off. By performing this surface smoothing treatment, it is possible to reduce the leakage current and to obtain a high-quality gate oxide film as compared with the case where the side and bottom surfaces of each second trench are rough. More specifically, the surface of the side surfaces of the second trenches serving as the channel portions of the MOSFET is subjected to the surface smoothing process, so that the channel of electrons that are majority carriers passing through the channel than the case where the surface smoothing process is not performed. Mobility (μch) can be improved.

  According to a third aspect of the present invention, the thermal oxide film that becomes the gate oxide film of the MOSFET is formed on the side and bottom surfaces of the plurality of second trenches.

  Preferably, in the MOSFET according to the third aspect, the thermal oxide film serving as the gate oxide film of the MOSFET is formed under an extremely clean atmosphere gas.

  Furthermore, in the MOSFET according to claim 3, polysilicon is filled in the plurality of second trenches, and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the inside of the plurality of second trenches. The N + type polysilicon layer is formed in the plurality of second trenches by doping N type impurities into the polysilicon filled in and the polysilicon deposited in a part of the peripheral portion of the active region of the semiconductor chip. And formed on a part of the peripheral edge of the active region of the semiconductor chip. The N + type polysilicon layer formed on a part of the peripheral edge of the active region of the semiconductor chip is used later for routing the gate wiring.

  Preferably, in the MOSFET according to claim 3, the polysilicon is selectively filled in each second trench and is selectively deposited on a part of the peripheral portion of the active region of the semiconductor chip. Instead, the polysilicon is deposited on the entire surface of the semiconductor chip, and then the excess polysilicon is etched back so that the polysilicon remains inside the second trenches and part of the periphery of the active region of the semiconductor chip. Is done.

  In the MOSFET according to claim 3, the sixth oxide film is formed on the entire surface of the semiconductor chip. Specifically, the sixth oxide film is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  Furthermore, in the MOSFET according to claim 3, an oxide film in a portion excluding the second trench in a central portion of the active region, a partial oxide film on the N + type polysilicon layer in a peripheral portion of the active region, and a guard ring region Electrode metal forming openings are formed in a part of the oxide film on the P + type polysilicon layer and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip.

  In the MOSFET according to the third aspect, the electrode metal is formed on the entire surface of the semiconductor chip by, for example, a sputtering method or a vapor deposition method.

  Furthermore, in the MOSFET according to claim 3, the electrode metal on the entire surface of the semiconductor chip includes a source electrode metal at the center of the active region, a gate wiring routing electrode metal at the peripheral portion of the active region, and a gate wiring routing electrode metal. The source electrode metal, guard ring electrode metal, and EQR electrode metal at the peripheral part of the semiconductor chip are electrically separated and patterned.

  As a result, in the MOSFET according to claim 3, the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal are electrically connected.

  Furthermore, in the MOSFET according to claim 3, the source electrode metal positioned above the N + type polysilicon layer at the peripheral portion of the active region and the first electrode positioned below the N + type polysilicon layer at the peripheral portion of the active region. A P + type polysilicon layer inside one trench is electrically connected.

  In the MOSFET according to claim 3, the drain electrode metal is formed on the back surface of the semiconductor chip.

  Preferably, in the MOSFET according to claim 3, the sintering process for ensuring ohmic contact is appropriately performed in an inert gas of, for example, about 400 ° C.

  That is, in the MOSFET according to the third aspect, the guard ring region is disposed outside the active region.

  Specifically, in the MOSFET according to claim 3, the first trench in the peripheral portion of the active region of the semiconductor chip, the first trench in the guard ring region outside the active region of the semiconductor chip, and the outside of the guard ring region. A breakdown voltage maintaining structure is formed by the N− type epitaxial layer and the N + type layer at the periphery of the semiconductor chip.

  Furthermore, since the MOSFET according to claim 3 employs a trench structure, according to the MOSFET according to claim 3, the lateral dimension of the semiconductor chip is made smaller than when the trench structure is not employed. can do.

  In the MOSFET according to claim 3, the guard ring electrode metal is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. Therefore, according to the MOSFET of the third aspect, the vacant layer at the time of reverse bias is formed on the semiconductor chip as compared with the case where the guard ring electrode metal is not formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip. It can be extended to the peripheral side.

Furthermore, in the MOSFET according to claim 3, the concentration of the P + type polysilicon layer inside the plurality of first trenches is set to the order of 10 ¹⁸ / cm ³ or more. Therefore, according to the MOSFET of the third aspect, the P + type polysilicon layer in the active region of the semiconductor chip and the source electrode metal can be brought into ohmic contact, and as a result, the potential of the source electrode metal can be obtained during forward bias. Can be transmitted to the P + type polysilicon layer inside the first trench faster than the P type layer formed along the side surface of the first trench.

  In other words, in the MOSFET according to claim 3, a high-concentration P + type polysilicon layer is formed inside the plurality of first trenches. Therefore, according to the MOSFET of the third aspect, the lower portion of the P + type polysilicon layer is more forward biased than in the case where the high concentration P + type polysilicon layer is not formed in the plurality of first trenches. The side empty layer can be extended to the drain electrode side, and as a result, the space between two adjacent first trenches can be easily pinched off.

  Specifically, in the MOSFET according to claim 3, since the high concentration P + type polysilicon layer is formed inside the plurality of first trenches, the MOSFET according to claim 3 has a P + type polysilicon layer. The empty layer extending to the lower N− type epitaxial layer quickly reaches the N + type substrate side. As a result, the electric field strength is maximum in the lower portion of the first trench compared to the other portions. That is, in the MOSFET according to the third aspect, the electric field strength in the lower portion of the second trench is relatively low, and the electric field strength applied to the gate oxide film on the side surface of the second trench is kept low. Therefore, according to the MOSFET of the third aspect, the gate oxide film on the side surface of the second trench can be made safer than the case where the electric field strength applied to the gate oxide film on the side surface of the second trench is increased. Can be protected.

  Specifically, according to the MOSFET of the third aspect, the electric field strength below the second trench can be made lower than the MOSFET in which the first trench is not provided and only the second trench is provided. .

  The diffusion rate of heavy metals in the polysilicon layer is faster than the diffusion rate of heavy metals in the N− type epitaxial layer, and the diffusion rate of heavy metals in the oxide film is slower than the diffusion rate of heavy metals in the N− type epitaxial layer. In view of the above, in the MOSFET according to claim 3, as described above, the P + type polysilicon layer formed inside the plurality of first trenches and the P type via the opening of the oxide film on the bottom surface of the plurality of first trenches. Heavy metal is diffused into the layer and the N-type epitaxial layer. Therefore, according to the MOSFET of the third aspect, heavy metal can be locally diffused into the P-type layer and the N − -type epitaxial layer near the opening of the oxide film on the bottom surface of the first trench. That is, according to the MOSFET of the third aspect, the carrier lifetimes of the P-type layer and the N− type epitaxial layer on the side of the oxide film on the side surface of the first trench can be maintained long.

  In the MOSFET according to the third aspect, as described above, a high concentration P + type polysilicon layer is formed inside the plurality of first trenches. That is, in the MOSFET according to claim 3, holes serving as majority carriers are not sufficiently activated inside the plurality of first trenches in which the high-concentration P + type polysilicon layer is formed, and the positive The hole mobility is not high enough. Therefore, according to the MOSFET of the third aspect, the N− type epitaxial layer is implanted through the inside of the first trench, the opening of the oxide film on the bottom surface of the first trench, and the P type layer immediately below the opening. The amount of holes injected as carriers can be limited.

  Furthermore, in the MOSFET according to the third aspect, as described above, heavy metal as a lifetime killer is introduced into the P-type layer directly below the opening of the oxide film on the bottom surface of the first trench. That is, in the MOSFET according to claim 3, the lifetime of holes as carriers is shortened in the P-type layer immediately below the opening of the oxide film on the bottom surface of the first trench. Therefore, according to the MOSFET of the third aspect, the N− type epitaxial layer is implanted through the inside of the first trench, the opening of the oxide film on the bottom surface of the first trench, and the P type layer immediately below the opening. The amount of holes injected as carriers can be limited.

  In the MOSFET according to the third aspect, as described above, the oxide film is left on the side surface of the first trench. In other words, in the MOSFET according to claim 3, holes as carriers are introduced into the N− type epitaxial layer through the oxide film on the side of the first trench, the side surface of the first trench, and the P type layer on the side thereof. It is never injected.

That is, according to the MOSFET of the third aspect, when the concentration of the P + type polysilicon layer in the first trench is less than 10 ¹⁸ / cm ³ order, or from the bottom surface of the first trench, the lifetime killer As compared with the case where no heavy metal is introduced or the case where no oxide film is formed on the side surface of the first trench, the amount of holes injected as carriers into the N − -type epitaxial layer can be limited.

  Furthermore, in the MOSFET according to claim 3, as described above, a high-concentration P + type polysilicon layer is formed inside the first trench, and there are sufficient holes serving as majority carriers inside the first trench. Not activated. Further, the heavy metal diffused in the P + type polysilicon layer inside the first trench is locally applied to the P type layer and the N− type epitaxial layer directly below the oxide film opening at the bottom of the first trench. Distributed.

  Therefore, in the MOSFET according to claim 3, the residual holes existing between the lower end of the vacant layer immediately below the portion between the two adjacent first trenches and the N + type substrate at the time of reverse bias. An N-type epitaxial layer and a P-type layer directly below the opening of the oxide film at the bottom of the first trench in which heavy metal is locally distributed when switching from reverse bias to forward bias, Then, it is quickly returned to the source electrode metal through the high-concentration P + type polysilicon layer inside the first trench, which has a potential close to that of the source electrode metal.

That is, according to the MOSFET of claim 3, when heavy metal is not locally distributed in the P-type layer and the N− type epitaxial layer immediately below the bottom surface of the first trench, or in the interior of the first trench, 10. The reverse recovery time (trr) of the anti-parallel connected diode built in the MOSFET can be shortened compared with the case where a high-concentration P + type polysilicon layer of ¹⁸ / cm ³ or more is not formed, and soft recovery can be performed. Can be achieved.

  The MOSFET according to claim 3 is a portion excluding a portion adjacent to the peripheral portion of the active region in the central portion of the active region of the semiconductor chip via the N + type layer forming opening, An N + type layer is formed in the oxide film except for the trench. That is, in the MOSFET according to the third aspect, the N + type layer is not formed in the portion adjacent to the peripheral portion of the active region in the central portion of the active region of the semiconductor chip, and the P type layer is left. Therefore, according to the MOSFET of the third aspect, the portion where the P-type layer is left can be operated as a diode connected in reverse parallel to the MOSFET.

  Preferably, in the MOSFET according to claim 3, two first trenches are arranged adjacent to each other at a central portion of the active region and a peripheral portion of the active region, and are shallower than the depth of the first trench therebetween. A P-type layer is formed, but instead of the two first trenches and the P-type layer between them, one first trench spanning the central part of the active region and the peripheral part of the active region is provided. It is also possible to form.

  In the MOSFET according to claim 3, two first trenches are disposed adjacent to each other at the central portion of the active region and the peripheral portion of the active region, and a P + type polysilicon layer is formed inside each first trench. Therefore, according to the MOSFET of the third aspect, the amount of holes injected as carriers into the N− type epitaxial layer can be limited, and the influence of the parasitic diode generated in this portion can be reduced. it can.

  Hereinafter, a first embodiment of the present invention will be described. 1 to 3 are cross-sectional views showing the manufacturing process of the JBS of the first embodiment, and FIG. 4 is a view showing the JBS of the first embodiment. Specifically, FIG. 4A is a plan view showing a part of the JBS of the first embodiment, and FIG. 4B is a cross-sectional view showing a part of the JBS of the first embodiment. FIG. 5 is a plan view seen through a part of the right half of the JBS of the first embodiment.

  When manufacturing the JBS of the first embodiment, first, as shown in FIG. 1A, an N− type epitaxial layer 2 is formed on an N + type substrate 1. Next, an oxide film (field oxide film) 3 is formed on the entire surface of the N − type epitaxial layer 2. Next, as shown in FIG. 1B, trench formation openings 3a, 3b, 3c are formed in the oxide film 3 in the central portion (cell region) A1 of the active region, and the trench formation opening 3d is the periphery of the active region. Trench formation openings 3e and 3f are formed in the oxide film 3 in the guard ring region A3.

  At the time of manufacturing the JBS of the first embodiment, as shown in FIG. 1C, the central portion (cell) of the active region is then passed through the trench formation openings 3a, 3b, 3c (see FIG. 1B). Trench 4a, 4b, 4c is formed in region A1 by, for example, reactive ion etching. A trench 4d is formed in the peripheral edge A2 of the active region through the trench formation opening 3d (see FIG. 1B), for example, by a reactive ion etching method or the like. Furthermore, trenches 4e and 4f are formed in the guard ring region A3 through the trench formation openings 3e and 3f (see FIG. 1B), for example, by a reactive ion etching method or the like.

  In the JBS of the first embodiment, as shown in FIG. 1C, the width dimension of the trench 4d in the outer peripheral portion A2 of the active region of the semiconductor chip (the horizontal dimension in FIG. 1C) is the same as that of the semiconductor chip. The width of the trenches 4a, 4b, 4c in the central portion (cell region) A1 of the active region (the size in the left-right direction in FIG. 1C) is made larger. In the JBS of the first embodiment, as shown in FIGS. 1C and 5, two annular trenches 4e and 4f are formed in the guard ring region A3 of the semiconductor chip.

  At the time of manufacturing the JBS of the first embodiment, next, as shown in FIG. 1C, the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 of the trenches 4a, 4b, 4c, 4d, 4e, 4f and Surface smoothing processing is performed on the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, and 4f2. In the surface smoothing process, the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2, etc. of the trenches 4a, 4b, 4c, 4d, 4e, 4f are obtained by sacrificial oxidation at a low temperature, for example. An oxide film (not shown) is formed on 4e2 and 4f2, and then the oxide film (not shown) is peeled off. By performing this surface smoothing treatment, the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the trenches 4a, 4b, 4c, 4d, 4e, 4f are obtained. Leakage current can be reduced as compared with the case where is rough.

At the time of manufacturing the JBS of the first embodiment, next, as shown in FIG. 2A, the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 of the trenches 4a, 4b, 4c, 4d, 4e, 4f and By introducing and diffusing P-type impurities into the N-type epitaxial layer 2 through the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, and 4f2 (see FIG. 1C), the lateral direction (FIG. 2A) P-type layers 5a, 5b, and 5c having a diffusion depth of about 0.1 to 0.2 μm and a concentration of the order of 10 ¹⁶ / cm ^3, and the vertical direction (the vertical direction of FIG. 2A). , 5d, 5e, 5f are side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 and bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the respective trenches 4a, 4b, 4c, 4d, 4e, 4f (FIG. 1). (C) Reference It is formed along the.

Specifically, when manufacturing the JBS of the first embodiment, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentrations of the P-type layers 5a, 5b, 5c, 5d, 5e, and 5f formed by introducing and diffusing P-type impurities are set to the order of 10 ¹⁶ / cm ³ .

At the time of manufacturing the JBS of the first embodiment, as shown in FIG. 2B, the oxide film 6 is then formed on the side surfaces 4a1, 4b1, 4c1, 4d1, side surfaces of the trenches 4a, 4b, 4c, 4d, 4e, 4f. 4e1, 4f1 and bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 (see FIG. 1C). Next, as shown in FIG. 2C, the openings 6a, 6b, 6c, 6d, 6e, 6f are formed in the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, and the bottom surfaces of the trenches 4a, 4b, 4c, 4d, 4e, 4f. 4f2 (see FIG. 1C) is formed on the oxide film 6 (see FIG. 2B), and the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, and 4f1 of the trenches 4a, 4b, 4c, 4d, 4e, 4f are formed. The oxide film 6 (see FIG. 2B) is left on 4f1 (see FIG. 1C). Specifically, the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 (see FIG. 1C) of the trenches 4a, 4b, 4c, 4d, 4e, 4f, for example, by reactive ion etching or the like. Only (see FIG. 2B) is removed by etching. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

At the time of manufacturing the JBS of the first embodiment, next, as shown in FIG. 3A, polysilicon is placed inside each of the trenches 4a, 4b, 4c, 4d, 4e, and 4f (see FIG. 1C). By filling the polysilicon filled in each of the trenches 4a, 4b, 4c, 4d, 4e, and 4f with a P-type impurity, a P + type poly having a concentration of 10 ¹⁸ / cm ³ or more is added. Silicon layers 7a, 7b, 7c, 7d, 7e, 7f are formed in the trenches 4a, 4b, 4c, 4d, 4e, 4f.

  Specifically, when the JBS of the first embodiment is manufactured, polysilicon is not selectively filled into the trenches 4a, 4b, 4c, 4d, 4e, and 4f (see FIG. 1C). 3A, polysilicon is deposited on the entire surface of the semiconductor chip, and then, as shown in FIG. 3B, each trench 4a, 4b, 4c, 4d, 4e, 4f ( The polysilicon is filled in the trenches 4a, 4b, 4c, 4d, 4e, and 4f by etching back the excess polysilicon so that the polysilicon remains only in the interior of FIG. 1C). The

  At the time of manufacturing the JBS of the first embodiment, P + type polysilicon layers 7a, 7b, and 7c formed in the trenches 4a, 4b, 4c, 4d, 4e, and 4f (see FIG. 1C) are then provided. , 7d, 7e, 7f (see FIG. 3B) and bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 (see FIG. 1C) of the trenches 4a, 4b, 4c, 4d, 4e, 4f. P-type layers 5a, 5b, 5c, 5d, 5e, and 5f are formed through openings 6a, 6b, 6c, 6d, 6e, and 6f (see FIG. 2C) of the oxide film 6 (see FIG. 2B). And heavy metal as a lifetime killer such as platinum is deposited and diffused in the N− type epitaxial layer 2 (see FIG. 3B).

  6 shows a diffusion region Bb of heavy metal such as platinum diffused in the P-type layer 5b and the N− type epitaxial layer 2 through the opening 6b (see FIG. 2C) of the oxide film 6, and the oxide film. 6 is a view showing a diffusion region Bc of heavy metal such as platinum diffused in the P-type layer 5c and the N− type epitaxial layer 2 through the opening 6c of FIG. 6 (see FIG. 2C). Although not shown in detail, in the JBS of the first embodiment, a heavy metal diffusion region similar to the heavy metal diffusion region Bb shown in FIG. 6 is formed in the P-type layers 5a and N through the opening 6a of the oxide film 6. Formed in − type epitaxial layer 2, formed in P type layer 5 d and N − type epitaxial layer 2 through opening 6 d of oxide film 6, and formed in P type layer 5 e and N − type through opening 6 e in oxide film 6. It is formed in epitaxial layer 2 and formed in P type layer 5 f and N − type epitaxial layer 2 through opening 6 f of oxide film 6.

  At the time of manufacturing the JBS of the first embodiment, as shown in FIG. 3 (B), it was then formed inside each trench 4a, 4b, 4c, 4d, 4e, 4f (see FIG. 1 (C)). Oxide films 8a, 8b, 8c, 8d, 8e, and 8f are formed on the surfaces of the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, and 7f.

  More specifically, in the JBS of the first embodiment, the P + type polysilicon layers 7a, 7b, 7c, 7d inside the trenches 4a, 4b, 4c, 4d, 4e, 4f (see FIG. 1C) are provided. When oxide films 8a, 8b, 8c, 8d, 8e, and 8f (see FIG. 3B) are formed on the surfaces of 7e and 7f, the trenches 4a, 4b, 4c, 4d, 4e, and 4f (see FIG. The oxide films 8a, 8b, 8c, 8d, 8e, and 8f (see FIG. 3B) are selected only on the surfaces of the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, and 7f inside Instead, the oxide films (8a, 8b, 8c, 8d, 8e, 8f) are formed on the entire surface of the semiconductor chip. Specifically, the oxide films 8a, 8b, 8c, 8d, 8e, and 8f are formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the JBS of the first embodiment, next, as shown in FIG. 3B, an N + type layer forming opening 3g is formed in the oxide film 3 at the peripheral edge A4 of the semiconductor chip, and the N + type layer forming An N + type layer 9 is formed on the peripheral edge A4 of the semiconductor chip through the opening 3g.

  At the time of manufacturing the JBS of the first embodiment, next, as shown in FIG. 3C, the barrier metal formation opening 3h is formed in the oxide film in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. The field plate openings 3i and 3j are formed in the oxide film 3 on the P + type polysilicon layers 7e and 7f in the guard ring region A3.

  At the time of manufacturing the JBS of the first embodiment, then, as shown in FIG. 3C, the active region has a central portion (cell region) A1 and a peripheral portion A2 of the active region through the barrier metal formation opening 3h. The barrier metal 10 is formed (for example, patterned) by, for example, a sputtering method or a vapor deposition method.

  Further, at the time of manufacturing the JBS of the first embodiment, as shown in FIG. 3C, the anode electrode metal 11 is formed (for example, patterned) on the barrier metal 10 by, for example, sputtering, vapor deposition, etc. Field plates 12a, 12b, and 12c are formed (for example, patterned) on the P + type polysilicons 7e and 7f in the guard ring region A3 of the semiconductor chip through the plate openings 3i and 3j by, for example, sputtering or vapor deposition. The EQR electrode metal 13 is formed (for example, patterned) on the N + type layer 9 at the peripheral edge A4 of the semiconductor chip by, for example, sputtering, vapor deposition or the like.

  At the time of manufacturing the JBS of the first embodiment, as shown in FIG. 3D, a final protective film 14 is then formed on the entire surface of the semiconductor chip, and a contact opening 14a for connecting to the anode electrode metal 11 is formed. Formed on the final protective film 14, the cathode electrode metal 15 is formed on the back surface of the semiconductor chip. Further, during the manufacture of the JBS of the first embodiment, a sintering process for ensuring ohmic contact is appropriately performed in an inert gas of about 400 ° C., for example.

  That is, in the JBS of the first embodiment, as shown in FIG. 4B, the barrier metal 10 and the N− type are formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region, as shown in FIG. A Schottky junction interface C1 formed by the epitaxial layer 2 and a PN junction interface C2 formed by the P-type layers 5a, 5b, 5c, 5d and the N-type epitaxial layer 2 coexist. Further, the guard ring region A3 is disposed outside the peripheral edge A2 of the active region.

  In detail, in the JBS of the first embodiment, as shown in FIG. 4B, the trench 4d in the peripheral portion A2 of the active region of the semiconductor chip and the guard ring region A3 outside the active region of the semiconductor chip are formed. A breakdown voltage maintaining structure is formed by the trenches 4e and 4f, the N− type epitaxial layer 2 outside the guard ring region A3, and the N + type layer 9 at the peripheral edge A4 of the semiconductor chip.

  Further, since the JBS of the first embodiment employs a trench structure, according to the JBS of the first embodiment, the lateral direction of the semiconductor chip (FIG. The dimension in B) can be reduced.

  FIG. 7 is a diagram showing the vacant layer D1 and the like when a reverse bias is applied to the JBS of the first embodiment.

  In the JBS of the first embodiment, as shown in FIG. 4B, field plates 12a, 12b, and 12c are formed on the P + type polysilicon layers 7e and 7f in the guard ring region A3 of the semiconductor chip. Yes. Therefore, in the JBS of the first embodiment, as shown in FIGS. 4B and 7, field plates 12a, 12b, and 12c are formed on the P + type polysilicon layers 7e and 7f in the guard ring region A3 of the semiconductor chip. The sky layer D1 at the time of reverse bias can be extended to the peripheral portion side (right side in FIG. 7) of the semiconductor chip, rather than the sky layer D1 ′ at the time of reverse bias when not formed.

Furthermore, in the JBS of the first embodiment, as shown in FIG. 4B, the P + type polysilicon layers 7a, 7b, 7c, 7d, and the like inside the trenches 4a, 4b, 4c, 4d, 4e, 4f, The concentrations of 7e and 7f are set to the order of 10 ¹⁸ / cm ³ or more. Therefore, according to the JBS of the first embodiment, the P + type polysilicon layers 7a, 7b, 7c in the central portion (cell region) A1 of the active region of the semiconductor chip and the barrier metal 10 can be brought into ohmic contact, As a result, at the time of forward bias, the potential of the anode electrode metal 11 is faster than that of the trenches 4a, 4b, 4c formed along the side surfaces of the trenches 4a, 4b, 4c. It can be transmitted to the internal P + type polysilicon layers 7a, 7b and 7c.

  In other words, in the JBS of the first embodiment, as shown in FIG. 4B, high-concentration P + type polysilicon layers 7a and 7b are formed in the trenches 4a, 4b, 4c, 4d, 4e, and 4f. , 7c, 7d, 7e, 7f are formed. Therefore, according to the JBS of the first embodiment, high-concentration P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, 7f are formed in the trenches 4a, 4b, 4c, 4d, 4e, 4f. As shown in FIG. 6, the vacant layer below the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, and 7f (the lower side in FIG. 6) (as shown in FIG. 6). The forward bias space-time layer) D2 can be extended to the cathode electrode 15 side (lower side in FIG. 6). As a result, the N − type epitaxial layer space 2 ′ between the two adjacent trenches 4b and 4c is reduced. It can be easily pinched off.

  Specifically, in the JBS of the first embodiment, as shown in FIG. 6, when forward biased, the N− type epitaxial layer space 2 ′ pinched off between two adjacent trenches 4 b and 4 c is horizontally The reverse electric field and the electric field pushed downward from the N-type Schottky junction interface C1 between the barrier metal 10 and the N-type epitaxial layer 2 cancel each other, and the Resurf effect occurs, and the barrier metal 10 and the N- The electric field at the N-type Schottky junction interface C1 with the type epitaxial layer 2 is greatly reduced. Therefore, according to the JBS of the first embodiment, the leakage current increases as the electric field at the N-type Schottky junction interface C1 between the barrier metal 10 and the N-type epitaxial layer 2 increases during forward bias. Or a decrease in carrier mobility, and the JBS can be operated safely.

  The diffusion rate of heavy metals in the P + polysilicon layers 7b and 7c is faster than the diffusion rate of heavy metals in the N− type epitaxial layer 2, and the diffusion rate of heavy metals in the oxide film 6 is higher than that of heavy metals in the N− type epitaxial layer 2. In view of the slower speed than the diffusion rate, in the JBS of the first embodiment, as shown in FIG. 6, the bottom surfaces of the P + type polysilicon layers 7b and 7c and the trenches 4b and 4c formed inside the trenches 4b and 4c. Heavy metals are diffused into the P-type layers 5b and 5c and the N− type epitaxial layer 2 through the openings 6b and 6c (see FIG. 2C) of the oxide film 6 of 4b2 and 4c2 (see FIG. 1C). . Therefore, according to the JBS of the first embodiment, heavy metals are applied to the P-type layers 5b and 5c and the N− type epitaxial layer 2 near the openings 6b and 6c of the oxide films 6 on the bottom surfaces 4b2 and 4c2 of the trenches 4b and 4c. (Bb, Bc) can be locally diffused. That is, according to the JBS of the first embodiment, the P-type layers 5b and 5c and the N − -type epitaxial layer on the side of the oxide film 6 on the side surfaces 4b1 and 4c1 (see FIG. 1C) of the trenches 4b and 4c. It is possible to maintain the lifetime of the second carrier for a long time.

  In the JBS of the first embodiment, as shown in FIG. 4B, high-concentration P + type polysilicon layers 7a, 7b, 7c are formed in the trenches 4a, 4b, 4c, 4d, 4e, 4f. , 7d, 7e, 7f are formed. That is, in the JBS of the first embodiment, the inside of each trench 4a, 4b, 4c, 4d, 4e, 4f in which high-concentration P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, 7f are formed. However, the holes serving as majority carriers are not sufficiently activated, and the hole mobility is not sufficiently high. Therefore, according to the JBS of the first embodiment, the inside of the trenches 4a, 4b, 4c, 4d, 4e, 4f and the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the trenches (see FIG. 1C) N− through the openings 6a, 6b, 6c, 6d, 6e, 6f (see FIG. 2C) of the oxide film 6 and the P-type layers 5a, 5b, 5c, 5d, 5e, 5f directly below the openings 6a, 6b, 6c, 6d, 6e, 6f. The amount of holes injected as carriers injected into the type epitaxial layer 2 can be limited.

  Furthermore, in the JBS of the first embodiment, as shown in FIG. 4B, the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the trenches 4a, 4b, 4c, 4d, 4e, 4f (FIG. 1 ( C)) to the P-type layers 5a, 5b, 5c, 5d, 5e, and 5f directly below the openings 6a, 6b, 6c, 6d, 6e, and 6f (see FIG. 2C). Heavy metals have been introduced as lifetime killer. In other words, in the JBS of the first embodiment, the openings 6a, 6b, 6c, 6d, and the openings 6a, 4b, 4c, 4d, 4e, and 4f of the oxide film 6 of the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, and 4f2 are formed. In the P-type layers 5a, 5b, 5c, 5d, 5e, and 5f immediately below 6e and 6f, the lifetime of holes as carriers is shortened. Therefore, according to the JBS of the first embodiment, the inside of the trenches 4a, 4b, 4c, 4d, 4e, 4f and the bottom surfaces 4a2, 4b2, 4c2, 4d2, the trenches 4a, 4b, 4c, 4d, 4e, 4f 4e2 and 4f2 through the openings 6a, 6b, 6c, 6d, 6e and 6f of the oxide film 6 and the P-type layers 5a, 5b, 5c, 5d, 5e and 5f directly below the N-type epitaxial layer 2 It is possible to limit the amount of holes injected as carriers to be injected.

  In the JBS of the first embodiment, as shown in FIG. 4B, the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 of the trenches 4a, 4b, 4c, 4d, 4e, 4f (FIG. 1 ( In (C), the oxide film 6 is left. That is, in the JBS of the first embodiment, the inside of the trenches 4a, 4b, 4c, 4d, 4e, 4f and the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, the sides of the trenches 4a, 4b, 4c, 4d, 4e, 4f Holes as carriers are not injected into the N − -type epitaxial layer 2 through the 4f1 oxide film 6 and the P-type layers 5a, 5b, 5c, 5d, 5e, and 5f on its side.

  Furthermore, in the JBS of the first embodiment, as shown in FIG. 6, P-type layers 5a, 4a1, 4b1, and 4c1 formed along the side surfaces 4a1, 4b1, and 4c1 (see FIG. 1C) of the trenches 4a, 4b, and 4c, The interface between 5b and 5c and the barrier metal 10 on the upper side constitutes a P-type Schottky junction interface C3. That is, in the JBS of the first embodiment, the P-type layers 5a, 5b, and 5c formed along the side surfaces 4a1, 4b1, and 4c1 of the trenches 4a, 4b, and 4c and the barrier metal 10 on the upper side are formed during forward bias. The P-type Schottky junction interface C3 functions as a P-type Schottky barrier diode connected in the opposite direction. Therefore, according to the JBS of the first embodiment, the N-type is formed via the P-type layers 5a, 5b, 5c formed along the side surfaces 4a1, 4b1, 4c1 of the barrier metal 10 and the trenches 4a, 4b, 4c. The amount of holes injected as carriers injected into the epitaxial layer 2 can be limited.

That is, according to the JBS of the first embodiment, the concentration of the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, 7f inside the trenches 4a, 4b, 4c, 4d, 4e, 4f is 10 ¹⁸ / When it is less than cm ³ order, or when heavy metal as a lifetime killer is not introduced from the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the trenches 4a, 4b, 4c, 4d, 4e, 4f When the oxide film 6 is not formed on the side surfaces 4a1, 4b1, 4c1, 4d1, 4e1, and 4f1 of the trenches 4a, 4b, 4c, 4d, 4e, and 4f, or the side surfaces 4a1, 4b1, and 4c1 of the trenches 4a, 4b, and 4c are formed. More than the case where the P-type Schottky junction interface C3 is not configured by the P-type layers 5a, 5b, 5c formed along 4c1 and the barrier metal 10, - it is possible to limit the amount of holes injected as carriers to the type epitaxial layer 2.

  Further, in the JBS of the first embodiment, as shown in FIG. 4B, N− which forms the barrier metal 10 and the N-type Schottky junction interface C1 between two adjacent trenches 4a and 4b. The N type epitaxial layer 2 which comprises the barrier metal 10 and the N type Schottky junction interface C1 is arranged between the two adjacent trenches 4b and 4c. Between the trenches 4c and 4d, the N − type epitaxial layer 2 constituting the barrier metal 10 and the N type Schottky junction interface C1 is disposed. Therefore, in the JBS of the first embodiment, as shown in FIGS. 4B and 7, at the time of reverse bias, the JBS is adjacent to the lower end of the vacant layer D1 directly below the trenches 4a, 4b, 4c, and 4d. The lower end of the empty layer D1 directly below the N-type Schottky junction interface C1 between the two trenches 4a, 4b, 4c, and 4d is located at a high position (upper position in FIG. 7). As a result, according to the JBS of the first embodiment, when the reverse bias is applied, the vacant layer D1 directly below the N-type Schottky junction interface C1 between the two adjacent trenches 4a, 4b, 4c, 4d Residual holes (holes) (see FIG. 6) can exist between the lower end and the N + type substrate 1.

  Furthermore, in the JBS of the first embodiment, as shown in FIG. 4B, high-concentration P + type polysilicon layers 7a, 7b, 7c, and trenches 4a, 4b, 4c, 4d, 4e, 4f 7d, 7e, and 7f are formed, and holes serving as majority carriers are not sufficiently activated in the trenches 4a, 4b, 4c, 4d, 4e, and 4f. Furthermore, as shown in FIG. 6, heavy metals (Bb, Bc) diffused into the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, 7f inside the trenches 4a, 4b, 4c, 4d, 4e, 4f. Are the openings 6a, 6b, 6c, 6d, 6e of the oxide film 6 in the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 (see FIG. 1C) of the trenches 4a, 4b, 4c, 4d, 4e, 4f. , 6f (see FIG. 2C), the P-type layers 5a, 5b, 5c, 5d, 5e, 5f and the N-type epitaxial layer 2 are distributed locally.

  Therefore, in the JBS of the first embodiment, as shown in FIG. 6, the lower end of the vacant layer D1 directly below the N-type Schottky junction interface C1 between the two adjacent trenches 4b and 4c during reverse biasing. And the residual holes (holes) existing between the N + type substrate 1 and the trenches 4b, in which heavy metals (Bb, Bc) are locally distributed when switching from the reverse bias to the forward bias. N-type epitaxial layer 2 and P-type layers 5b and 5c immediately below openings 6b and 6c (see FIG. 2C) of oxide film 6 on bottom surfaces 4b2 and 4c2 of 4c (see FIG. 1C), and 6 is quickly returned to the anode electrode metal 11 via the high-concentration P + type polysilicon layers 7b and 7c inside the trenches 4b and 4c having a potential close to that of the anode electrode metal 11 (path in FIG. 6). L1).

That is, according to the JBS of the first embodiment, the P-type layers 5a, 5b, 5c, just below the bottom surfaces 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 of the trenches 4a, 4b, 4c, 4d, 4e, 4f, In the case where heavy metals (Bb, Bc) are not locally distributed in 5d, 5e, 5f and N− type epitaxial layer 2, or in the trenches 4a, 4b, 4c, 4d, 4e, 4f, 10 ¹⁸ / cm ^3. The reverse recovery time (trr) can be shortened and soft recovery can be achieved as compared with the case where the P + type polysilicon layers 7a, 7b, 7c, 7d, 7e, 7f having a high concentration higher than the order are not formed. Can do.

Incidentally, in the JBS of the first embodiment, as shown in FIG. 6, the lower end of the vacant layer D1 directly below the N-type Schottky junction interface C1 between the two adjacent trenches 4b and 4c at the time of reverse bias is provided. And a portion of residual holes (holes) existing between the N + type substrate 1 and the side surfaces 4b1 and 4c1 of the trenches 4b and 4c (FIG. 1C) when switching from the reverse bias to the forward bias. ) P-type layer 5b of a low concentration of ¹⁰ 16 / cm ³ orders formed along the reference) single crystal layer, 5c, and, P-type shot and its P-type layer 5b, 5c and the barrier metal 10 It returns to the anode electrode metal 11 via the key junction interface C3 (path L2 in FIG. 6).

  Further, in the JBS of the first embodiment, as shown in FIG. 6, when switching from the reverse bias to the forward bias, residual electrons are returned to the cathode electrode metal 15 through the path L3.

  Hereinafter, a second embodiment of the present invention will be described. 8 to 11 are cross-sectional views showing the manufacturing process of the MOSFET according to the second embodiment, and FIG. 12 is a view showing the MOSFET according to the second embodiment. Specifically, FIG. 12A is a plan view showing a part of the MOSFET of the second embodiment, and FIG. 12B is a cross-sectional view showing a part of the MOSFET of the second embodiment. FIG. 13 is a plan view seen through a part of the right half of the MOSFET of the second embodiment. FIG. 14 is a plan view showing the right half of the outermost surface of the MOSFET of the second embodiment.

  At the time of manufacturing the MOSFET of the second embodiment, first, as shown in FIG. 8A, the N− type epitaxial layer 2 is formed on the N + type substrate 1. Next, an oxide film (field oxide film) 3 is formed on the entire surface of the N − type epitaxial layer 2. Next, a P-type layer forming opening 3a is formed in the oxide film 3 in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. Next, by introducing and diffusing P-type impurities through the P-type layer forming opening 3a, the P-type layer 21 is formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region.

  In the MOSFET of the second embodiment, considering that the diffusion depth of the P-type impurity is increased by the subsequent heat treatment, the diffusion depth of the P-type impurity in the stage shown in FIG. 8A is higher than the target diffusion depth. Set shallower.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 8B, an oxide film 22 is formed on the surface of the P-type layer 21 during the diffusion of P-type impurities. Next, trench formation openings 22a and 22b are formed in the oxide film 22 in the central portion (cell region) A1 of the active region, and trench formation openings 22c are formed in the oxide film 22 in the peripheral portion A2 of the active region. Opening 3b is formed in oxide film 3 in guard ring region A3. Next, the trenches 4a and 4b are formed in the central portion (cell region) A1 of the active region through the trench forming openings 22a and 22b, for example, by the reactive ion etching method, and the active region is formed through the trench forming opening 22c. The trench 4c is formed in the peripheral edge A2 by, for example, a reactive ion etching method, and the trench 4d is formed in the guard ring region A3 through, for example, the reactive ion etching method through the trench forming opening 3b.

  In the MOSFET of the second embodiment, as shown in FIG. 8B, the width dimension of the trench 4c in the peripheral edge A2 of the active region (the horizontal dimension in FIG. 8B) is the central portion ( The cell region is made larger than the width dimension of the trenches 4a and 4b in the A1 (the lateral dimension in FIG. 8B). In the MOSFET of the second embodiment, as shown in FIG. 8B, one annular trench 4d is formed in the guard ring region A3.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 8B, the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. The surface smoothing process is performed. In the surface smoothing process, for example, oxide films (not shown) are formed on the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d by a sacrificial oxidation process at a low temperature. Then, the oxide film (not shown) is peeled off. By performing the surface smoothing process, the leakage current can be reduced as compared with the case where the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d are rough. it can.

At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 8C, the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. By introducing and diffusing P-type impurities into the N − -type epitaxial layer 2 via (see FIG. 8B), the horizontal direction (left-right direction in FIG. 8C) and the vertical direction (FIG. 8C P-type layers 5a, 5b, 5c, 5d having a diffusion depth of about 0.1 to 0.2 μm and a concentration of the order of 10 ¹⁶ / cm ³ are formed in the trenches 4a, 4b, 4c, 4d side surfaces 4a1, 4b1, 4c1, 4d1 and bottom surfaces 4a2, 4b2, 4c2, 4d2 are formed. Specifically, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentration of the P-type layers 5a, 5b, 5c, and 5d formed by introducing and diffusing P-type impurities is set to the order of 10 ¹⁶ / cm ³ .

At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 9A, the oxide film 6 is formed on the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2 of the trenches 4a, 4b, 4c, 4d. , 4c2, 4d2 (see FIG. 8B). Next, openings 6a, 6b, 6c and 6d are formed in the oxide film 6 of the bottom surfaces 4a2, 4b2, 4c2 and 4d2 of the trenches 4a, 4b, 4c and 4d, and the side surfaces 4a1 and 4a1 of the trenches 4a, 4b, 4c and 4d. The oxide film 6 is left on 4b1, 4c1, and 4d1. Specifically, only the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2, and 4d2 of the trenches 4a, 4b, 4c, and 4d is removed by etching, for example, by reactive ion etching. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

At the time of manufacturing the MOSFET of the second embodiment, as shown in FIG. 9A, polysilicon is then filled in the trenches 4a, 4b, 4c, and 4d (see FIG. 8B). By doping the polysilicon filled in the trenches 4a, 4b, 4c, and 4d with a P-type impurity, the P + type polysilicon layers 7a, 7b, 7c having a concentration of 10 ¹⁸ / cm ³ or more 7d is formed inside each trench 4a, 4b, 4c, 4d.

  Specifically, when manufacturing the MOSFET of the second embodiment, polysilicon is not selectively filled into the trenches 4a, 4b, 4c, and 4d, but is deposited over the entire surface of the semiconductor chip. Next, the polysilicon is etched back so that the polysilicon remains only in the trenches 4a, 4b, 4c, and 4d, so that the polysilicon is etched in the trenches 4a, 4b, 4c, and 4d. Filled.

  At the time of manufacturing the MOSFET of the second embodiment, as shown in FIG. 9 (A), P + type polysilicon formed in the trenches 4a, 4b, 4c, 4d (see FIG. 8 (B)). Through the openings 6a, 6b, 6c, 6d of the oxide film 6 on the layers 7a, 7b, 7c, 7d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 8B) of the trenches 4a, 4b, 4c, 4d. Heavy metal as a lifetime killer such as platinum is deposited and diffused on the P-type layers 5a, 5b, 5c, 5d and the N-type epitaxial layer 2 directly below the lever.

  At the time of manufacturing the MOSFET of the second embodiment, as shown in FIG. 9B, P + type polysilicon formed in the trenches 4a, 4b, 4c and 4d (see FIG. 8B) Oxide films 8a, 8b, 8c and 8d are formed on the surfaces of the layers 7a, 7b, 7c and 7d.

  Specifically, when the MOSFET of the second embodiment is manufactured, the surface of the P + type polysilicon layers 7a, 7b, 7c, 7d inside the trenches 4a, 4b, 4c, 4d (see FIG. 8B) is formed. When the oxide films 8a, 8b, 8c and 8d are formed, the oxide films 8a, 8b and 8c are formed only on the surfaces of the P + type polysilicon layers 7a, 7b, 7c and 7d in the trenches 4a, 4b, 4c and 4d. , 8d are not selectively formed, but an oxide film is formed on the entire surface of the semiconductor chip. Specifically, the oxide films 8a, 8b, 8c, and 8d are formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 9C, the N + type layer forming openings 3c and 22d are formed in the oxide film 3 on the peripheral edge A4 of the semiconductor chip and the activity of the semiconductor chip. It is formed on the oxide film 22 in a portion excluding the trenches 4a and 4b (see FIG. 8B) in the central portion (cell region) A1 of the region. Next, the N + type layer 9 is formed in the peripheral edge portion A4 of the semiconductor chip through the N + type layer forming opening 3c, and the central portion (cell region) of the active region of the semiconductor chip is formed through the N + type layer forming opening 22d. ) An N + type layer 23 is formed in a portion of A1 excluding the trenches 4a and 4b (see FIG. 8B).

  Specifically, in the MOSFET of the second embodiment, the N + type layer 23 formed in the central portion (cell region) A1 of the active region of the semiconductor chip functions as a MOSFET cell.

  At the time of manufacturing the MOSFET of the second embodiment, an oxide film 24 is then formed on the surfaces of the N + type layers 23 and 9 as shown in FIG. Specifically, the oxide film 24 is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 10A, trench formation openings 24a and 24b are formed in the oxide film 24 in the central portion (cell region) A1 of the active region. Next, trenches 25a and 25b are formed in the central portion (cell region) A1 of the active region via the trench formation openings 24a and 24b, for example, by reactive ion etching.

  Next, when the MOSFET of the second embodiment is manufactured, the surface smoothing process is performed on the side surfaces and the bottom surface of each of the trenches 25a and 25b. In the surface smoothing process, an oxide film (not shown) is formed on the side and bottom surfaces of the trenches 25a and 25b by, for example, a sacrificial oxidation process at a low temperature, and then the oxide film (not shown) is peeled off. By performing the surface smoothing process, the leakage current can be reduced as compared with the case where the side and bottom surfaces of the trenches 25a and 25b are rough, and a high-quality gate oxide film can be obtained. Specifically, by performing the surface smoothing process on the side surfaces of the trenches 25a and 25b serving as the channel portions of the MOSFET, the electrons of the majority carriers passing through the channel are more than when the surface smoothing process is not performed. Channel mobility (μch) can be improved.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 10B, a thermal oxide film 26 serving as the gate oxide film of the MOSFET is formed on the side and bottom surfaces of the trenches 25a and 25b. Specifically, when the MOSFET of the second embodiment is manufactured, the thermal oxide film 26 that becomes the gate oxide film of the MOSFET is formed under an extremely clean atmosphere gas.

  At the time of manufacturing the MOSFET of the second embodiment, as shown in FIG. 10B, polysilicon is then trenched in trenches 25a and 25b in a portion corresponding to the cross section along the line AA in FIG. The polysilicon filled in the active region of the semiconductor chip and deposited on the peripheral portion A2 of the active region of the semiconductor chip, and the polysilicon filled in the trenches 25a and 25b and the polycrystal deposited on the peripheral portion A2 of the active region of the semiconductor chip. By doping the silicon with N-type impurities, N + -type polysilicon layers 27a, 27b, and 27c are formed in the trenches 25a and 25b and in the peripheral portion A2 of the active region of the semiconductor chip. The N + type polysilicon layer 27c formed at the peripheral edge A2 of the active region of the semiconductor chip is used later for routing the gate wiring.

  On the other hand, in the portion corresponding to the cross section along the line BB in FIG. 12A, polysilicon is filled in the trenches 25a and 25b, and the periphery A2 of the active region of the semiconductor chip is formed. By partially depositing and doping the polysilicon filled in the trenches 25a and 25b and the polysilicon deposited on a part of the peripheral portion A2 of the active region of the semiconductor chip with N-type impurities N + type polysilicon layers 27a, 27b and 27c ′ (see FIG. 11A) are formed in the trenches 25a and 25b and in a part of the peripheral portion A2 of the active region of the semiconductor chip. The N + type polysilicon layer 27c ′ (see FIG. 11A) formed on a part of the peripheral edge A2 of the active region of the semiconductor chip is used later for routing the gate wiring.

  Specifically, during the manufacture of the MOSFET of the second embodiment, polysilicon is selectively filled into the trenches 25a and 25b, and is selectively applied to a part of the peripheral edge A2 of the active region of the semiconductor chip. Rather than being deposited, polysilicon is deposited over the entire surface of the semiconductor chip, and then excess polysilicon is left in the trenches 25a, 25b and in part of the periphery A2 of the active region of the semiconductor chip. The polysilicon is etched back.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 10C, an oxide film 28 is formed on the entire surface of the semiconductor chip. Specifically, the oxide film 28 is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 11A, in the portion corresponding to the cross section along the line BB in FIG. Region) A1 except for trenches 25a and 25b (see FIG. 10A) in oxide region A1, a portion of oxide film on P + type polysilicon layer 7d in guard ring region A3, and the peripheral portion of the semiconductor chip Electrode metal forming openings 28a, 28b, 28d, and 28e are formed in a portion of the oxide film on the N + type layer 9 of A4.

  On the other hand, at this time, in the portion corresponding to the cross section along the line AA in FIG. 12A, as shown in FIG. 11B, the trench 25a, 25b (see FIG. 10A), a portion of the oxide film, a part of the oxide film on the N + type polysilicon layer 27c in the peripheral portion A2 of the active region, and a part of the guard ring region A3 on the P + type polysilicon layer 7d Electrode metal forming openings 28a, 28c, 28d, and 28e are formed in part of the oxide film and part of the oxide film on the N + type layer 9 at the peripheral edge A4 of the semiconductor chip.

  At the time of manufacturing the MOSFET of the second embodiment, an electrode metal is then formed on the entire surface of the semiconductor chip by, for example, sputtering or vapor deposition.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 11C, the electrode metal on the entire surface of the semiconductor chip is replaced with the source electrode metal 29a in the central portion (cell region) A1 of the active region, A gate wiring lead electrode metal 29b at the peripheral edge A2 of the active region, a source electrode metal 29c located on the peripheral edge (right side in FIG. 11C) side of the gate wiring leading electrode metal 29b, a guard ring electrode metal 29d, The semiconductor chip is electrically separated and patterned into the EQR electrode metal 29e at the peripheral edge A4 of the semiconductor chip.

  As a result, in the MOSFET of the second embodiment, as shown in FIGS. 11C and 13, the N + type polysilicon layer inside the trenches 25a and 25b (see FIG. 10A) functioning as gate electrodes. 27a, 27b and the gate wiring routing electrode metal 29b are electrically connected.

  At the time of manufacturing the MOSFET of the second embodiment, next, as shown in FIG. 11C, the source electrode metal 29a located above the N + type polysilicon layer 27c in the central portion (cell region) A1 of the active region The P + type polysilicon layer 7b inside the trench 4b (see FIG. 8B) located below the N + type polysilicon layer 27c in the central portion (cell region) A1 of the active region is electrically connected. Is done. Further, the source electrode metal 29c located above the N + type polysilicon layer 27c in the peripheral portion A2 of the active region and the trench 4c located below the N + type polysilicon layer 27c in the peripheral portion A2 of the active region (FIG. 8). The P + type polysilicon layer 7c inside (see (B)) is electrically connected.

  At the time of manufacturing the MOSFET of the second embodiment, the final protective film 14 is then formed on the entire surface of the semiconductor chip, as shown in FIG. Further, a contact opening 14 a for connecting to the source electrode metal 29 a is formed in the final protective film 14. A drain electrode metal 30 is formed on the back surface of the semiconductor chip.

  Further, when the MOSFET of the second embodiment is manufactured, as shown in FIG. 14, a gate electrode metal 31 electrically connected to the gate wiring lead electrode metal 29b is formed on the surface of the semiconductor chip. Furthermore, a gate pad 32 electrically connected to the gate electrode metal 31 is formed on the surface of the semiconductor chip. A source pad 33 electrically connected to the source electrode metals 29a and 29c is formed on the surface of the semiconductor chip.

  As a result, in the MOSFET of the second embodiment, as shown in FIG. 12, the N + type polysilicon layers 27a ′, 27a, and 27b function as gate electrodes. Further, the P-type layer 21 adjacent to the gate oxide film 26 on the side surfaces of the N + type polysilicon layers 27a ', 27a, and 27b functions as a vertical MOSFET channel.

  Specifically, during the manufacture of the MOSFET of the second embodiment, a sintering process for ensuring ohmic contact is appropriately performed in, for example, an inert gas at about 400 ° C.

  That is, in the MOSFET of the second embodiment, as shown in FIG. 12B, the guard ring region A3 is disposed outside the peripheral edge A2 of the active region (on the right side in FIG. 12B). Specifically, in the MOSFET according to the second embodiment, the trench 4c (see FIG. 8B) in the peripheral portion A2 of the active region of the semiconductor chip and the guard ring region outside the peripheral portion A2 of the active region of the semiconductor chip. A breakdown voltage maintaining structure is formed by the trench 4d of A3 (see FIG. 8B), the N− type epitaxial layer 2 outside the guard ring region A3, and the N + type layer 9 of the peripheral portion A4 of the semiconductor chip. .

  Furthermore, since the MOSFET according to the second embodiment employs a trench structure, according to the MOSFET according to the second embodiment, the lateral dimension of the semiconductor chip (FIG. 12) is greater than when the trench structure is not employed. (B) horizontal dimension) can be reduced.

  In the MOSFET of the second embodiment, as shown in FIG. 12B, the guard ring electrode metal 29d is formed on the P + type polysilicon layer 7d in the guard ring region A3 of the semiconductor chip. For this reason, according to the MOSFET of the second embodiment, the sky loss at the time of reverse bias is greater than the case where the guard ring electrode metal 29d is not formed on the P + type polysilicon layer 7d in the guard ring region A3 of the semiconductor chip. The layer D1 (see FIG. 7) can be extended to the peripheral edge side of the semiconductor chip.

Furthermore, in the MOSFET of the second embodiment, as shown in FIG. 12B, the P + type polysilicon layers 7a ′, 7a, 7a, 4a, 4d (see FIG. 8B) inside the trenches 4a, 4b, 4c, 4d The concentration of 7b, 7c, 7d is set to 10 ¹⁸ / cm ³ or more. Therefore, according to the MOSFET of the second embodiment, the P + type polysilicon layers 7a ′ and 7a in the central portion (cell region) A1 of the active region of the semiconductor chip and the source electrode metal 29a can be in ohmic contact, As a result, at the time of forward bias, the potential of the source electrode metal 29a is made faster than the P-type layers 5a ′ and 5a formed along the side surfaces of the trench 4a, and the P + -type polysilicon layers 7a ′ and 7a inside the trench 4a. Can tell.

  In other words, in the MOSFET of the second embodiment, as shown in FIG. 12B, a high-concentration P + type polysilicon layer is formed inside the trenches 4a, 4b, 4c, and 4d (see FIG. 8B). 7a ', 7a, 7b, 7c, 7d are formed. Therefore, according to the MOSFET of the second embodiment, compared to the case where the high concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d are not formed in the trenches 4a, 4b, 4c, 4d. When the forward bias is applied, the empty layer D2 (see FIG. 6) below the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d is connected to the drain electrode 30 side (the lower side of FIG. 12B). As a result, the space 2 ′ (see FIG. 6) between two adjacent trenches can be easily pinched off.

  Specifically, in the MOSFET of the second embodiment, the high concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d are formed inside the trenches 4a, 4b, 4c, 4d. In the MOSFET of the second embodiment, the sky layer that extends to the N− type epitaxial layer 2 below the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d quickly reaches the N + type substrate 1 side. . As a result, the electric field strength is maximum in the lower portions of the trenches 4a, 4b, 4c, and 4d as compared with other portions. That is, in the MOSFET of the second embodiment, the electric field strength in the lower portion of the trenches 25a and 25b (see FIG. 10B) is relatively low, and the gate oxide film 26 on the side surfaces of the trenches 25a and 25b is applied. Electric field strength can be kept low. Therefore, according to the MOSFET of the second embodiment, the gate oxidation on the side surfaces of the trenches 25a and 25b is higher than the case where the electric field strength applied to the gate oxide film 26 on the side surfaces of the trenches 25a and 25b is higher. The membrane 26 can be safely protected.

  Incidentally, a MOSFET generally has output characteristics as shown in FIG. Specifically, the gate voltage at the time of SW (switching) from VG1 (OFF mode) to VGn (ON mode) and at the time of SW (switching) from VGn (ON mode) to VG1 (OFF mode) is shown in FIG. (B) Go back and forth in the arrow 行 っ. In addition, inside the MOSFET device, the shape of the airborne layer in the ON mode is like the “ON airborne layer shape” in FIG. 20A, and the shape of the airborne layer in the OFF mode is shown in FIG. It becomes like the “OFF spacetime layer shape” in 20 (A). That is, when SW (switching) from VG1 (OFF mode) to VGn (ON mode) and SW (switching) from VGn (ON mode) to VG1 (OFF mode), the shape of the sky layer is shown in FIG. The arrow 中 in 20 (A) goes back and forth.

  Specifically, in the MOSFET of the second embodiment, a trench 25b and a gate oxide film 26 (see FIG. 10B) are arranged between adjacent trenches 4a and 4b (see FIG. 8B). Therefore, the interval between the adjacent trenches 4a and 4b is wider than the JBS of the first embodiment. In addition, the sky layer extends from the trenches 25a and 25b concentrically along the bottoms of the trenches 25a and 25b. For this reason, in the MOSFET of the second embodiment, the shape of the vacant layer in the OFF mode is the “OFF vacant layer shape” in FIG.

  That is, in the MOSFET of the second embodiment, as shown in FIG. 20 (A), the OFF spacetime layer shape is from the PN junction surface of the bottom surfaces 4a2 and 4b2 (see FIG. 8 (B)) of the trenches 4a and 4b. While spreading downward, it spreads downward from the gate oxide film 26 (see FIG. 10B) of the trench 25b. Specifically, in the MOSFET of the second embodiment, the PN junction surfaces of the bottom surfaces 4a2 and 4b2 of the trenches 4a and 4b are disposed at a deeper position than the gate oxide film 26 of the trench 25b. Therefore, in the MOSFET of the second embodiment, the boundary portion between the N− type epitaxial layer 2 below the trenches 4a and 4b and the N + type substrate 1 (see FIG. 12B) (in FIG. 20A). The electric field strength at the mark) is the highest.

  On the other hand, in the MOSFET of the second embodiment, the thickness of the N− type epitaxial layer 2 (see FIG. 12B) below the trench 25b (see FIG. 10B) is the trenches 4a and 4b (see FIG. 8). It is thicker than the thickness of the N− type epitaxial layer 2 below (see (B)). Therefore, in the MOSFET of the second embodiment, the electric field strength below the trench 25b is lower than the electric field strength below the trenches 4a and 4b.

  In other words, in the MOSFET of the second embodiment, the vacant layers extending simultaneously from the trenches 4a and 4b (see FIG. 8B) and the trench 25b (see FIG. 10B) cancel each other, and the Resurf effect is obtained. Something happens. As a result, according to the MOSFET of the second embodiment, the electric field intensity below the trench 25b can be made lower than the MOSFET in which the trenches 4a and 4b are not provided and only the trench 25b is provided.

  In the MOSFET of the second embodiment, in the ON mode, the VDS voltage applied to the PN junction around the trenches 4a and 4b (see FIG. 8B) gradually decreases, and the trench 25b functioning as a gate electrode (FIG. 10). The gate voltage of VGn (On mode) is applied to the N + type polysilicon layer 27b (see FIG. 10B) inside (see (B)). Therefore, due to the capacitor effect formed by the N + type polysilicon layer 27b inside the trench 25b, the gate oxide film 26 (see FIG. 10B), and the N− type epitaxial layer 2 (see FIG. 10B), Many electrons are accumulated. As a result, the N − type epitaxial layer 2 is further changed to N type, while the P type layer 21 (see FIG. 10B) adjacent to the gate oxide film 26 is changed from “P type” → “P− type” → “ It is inverted from “N-type” to “N-type”. Then, as shown in FIG. 20A, a “channel” is formed in the P-type layer 21 adjacent to the gate oxide film 26 on the side surface of the trench 25b, and a path through which “electron current” flows is formed. This “electron current” path is preferably a wide path.

  In other words, the portion between the trench 4b (see FIG. 8B) and the trench 25b (see FIG. 10B) in the “ON spacetime layer shape” in FIG. If it is close to 4b and far from the trench 25b, a wide "electron current" path is secured.

  The diffusion rate of heavy metal in the polysilicon layer is faster than the diffusion rate of heavy metal in the N − type epitaxial layer 2, and the diffusion rate of heavy metal in the oxide film 6 is higher than the diffusion rate of heavy metal in the N − type epitaxial layer 2. In view of the slow point, in the MOSFET of the second embodiment, as shown in FIG. 12B, P + type polysilicon formed in the trenches 4a, 4b, 4c, and 4d (see FIG. 8B). Openings 6a, 6b, 6c, 6d in the oxide film 6 in the layers 7a ', 7a, 7b, 7c, 7d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 8B) of the trenches 4a, 4b, 4c, 4d Heavy metal is diffused into the P-type layers 5a′5a, 5b, 5c, 5d and the N − -type epitaxial layer 2 via (see FIG. 9A). Therefore, according to the MOSFET of the second embodiment, the P-type layer immediately below the openings 6a, 6b, 6c, 6d of the oxide film 6 in the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. Heavy metals (Bb, Bc (see FIG. 6)) can be locally diffused in 5a′5a, 5b, 5c, 5d and the N− type epitaxial layer 2. That is, according to the MOSFET of the second embodiment, the P-type layers 5a′5a, 5b, 5c, 5d on the side of the oxide film 6 of the side surfaces 4a1, 4b1, 4c1, 4d1 of the trenches 4a, 4b, 4c, 4d. In addition, the carrier lifetime of the N − type epitaxial layer 2 can be maintained long.

  Further, in the MOSFET of the second embodiment, as shown in FIG. 12B, a high-concentration P + type polysilicon layer 7a ′ is placed inside the trenches 4a, 4b, 4c, and 4d (see FIG. 8B). , 7a, 7b, 7c, 7d are formed. That is, in the MOSFET of the second embodiment, a majority carrier is formed in the trenches 4a, 4b, 4c, and 4d in which the high-concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d are formed. Holes are not sufficiently activated, and hole mobility is not sufficiently high. Therefore, according to the MOSFET of the second embodiment, the inside of the trenches 4a, 4b, 4c, 4d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d (see FIG. 8B) The oxide film 6 is injected into the N − type epitaxial layer 2 through the openings 6a, 6b, 6c, 6d (see FIG. 9A) and the P type layers 5a′5a, 5b, 5c, 5d immediately below the openings 6a, 6b, 6c, 6d. The amount of holes injected as carriers can be limited.

  Furthermore, in the MOSFET of the second embodiment, as shown in FIG. 12B, the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 8B) of the trenches 4a, 4b, 4c, 4d. Heavy metal as a lifetime killer is introduced into the P-type layers 5a′5a, 5b, 5c, and 5d directly below the openings 6a, 6b, 6c, and 6d (see FIG. 9A). That is, in the MOSFET of the second embodiment, the P-type layer 5a′5a immediately below the openings 6a, 6b, 6c, 6d of the oxide film 6 in the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. , 5b, 5c, 5d, the lifetime of holes as carriers is shortened. Therefore, according to the MOSFET of the second embodiment, the openings 6a, 6b in the oxide films 6 in the trenches 4a, 4b, 4c, 4d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. , 6c, 6d and the P-type layers 5a′5a, 5b, 5c, 5d directly below them, the amount of holes injected as carriers injected into the N− type epitaxial layer 2 can be limited.

  In the MOSFET of the second embodiment, as shown in FIG. 12B, the oxide film is not formed on the side surfaces 4a1, 4b1, 4c1, 4d1 (see FIG. 8B) of the trenches 4a, 4b, 4c, 4d. 6 is left. That is, in the MOSFET of the second embodiment, the oxide films 6 on the insides of the trenches 4a, 4b, 4c and 4d, the side surfaces 4a1, 4b1, 4c1 and 4d1 of the trenches 4a, 4b, 4c and 4d, Holes as carriers are not injected into the N− type epitaxial layer 2 through the P type layers 5a′5a, 5b, 5c, and 5d.

That is, according to the MOSFET of the second embodiment, the concentration of the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d inside the trenches 4a, 4b, 4c, and 4d is less than the order of 10 ¹⁸ / cm ^3. Or when no heavy metal as a lifetime killer is introduced from the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d, or the side surfaces 4a1, 4b, 4c, 4d of the trenches 4a, 4b, 4c, 4d. The amount of holes injected as carriers into the N − -type epitaxial layer 2 can be limited as compared with the case where the oxide film 6 is not formed on 4b1, 4c1, and 4d1.

  Furthermore, in the MOSFET of the second embodiment, as shown in FIG. 12B, a high-concentration P + type polysilicon layer 7a ′ is formed inside the trenches 4a, 4b, 4c, and 4d (see FIG. 8B). , 7a, 7b, 7c, and 7d are formed, and holes serving as majority carriers in the trenches 4a, 4b, 4c, and 4d are not sufficiently activated. Further, the heavy metal diffused in the P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d inside the trenches 4a, 4b, 4c, 4d is the bottom surfaces 4a2, 4b2, 4c2 of the trenches 4a, 4b, 4c, 4d. , 4d2 (see FIG. 8B) through the openings 6a, 6b, 6c, 6d (see FIG. 9A) of the oxide film 6, the P-type layers 5a ′, 5a, 5b, 5c directly below the openings 6a, 6b, 6c, 6d 5d and locally distributed in the N− type epitaxial layer 2.

  Therefore, in the MOSFET of the second embodiment, as shown in FIG. 12B, immediately below the portion between two adjacent trenches 4a, 4b, and 4c (see FIG. 8B) at the time of reverse bias. The residual holes (holes) (see FIG. 6) existing between the lower end of the empty layer D1 (see FIG. 6) and the N + type substrate 1 are switched from the reverse bias to the forward bias. Openings 6a, 6b in the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2 (see FIG. 8B) of the trenches 4a, 4b, 4c in which heavy metals (Bb, Bc (see FIG. 6)) are locally distributed. N-type epitaxial layer 2 and P-type layers 5a′5a, 5b, and 5c directly below 6c (see FIG. 9A), and trenches 4a that are close to the potentials of source electrode metals 29a and 29c, High concentration P + type policy inside 4b, 4c Con layer 7a ', 7a, 7b, through 7c, the source electrode metal 29a, are quickly returned to 29c.

That is, according to the MOSFET of the second embodiment, as shown in FIG. 12B, directly below the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d (see FIG. 8B). In the case where heavy metal is not locally distributed in the P-type layers 5a′5a, 5b, 5c, 5d and the N− type epitaxial layer 2, or in the order of 10 ¹⁸ / cm ^{3 in} the trenches 4a, 4b, 4c, 4d The reverse recovery time (trr) of the reverse-parallel connected diode built in the MOSFET can be made shorter than when the high-concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d are not formed. And soft recovery can be achieved.

  Furthermore, in the MOSFET of the second embodiment, as shown in FIG. 12B, the N + type layer 23 (see FIG. 9C) is formed in the active region in the central portion (cell region) A1 of the active region. It is formed on the upper side of the P-type layer 21 in a portion adjacent to the peripheral edge A2 (that is, a portion between the P + -type polysilicon layer 7b and the N + -type polysilicon layer 27b in FIG. 12B). Therefore, according to the MOSFET of the second embodiment, the portion adjacent to the peripheral portion A2 of the active region (that is, the P + type polysilicon layer in FIG. 12B) in the central portion (cell region) A1 of the active region. The N + -type layer 23 (see FIG. 9C) above the P-type layer 21 in the portion between 7b and the N + -type polysilicon layer 27b can serve as a MOSFET cell.

  In the MOSFET of the second embodiment, as shown in FIG. 12B, two trenches 4b and 4c (FIG. 8B) are formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. )) Are arranged adjacent to each other, and a P-type layer 21 shallower than the depth of the trenches 4b and 4c is formed between the trenches 4b and 4c. However, in the modification of the MOSFET of the second embodiment, Instead of the two trenches 4b and 4c and the P-type layer 21 between them, as shown in FIG. 21B, it straddles the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. It is also possible to form one trench, form a P-type layer 5bc, form an oxide film 6, and form a P + type polysilicon layer 7bc. FIG. 21 is a view showing a modification of the MOSFET of the second embodiment. Specifically, FIG. 21A is a plan view showing a part of a modification of the MOSFET of the second embodiment, and FIG. 21B shows a part of a modification of the MOSFET of the second embodiment. FIG.

  In the MOSFET of the second embodiment, as shown in FIG. 12B, two trenches 4b and 4c (FIG. 8B) are formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. )) Are arranged adjacent to each other, and the P + type polysilicon layers 7b and 7c are formed in the trenches 4b and 4c. Therefore, according to the MOSFET of the second embodiment, the N− type epitaxial layer 2 is formed. The amount of holes injected as carriers can be limited, and the influence of the parasitic diode generated in this portion can be reduced.

  Hereinafter, a third embodiment of the present invention will be described. 15 to 18 are cross-sectional views showing the manufacturing process of the MOSFET according to the third embodiment, and FIG. 19 is a view showing the MOSFET according to the third embodiment. Specifically, FIG. 19A is a plan view showing a part of the MOSFET of the third embodiment, and FIG. 19B is a cross-sectional view showing a part of the MOSFET of the third embodiment. A plan view seen through a part of the right half of the MOSFET of the third embodiment is similar to the plan view of the MOSFET of the second embodiment shown in FIG. The plan view showing the right half of the outermost surface of the MOSFET of the third embodiment is the same as the plan view of the MOSFET of the second embodiment shown in FIG.

  At the time of manufacturing the MOSFET of the third embodiment, first, as shown in FIG. 15A, the N− type epitaxial layer 2 is formed on the N + type substrate 1. Next, an oxide film (field oxide film) 3 is formed on the entire surface of the N − type epitaxial layer 2. Next, a P-type layer forming opening 3a is formed in the oxide film 3 in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. Next, by introducing and diffusing P-type impurities through the P-type layer forming opening 3a, the P-type layer 21 is formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region.

  In the MOSFET of the third embodiment, considering that the diffusion depth of the P-type impurity is increased by the subsequent heat treatment, the diffusion depth of the P-type impurity at the stage shown in FIG. 15A is higher than the target diffusion depth. Set shallower.

  At the time of manufacturing the MOSFET of the third embodiment, an oxide film 22 is then formed on the surface of the P-type layer 21 during the diffusion of P-type impurities, as shown in FIG. Next, trench formation openings 22a and 22b are formed in the oxide film 22 in the central portion (cell region) A1 of the active region, and trench formation openings 22c are formed in the oxide film 22 in the peripheral portion A2 of the active region. Opening 3b is formed in oxide film 3 in guard ring region A3. Next, the trenches 4a and 4b are formed in the central portion (cell region) A1 of the active region through the trench forming openings 22a and 22b, for example, by the reactive ion etching method, and the active region is formed through the trench forming opening 22c. The trench 4c is formed in the peripheral edge A2 by, for example, a reactive ion etching method, and the trench 4d is formed in the guard ring region A3 through, for example, the reactive ion etching method through the trench forming opening 3b.

  In the MOSFET of the third embodiment, as shown in FIG. 15B, the width dimension of the trench 4c in the peripheral portion A2 of the active region (the horizontal dimension in FIG. 15B) is the central portion ( The cell region is made larger than the width dimension of the trenches 4a and 4b in the A1 (the lateral dimension in FIG. 15B). In the MOSFET of the third embodiment, as shown in FIG. 15B, one annular trench 4d is formed in the guard ring region A3.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 15B, the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. The surface smoothing process is performed. In the surface smoothing process, for example, oxide films (not shown) are formed on the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d by a sacrificial oxidation process at a low temperature. Then, the oxide film (not shown) is peeled off. By performing the surface smoothing process, the leakage current can be reduced as compared with the case where the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d are rough. it can.

At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 15C, the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. By introducing and diffusing P-type impurities into the N − -type epitaxial layer 2 through (see FIG. 15B), the horizontal direction (left-right direction in FIG. 15C) and the vertical direction (FIG. 15C P-type layers 5a, 5b, 5c, 5d having a diffusion depth of about 0.1 to 0.2 μm and a concentration of the order of 10 ¹⁶ / cm ³ are formed in the trenches 4a, 4b, 4c, 4d side surfaces 4a1, 4b1, 4c1, 4d1 and bottom surfaces 4a2, 4b2, 4c2, 4d2 are formed. Specifically, the P-type impurity is introduced by, for example, an oblique ion implantation method, CVD deposition, low-temperature diffusion deposition, or the like. More specifically, the surface concentration of the P-type layers 5a, 5b, 5c, and 5d formed by introducing and diffusing P-type impurities is set to the order of 10 ¹⁶ / cm ³ .

At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 16A, the oxide film 6 is formed on the side surfaces 4a1, 4b1, 4c1, 4d1 and the bottom surfaces 4a2, 4b2 of the trenches 4a, 4b, 4c, 4d. , 4c2, 4d2 (see FIG. 15B). Next, openings 6a, 6b, 6c and 6d are formed in the oxide film 6 of the bottom surfaces 4a2, 4b2, 4c2 and 4d2 of the trenches 4a, 4b, 4c and 4d, and the side surfaces 4a1 and 4a1 of the trenches 4a, 4b, 4c and 4d. The oxide film 6 is left on 4b1, 4c1, and 4d1. Specifically, only the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2, and 4d2 of the trenches 4a, 4b, 4c, and 4d is removed by etching, for example, by reactive ion etching. This etching removal is performed under etching conditions with a relatively high SiO ₂ / Si etching rate.

At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 16A, polysilicon is filled in the trenches 4a, 4b, 4c, and 4d (see FIG. 15B), and By doping the polysilicon filled in the trenches 4a, 4b, 4c, and 4d with a P-type impurity, the P + type polysilicon layers 7a, 7b, 7c having a concentration of 10 ¹⁸ / cm ³ or more 7d is formed inside each trench 4a, 4b, 4c, 4d.

  Specifically, when manufacturing the MOSFET of the third embodiment, polysilicon is not selectively filled into the trenches 4a, 4b, 4c, and 4d, but is deposited over the entire surface of the semiconductor chip. Next, the polysilicon is etched back so that the polysilicon remains only in the trenches 4a, 4b, 4c, and 4d, so that the polysilicon is etched in the trenches 4a, 4b, 4c, and 4d. Filled.

  At the time of manufacturing the MOSFET of the third embodiment, as shown in FIG. 16 (A), P + type polysilicon formed in the trenches 4a, 4b, 4c, 4d (see FIG. 15 (B)). Through the openings 6a, 6b, 6c, 6d of the oxide film 6 in the layers 7a, 7b, 7c, 7d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 15B) of the trenches 4a, 4b, 4c, 4d. Heavy metal as a lifetime killer such as platinum is deposited and diffused on the P-type layers 5a, 5b, 5c, 5d and the N-type epitaxial layer 2 directly below the lever.

  At the time of manufacturing the MOSFET according to the third embodiment, as shown in FIG. 16 (B), P + type polysilicon formed in the trenches 4a, 4b, 4c, 4d (see FIG. 15 (B)). Oxide films 8a, 8b, 8c and 8d are formed on the surfaces of the layers 7a, 7b, 7c and 7d.

  Specifically, when the MOSFET of the third embodiment is manufactured, the surface of the P + type polysilicon layers 7a, 7b, 7c, 7d inside the trenches 4a, 4b, 4c, 4d (see FIG. 15B) is formed. When the oxide films 8a, 8b, 8c and 8d are formed, the oxide films 8a, 8b and 8c are formed only on the surfaces of the P + type polysilicon layers 7a, 7b, 7c and 7d in the trenches 4a, 4b, 4c and 4d. , 8d are not selectively formed, but an oxide film is formed on the entire surface of the semiconductor chip. Specifically, the oxide films 8a, 8b, 8c, and 8d are formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 16C, an N + type layer forming opening 3c is formed in the oxide film 3 on the peripheral edge A4 of the semiconductor chip, and at the same time, an N + type. The layer formation opening 22d is a portion of the central portion (cell region) A1 of the active region of the semiconductor chip excluding the portion adjacent to the peripheral portion A2 of the active region, and the trenches 4a and 4b (FIG. 15B). It is formed on the oxide film 22 except for the reference.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 16C, the N + type layer 9 is formed on the peripheral edge A4 of the semiconductor chip through the N + type layer forming opening 3c, Of the central portion (cell region) A1 of the active region of the semiconductor chip through the N + type layer forming opening 22d, the portion excluding the portion adjacent to the peripheral portion A2 of the active region, the trenches 4a and 4b (FIG. 15). An N + type layer 23 is formed in a portion except (B).

  In the MOSFET of the third embodiment, as shown in FIG. 16C, an N + type layer is formed in a portion adjacent to the peripheral edge A2 of the active region in the central portion (cell region) A1 of the active region of the semiconductor chip. 23 is not formed, and the portion (that is, the portion where the P-type layer 21 is left) is a P-type (PB) layer located below the N + type layer 23 in the central portion (cell region) A1 of the active region. 21 functions as a diode connected in reverse parallel to the MOSFET.

  Specifically, when the N + type layer 23 is formed in a portion adjacent to the peripheral portion A2 of the active region in the central portion (cell region) A1 of the active region of the semiconductor chip, a parasitic npn transistor is formed in that portion. When the holes and residual holes injected into the periphery A2 of the active region and the lower portion of the guard ring region A3 return to the source electrode metals 29a and 29c (see FIG. 19) when reverse biased, the parasitic npn transistor is There is a risk of operating. In view of this point, in the MOSFET of the third embodiment, as shown in FIG. 16C, a portion adjacent to the peripheral edge A2 of the active region in the central portion (cell region) A1 of the active region of the semiconductor chip. In addition, the N + type layer 23 is not formed, and the P type layer 21 is left.

  In the MOSFET according to the third embodiment, as shown in FIG. 18C, an N + type layer 23 adjacent to the peripheral portion A2 of the active region is formed in the central portion (cell region) A1 of the active region of the semiconductor chip. The width of the portion that is not used (that is, the portion where the P-type layer 21 is left), that is, the width of the portion that functions as a diode connected in reverse parallel to the MOSFET is about half the width of one cell unit. Is set. In the modification of the MOSFET of the third embodiment, instead, the width of the portion that functions as a diode connected in reverse parallel to the MOSFET is set to a width corresponding to one cell unit, or about the width of one cell unit width. Set the width to 1.5 times, set the width to about twice the width of one cell unit, set the width to about 2.5 times the width of one cell unit, It is also possible to set an arbitrary width other than.

  At the time of manufacturing the MOSFET of the third embodiment, an oxide film 24 is then formed on the surfaces of the N + type layers 23 and 9 as shown in FIG. Specifically, the oxide film 24 is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 17A, trench formation openings 24a and 24b are formed in the oxide film 24 in the central portion (cell region) A1 of the active region. Next, trenches 25a and 25b are formed in the central portion (cell region) A1 of the active region via the trench formation openings 24a and 24b, for example, by reactive ion etching.

  Next, when the MOSFET of the third embodiment is manufactured, the surface smoothing process is performed on the side surfaces and the bottom surface of the trenches 25a and 25b. In the surface smoothing process, an oxide film (not shown) is formed on the side and bottom surfaces of the trenches 25a and 25b by, for example, a sacrificial oxidation process at a low temperature, and then the oxide film (not shown) is peeled off. By performing the surface smoothing process, the leakage current can be reduced as compared with the case where the side and bottom surfaces of the trenches 25a and 25b are rough, and a high-quality gate oxide film can be obtained. Specifically, by performing the surface smoothing process on the side surfaces of the trenches 25a and 25b serving as the channel portions of the MOSFET, the electrons of the majority carriers passing through the channel are more than when the surface smoothing process is not performed. Channel mobility (μch) can be improved.

  At the time of manufacturing the MOSFET of the third embodiment, as shown in FIG. 17B, a thermal oxide film 26 that becomes the gate oxide film of the MOSFET is then formed on the side and bottom surfaces of the trenches 25a and 25b. Specifically, when the MOSFET of the third embodiment is manufactured, the thermal oxide film 26 that becomes the gate oxide film of the MOSFET is formed under an extremely clean atmospheric gas.

  At the time of manufacturing the MOSFET according to the third embodiment, as shown in FIG. 17B, polysilicon is then trenched in the trenches 25a and 25b in a portion corresponding to the cross section along the line AA in FIG. The polysilicon filled in the active region of the semiconductor chip and deposited on the peripheral portion A2 of the active region of the semiconductor chip, and the polysilicon filled in the trenches 25a and 25b and the polycrystal deposited on the peripheral portion A2 of the active region of the semiconductor chip. By doping the silicon with N-type impurities, N + -type polysilicon layers 27a, 27b, and 27c are formed in the trenches 25a and 25b and in the peripheral portion A2 of the active region of the semiconductor chip. The N + type polysilicon layer 27c formed at the peripheral edge A2 of the active region of the semiconductor chip is used later for routing the gate wiring.

  On the other hand, in the portion corresponding to the cross section along the line BB in FIG. 19A, polysilicon is filled in the trenches 25a and 25b, and the periphery A2 of the active region of the semiconductor chip is formed. By partially depositing and doping the polysilicon filled in the trenches 25a and 25b and the polysilicon deposited on a part of the peripheral portion A2 of the active region of the semiconductor chip with N-type impurities N + type polysilicon layers 27a, 27b, 27c ′ (see FIG. 18A) are formed in the trenches 25a, 25b and part of the peripheral edge A2 of the active region of the semiconductor chip. The N + type polysilicon layer 27c '(see FIG. 18A) formed on a part of the peripheral edge A2 of the active region of the semiconductor chip is used later for routing the gate wiring.

  Specifically, during the manufacture of the MOSFET of the third embodiment, polysilicon is selectively filled into the trenches 25a and 25b, and is selectively applied to a part of the peripheral edge A2 of the active region of the semiconductor chip. Rather than being deposited, polysilicon is deposited over the entire surface of the semiconductor chip, and then excess polysilicon is left in the trenches 25a, 25b and in part of the periphery A2 of the active region of the semiconductor chip. The polysilicon is etched back.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 17C, an oxide film 28 is formed on the entire surface of the semiconductor chip. Specifically, the oxide film 28 is formed by, for example, thermal oxidation, CVD oxidation, or the like.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 18A, in the portion corresponding to the cross section along the line BB in FIG. Region) A1 except for trenches 25a and 25b (see FIG. 17A) in oxide region A1, a portion of oxide film on P + type polysilicon layer 7d in guard ring region A3, and the peripheral portion of the semiconductor chip Electrode metal forming openings 28a, 28b, 28d, and 28e are formed in a portion of the oxide film on the N + type layer 9 of A4.

  On the other hand, at this time, in the portion corresponding to the cross section along the line AA in FIG. 19A, as shown in FIG. 18B, the trench 25a in the central portion (cell region) A1 of the active region is formed. 25b (see FIG. 17A), a portion of the oxide film, a part of the oxide film on the N + type polysilicon layer 27c in the peripheral portion A2 of the active region, and a part of the guard ring region A3 on the P + type polysilicon layer 7d Electrode metal forming openings 28a, 28c, 28d, and 28e are formed in part of the oxide film and part of the oxide film on the N + type layer 9 at the peripheral edge A4 of the semiconductor chip.

  At the time of manufacturing the MOSFET of the third embodiment, an electrode metal is then formed on the entire surface of the semiconductor chip by, for example, sputtering or vapor deposition.

  At the time of manufacturing the MOSFET of the third embodiment, as shown in FIG. 18C, the electrode metal on the entire surface of the semiconductor chip is then replaced with the source electrode metal 29a in the central portion (cell region) A1 of the active region, The gate wiring routing electrode metal 29b in the peripheral portion A2 of the active region, the source electrode metal 29c located on the peripheral portion (right side in FIG. 18C) side of the gate wiring routing electrode metal 29b, the guard ring electrode metal 29d, The semiconductor chip is electrically separated and patterned into the EQR electrode metal 29e at the peripheral edge A4 of the semiconductor chip.

  As a result, in the MOSFET of the third embodiment, as shown in FIGS. 18C and 13, the N + type polysilicon layer inside the trenches 25a and 25b (see FIG. 17A) functioning as gate electrodes. 27a, 27b and the gate wiring routing electrode metal 29b are electrically connected.

  At the time of manufacturing the MOSFET of the third embodiment, next, as shown in FIG. 18C, the source electrode metal 29a positioned above the N + type polysilicon layer 27c in the central portion (cell region) A1 of the active region The P + type polysilicon layer 7b inside the trench 4b (see FIG. 15B) located below the N + type polysilicon layer 27c in the central portion (cell region) A1 of the active region is electrically connected. Is done. Further, the source electrode metal 29c located above the N + type polysilicon layer 27c in the peripheral part A2 of the active region and the trench 4c located below the N + type polysilicon layer 27c in the peripheral part A2 of the active region (FIG. 15). The P + type polysilicon layer 7c inside (see (B)) is electrically connected.

  At the time of manufacturing the MOSFET of the third embodiment, the final protective film 14 is then formed on the entire surface of the semiconductor chip as shown in FIG. Further, a contact opening 14 a for connecting to the source electrode metal 29 a is formed in the final protective film 14. A drain electrode metal 30 is formed on the back surface of the semiconductor chip.

  Further, at the time of manufacturing the MOSFET of the third embodiment, as shown in FIG. 14, the gate electrode metal 31 electrically connected to the gate wiring routing electrode metal 29b is formed on the surface of the semiconductor chip. Furthermore, a gate pad 32 electrically connected to the gate electrode metal 31 is formed on the surface of the semiconductor chip. A source pad 33 electrically connected to the source electrode metals 29a and 29c is formed on the surface of the semiconductor chip.

  As a result, in the MOSFET of the third embodiment, as shown in FIG. 19, the N + type polysilicon layers 27a ′, 27a, and 27b function as gate electrodes. Further, the P-type layer 21 adjacent to the gate oxide film 26 on the side surfaces of the N + type polysilicon layers 27a ', 27a, and 27b functions as a vertical MOSFET channel.

  Specifically, during the manufacture of the MOSFET of the third embodiment, a sintering process for ensuring ohmic contact is appropriately performed in an inert gas of about 400 ° C., for example.

  That is, in the MOSFET of the third embodiment, as shown in FIG. 19B, the guard ring region A3 is disposed outside the peripheral edge A2 of the active region (on the right side of FIG. 19B). Specifically, in the MOSFET according to the third embodiment, the trench 4c (see FIG. 15B) in the peripheral portion A2 of the active region of the semiconductor chip and the guard ring region outside the peripheral portion A2 of the active region of the semiconductor chip. A breakdown voltage maintaining structure is formed by the trench 4d of A3 (see FIG. 15B), the N− type epitaxial layer 2 outside the guard ring region A3, and the N + type layer 9 of the peripheral portion A4 of the semiconductor chip. .

  Furthermore, since the MOSFET according to the third embodiment employs a trench structure, according to the MOSFET according to the third embodiment, the lateral dimension of the semiconductor chip (FIG. 19) is greater than when the trench structure is not employed. (B) horizontal dimension) can be reduced.

  In the MOSFET of the third embodiment, as shown in FIG. 19B, a guard ring electrode metal 29d is formed on the P + type polysilicon layer 7d in the guard ring region A3 of the semiconductor chip. For this reason, according to the MOSFET of the third embodiment, more than the case where the guard ring electrode metal 29d is not formed on the P + type polysilicon layer 7d in the guard ring region A3 of the semiconductor chip, the sky is lost at the time of reverse bias. The layer D1 (see FIG. 7) can be extended to the peripheral edge side of the semiconductor chip.

Further, in the MOSFET of the third embodiment, as shown in FIG. 19B, the P + type polysilicon layers 7a ′, 7a, 7a, 4b, 4c, 4d (see FIG. 15B) inside the trenches 4a, 4b, 4c, 4d, The concentration of 7b, 7c, 7d is set to 10 ¹⁸ / cm ³ or more. Therefore, according to the MOSFET of the third embodiment, it is possible to make ohmic contact between the P + type polysilicon layers 7a ′ and 7a in the central portion (cell region) A1 of the active region of the semiconductor chip and the source electrode metal 29a. As a result, at the time of forward bias, the potential of the source electrode metal 29a is made faster than the P-type layers 5a ′ and 5a formed along the side surfaces of the trench 4a, and the P + -type polysilicon layers 7a ′ and 7a inside the trench 4a. Can tell.

  In other words, in the MOSFET of the third embodiment, as shown in FIG. 19B, a high concentration P + type polysilicon layer is formed inside the trenches 4a, 4b, 4c, 4d (see FIG. 15B). 7a ', 7a, 7b, 7c, 7d are formed. Therefore, according to the MOSFET of the third embodiment, compared to the case where the high-concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d are not formed in the trenches 4a, 4b, 4c, 4d. When the forward bias is applied, the empty layer D2 (see FIG. 6) below the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d is connected to the drain electrode 30 side (the lower side of FIG. 19B). As a result, the space 2 ′ (see FIG. 6) between two adjacent trenches can be easily pinched off.

  Specifically, in the MOSFET of the third embodiment, the high concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d are formed inside the trenches 4a, 4b, 4c, 4d. In the MOSFET of the third embodiment, the sky layer extending to the N− type epitaxial layer 2 below the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d quickly reaches the N + type substrate 1 side. . As a result, the electric field strength is maximum in the lower portions of the trenches 4a, 4b, 4c, and 4d as compared with other portions. That is, in the MOSFET of the third embodiment, the electric field strength in the lower part of the trenches 25a and 25b (see FIG. 17B) is relatively low, and the gate oxide film 26 on the side surfaces of the trenches 25a and 25b is applied. Electric field strength can be kept low. Therefore, according to the MOSFET of the third embodiment, the gate oxidation on the side surfaces of the trenches 25a and 25b is higher than the case where the electric field strength applied to the gate oxide film 26 on the side surfaces of the trenches 25a and 25b is higher. The membrane 26 can be safely protected.

  Specifically, according to the MOSFET of the third embodiment, the electric field strength below the trenches 25a and 25b is made lower than the MOSFET in which the trenches 4a and 4b are not provided and only the trenches 25a and 25b are provided. be able to.

  The diffusion rate of heavy metal in the polysilicon layer is faster than the diffusion rate of heavy metal in the N − type epitaxial layer 2, and the diffusion rate of heavy metal in the oxide film 6 is higher than the diffusion rate of heavy metal in the N − type epitaxial layer 2. In view of the slow point, in the MOSFET of the third embodiment, as shown in FIG. 19B, P + type polysilicon formed in the trenches 4a, 4b, 4c, and 4d (see FIG. 15B). Openings 6a, 6b, 6c, 6d in the oxide film 6 in the layers 7a ′, 7a, 7b, 7c, 7d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 15B) of the trenches 4a, 4b, 4c, 4d Heavy metal is diffused into the P-type layers 5a′5a, 5b, 5c, 5d and the N − -type epitaxial layer 2 via (see FIG. 16A). Therefore, according to the MOSFET of the third embodiment, the P-type layer near the openings 6a, 6b, 6c, 6d of the oxide film 6 in the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. Heavy metals (Bb, Bc (see FIG. 6)) can be locally diffused in 5a′5a, 5b, 5c, 5d and the N− type epitaxial layer 2. That is, according to the MOSFET of the third embodiment, the P-type layers 5a′5a, 5b, 5c, 5d on the side of the oxide film 6 of the side surfaces 4a1, 4b1, 4c1, 4d1 of the trenches 4a, 4b, 4c, 4d. In addition, the carrier lifetime of the N − type epitaxial layer 2 can be maintained long.

  Further, in the MOSFET of the third embodiment, as shown in FIG. 19B, a high-concentration P + type polysilicon layer 7a ′ is placed inside the trenches 4a, 4b, 4c, 4d (see FIG. 15B). , 7a, 7b, 7c, 7d are formed. That is, in the MOSFET of the third embodiment, the majority carriers are formed in the trenches 4a, 4b, 4c, and 4d in which the high-concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d are formed. Holes are not sufficiently activated, and hole mobility is not sufficiently high. Therefore, according to the MOSFET of the third embodiment, the inside of the trenches 4a, 4b, 4c, 4d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d (see FIG. 15B) The oxide film 6 is implanted into the N − type epitaxial layer 2 through the openings 6a, 6b, 6c, 6d (see FIG. 16A) and the P type layers 5a′5a, 5b, 5c, 5d directly below the openings 6a, 6b, 6c, 6d. The amount of holes injected as carriers can be limited.

  Further, in the MOSFET of the third embodiment, as shown in FIG. 19B, the oxide film 6 on the bottom surfaces 4a2, 4b2, 4c2, 4d2 (see FIG. 15B) of the trenches 4a, 4b, 4c, 4d. Heavy metal as a lifetime killer is introduced into the P-type layers 5a′5a, 5b, 5c, and 5d directly below the openings 6a, 6b, 6c, and 6d (see FIG. 16A). That is, in the MOSFET of the third embodiment, the P-type layer 5a′5a just below the openings 6a, 6b, 6c, 6d of the oxide film 6 in the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. , 5b, 5c, 5d, the lifetime of holes as carriers is shortened. Therefore, according to the MOSFET of the third embodiment, the openings 6a, 6b in the oxide film 6 in the trenches 4a, 4b, 4c, 4d and the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d. , 6c, 6d and the P-type layers 5a′5a, 5b, 5c, 5d directly below them, the amount of holes injected as carriers injected into the N− type epitaxial layer 2 can be limited.

  In the MOSFET of the third embodiment, as shown in FIG. 19B, oxide films are not formed on the side surfaces 4a1, 4b1, 4c1, 4d1 (see FIG. 15B) of the trenches 4a, 4b, 4c, 4d. 6 is left. That is, in the MOSFET of the third embodiment, the oxide film 6 on the inside of the trenches 4a, 4b, 4c, 4d, the side surfaces 4a1, 4b1, 4c1, 4d1 of the trenches 4a, 4b, 4c, 4d, and the side Holes as carriers are not injected into the N − -type epitaxial layer 2 through the P-type layers 5a′5a, 5b, 5c, and 5d.

That is, according to the MOSFET of the third embodiment, the concentration of the P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d in the trenches 4a, 4b, 4c, and 4d is less than 10 ¹⁸ / cm ³ order. Or when no heavy metal as a lifetime killer is introduced from the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d, or the side surfaces 4a1, 4b, 4c, 4d of the trenches 4a, 4b, 4c, 4d. The amount of holes injected as carriers into the N − -type epitaxial layer 2 can be limited as compared with the case where the oxide film 6 is not formed on 4b1, 4c1, and 4d1.

  Furthermore, in the MOSFET according to the third embodiment, as shown in FIG. 19B, a high-concentration P + type polysilicon layer 7a ′ is formed inside the trenches 4a, 4b, 4c, and 4d (see FIG. 15B). , 7a, 7b, 7c, and 7d are formed, and holes serving as majority carriers in the trenches 4a, 4b, 4c, and 4d are not sufficiently activated. Further, the heavy metal diffused in the P + type polysilicon layers 7a ′, 7a, 7b, 7c, 7d inside the trenches 4a, 4b, 4c, 4d is the bottom surfaces 4a2, 4b2, 4c2 of the trenches 4a, 4b, 4c, 4d. , 4d2 (see FIG. 15B) through the openings 6a, 6b, 6c, 6d (see FIG. 16A) of the oxide film 6, the P-type layers 5a ′, 5a, 5b, 5c immediately below the openings 6a, 6b, 6c, 5d and locally distributed in the N− type epitaxial layer 2.

  Therefore, in the MOSFET of the third embodiment, as shown in FIG. 19B, immediately below the portion between two adjacent trenches 4a, 4b, 4c (see FIG. 15B) at the time of reverse bias. The residual holes (holes) (see FIG. 6) existing between the lower end of the empty layer D1 (see FIG. 6) and the N + type substrate 1 are switched from the reverse bias to the forward bias. Openings 6a, 6b, 6a, 6b in the bottom surface 4a2, 4b2, 4c2 (see FIG. 15B) of the trenches 4a, 4b, 4c in which heavy metals (Bb, Bc (see FIG. 6)) are locally distributed. 6c (see FIG. 16A), the N − type epitaxial layer 2 and the P type layers 5a′5a, 5b, and 5c, and the trenches 4a that are close to the potentials of the source electrode metals 29a and 29c, High concentration P + type inside 4b, 4c Rishirikon layer 7a ', 7a, 7b, through 7c, the source electrode metal 29a, are quickly returned to 29c.

That is, according to the MOSFET of the third embodiment, as shown in FIG. 19B, directly below the bottom surfaces 4a2, 4b2, 4c2, 4d2 of the trenches 4a, 4b, 4c, 4d (see FIG. 15B). In the case where heavy metal is not locally distributed in the P-type layers 5a′5a, 5b, 5c, 5d and the N− type epitaxial layer 2, or in the order of 10 ¹⁸ / cm ^{3 in} the trenches 4a, 4b, 4c, 4d The reverse recovery time (trr) of the reverse-parallel connected diode built in the MOSFET can be made shorter than when the high-concentration P + type polysilicon layers 7a ′, 7a, 7b, 7c, and 7d are not formed. And soft recovery can be achieved.

  Furthermore, in the MOSFET of the third embodiment, as shown in FIG. 19B, the N + type layer 23 (see FIG. 16C) is formed in the active region in the central portion (cell region) A1 of the active region. It is not formed in a portion adjacent to the peripheral portion A2 (that is, a portion between the P + type polysilicon layer 7b and the N + type polysilicon layer 27b in FIG. 19B), and the P type layer 21 is not formed in that portion. Is left behind. Therefore, according to the MOSFET of the third embodiment, the portion where the P-type layer 21 is left (that is, between the P + type polysilicon layer 7b and the N + type polysilicon layer 27b in FIG. 19B). Can act as a diode connected in reverse parallel to the MOSFET.

  In the MOSFET of the third embodiment, as shown in FIG. 19B, two trenches 4b and 4c (FIG. 15B) are formed in the central portion (cell region) A1 of the active region and the peripheral portion A2 of the active region. )) Are arranged adjacent to each other, and the P + type polysilicon layers 7b and 7c are formed inside the trenches 4b and 4c. Therefore, according to the MOSFET of the third embodiment, the N− type epitaxial layer 2 is formed. The amount of holes injected as carriers can be limited, and the influence of the parasitic diode generated in this portion can be reduced.

  In the fourth embodiment, the above-described first to third embodiments and their modifications can be combined as appropriate.

It is sectional drawing which showed the manufacturing process of JBS of 1st Embodiment. It is sectional drawing which showed the manufacturing process of JBS of 1st Embodiment. It is sectional drawing which showed the manufacturing process of JBS of 1st Embodiment. It is the figure which showed JBS of 1st Embodiment. It is the top view seen through a part of right half of JBS of a 1st embodiment. A diffusion region Bb of heavy metal such as platinum diffused in the P-type layer 5b and the N− type epitaxial layer 2 through the opening 6b in the oxide film 6 and the P-type layer 5c through the opening 6c in the oxide film 6 4 is a view showing a diffusion region Bc of a heavy metal such as platinum diffused in the N − type epitaxial layer 2. It is the figure which showed the vacant layer D1 etc. when a reverse bias is applied to JBS of 1st Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 2nd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 2nd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 2nd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 2nd Embodiment. It is the figure which showed MOSFET of 2nd Embodiment. It is the top view seen through a part of right half of MOSFET of 2nd Embodiment. It is the top view which showed the right half of the outermost surface of MOSFET of 2nd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 3rd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 3rd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 3rd Embodiment. It is sectional drawing which showed the manufacturing process of MOSFET of 3rd Embodiment. It is the figure which showed MOSFET of 3rd Embodiment. It is a figure for demonstrating the empty layer of MOSFET. It is the figure which showed the modification of MOSFET of 2nd Embodiment.

Explanation of symbols

A1 Central part of active area (cell area)
A2 Edge of active region A3 Guard ring region A4 Edge of semiconductor chip 1 N + type substrate 2 N− type epitaxial layer 3 Oxide films 3a, 3b, 3c, 3d, 3e, 3f, 3g Openings 3h, 3i, 3j Openings 4a , 4b, 4c, 4d, 4e, 4f Trench 4a1, 4b1, 4c1, 4d1, 4e1, 4f1 Side surface 4a2, 4b2, 4c2, 4d2, 4e2, 4f2 Bottom surface 5a, 5b, 5c, 5d, 5e, 5f P-type layer 6 Oxides 6a, 6b, 6c, 6d, 6e, 6f Openings 7a, 7b, 7c, 7d, 7e, 7f P + type polysilicon layers 8a, 8b, 8c, 8d, 8e, 8f Oxide film 9 N + type layer 10 Barrier metal 11 Anode electrode metal 12a, 12b, 12c Field plate 13 EQR electrode metal 14 Final protective film 14a Opening 15 Cathode electrode metal

Claims (3)

In a JBS configured by a semiconductor chip including an active region in which a Schottky junction and a PN junction coexist, and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a plurality of trench formation openings in the first oxide film of the active region and the guard ring region;
A plurality of trenches are formed in the active region and the guard ring region through a plurality of trench formation openings,
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm and the concentration Forming a P-type layer of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of trenches,
Forming a second oxide film on the side and bottom surfaces of the plurality of trenches;
Forming openings in the second oxide film on the bottom surfaces of the plurality of trenches;
P + type polysilicon having a concentration of 10 ¹⁸ / cm ³ or more is formed by filling polysilicon into the plurality of trenches and doping the polysilicon filled in the plurality of trenches with P type impurities. Forming a layer inside a plurality of trenches;
Depositing and diffusing heavy metal into the P-type layer and the N-type epitaxial layer through the P + type polysilicon layer formed inside the plurality of trenches and the opening of the second oxide film on the bottom surface of the plurality of trenches;
Forming a third oxide film on the surface of the P + type polysilicon layer formed in the plurality of trenches;
Forming an opening for N + type layer formation in the oxide film at the periphery of the semiconductor chip;
Forming an N + type layer on the periphery of the semiconductor chip through the N + type layer forming opening;
An opening for forming a barrier metal is formed in the oxide film in the active region of the semiconductor chip,
An opening for the field plate is formed in the oxide film on the P + type polysilicon layer in the guard ring region of the semiconductor chip,
A barrier metal is formed in the active region of the semiconductor chip through the opening for forming the barrier metal,
An anode electrode metal is formed on the barrier metal,
A field plate is formed on the P + type polysilicon layer in the guard ring region of the semiconductor chip through the field plate opening,
An EQR electrode metal is formed on the N + type layer at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
A contact opening for connecting to the anode electrode metal is formed in the final protective film,
A JBS characterized in that a cathode electrode metal is formed on the back surface of a semiconductor chip. In a MOSFET constituted by a semiconductor chip comprising an active region and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a P-type layer forming opening in the first oxide film of the active region;
A P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening,
Forming a second oxide film on the surface of the P-type layer during the diffusion of the P-type impurities;
Forming a plurality of first trench formation openings in the oxide film of the active region and the guard ring region;
Forming a plurality of first trenches in the active region and the guard ring region through a plurality of first trench formation openings;
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm. Forming a P-type layer with a concentration of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of first trenches,
Forming a third oxide film on the side and bottom surfaces of the plurality of first trenches;
Forming an opening in the third oxide film on the bottom surface of the plurality of first trenches;
By filling polysilicon into the plurality of first trenches and doping the polysilicon filled in the plurality of first trenches with a P-type impurity, the concentration becomes 10 ¹⁸ / cm ³ or more. Forming a P + type polysilicon layer inside the first trenches;
Heavy metal is deposited on the P + type polysilicon layer formed in the plurality of first trenches and the P-type layer and the N− type epitaxial layer immediately below the third oxide film through the openings of the third oxide films on the bottom surfaces of the plurality of first trenches.・ Diffusion,
Forming a fourth oxide film on the surface of the P + type polysilicon layer formed in the plurality of first trenches;
N + type layer forming openings are formed in the oxide film at the peripheral portion of the semiconductor chip and the oxide film in the central portion of the active region of the semiconductor chip excluding the first trench,
Forming an N + type layer on the periphery of the semiconductor chip through the N + type layer forming opening and a portion excluding the first trench in the central part of the active region of the semiconductor chip;
Forming a fifth oxide film on the surface of the N + type layer;
Forming a plurality of second trench formation openings in the oxide film in the center of the active region;
Forming a plurality of second trenches in the central portion of the active region through the plurality of second trench formation openings;
Forming a thermal oxide film to be a gate oxide film of the MOSFET on the side and bottom surfaces of the plurality of second trenches;
The polysilicon is filled in the plurality of second trenches and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the polysilicon and the semiconductor chip filled in the plurality of second trenches are activated. By doping the polysilicon deposited on a part of the peripheral portion of the region with an N-type impurity, the N + -type polysilicon layer is formed inside the second trenches and on the peripheral portion of the active region of the semiconductor chip. Formed in the part,
Forming a sixth oxide film over the entire surface of the semiconductor chip;
Of the central portion of the active region, a portion of the oxide film excluding the second trench, a portion of the oxide film on the N + type polysilicon layer at the peripheral portion of the active region, and a portion of the guard ring region on the P + type polysilicon layer An opening for forming an electrode metal is formed in the oxide film and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip,
Electrode metal is formed on the entire surface of the semiconductor chip,
The electrode metal on the entire surface of the semiconductor chip is divided into a source electrode metal at the center of the active region, a gate wiring routing electrode metal at the peripheral portion of the active region, and a source electrode metal positioned on the peripheral side of the gate wiring routing electrode metal. And electrically separating the guard ring electrode metal and the EQR electrode metal at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
Electrically connecting the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal;
A source electrode metal located above the N + type polysilicon layer at the periphery of the active region, and a P + type polysilicon layer inside the first trench located below the N + type polysilicon layer at the periphery of the active region; Electrically connect
A MOSFET characterized in that a drain electrode metal is formed on the back surface of a semiconductor chip. In a MOSFET constituted by a semiconductor chip comprising an active region and a guard ring region disposed outside the active region,
Forming an N− type epitaxial layer on an N + type substrate;
Forming a first oxide film over the entire surface of the N-type epitaxial layer;
Forming a P-type layer forming opening in the first oxide film of the active region;
A P-type layer is formed in the active region by introducing and diffusing P-type impurities through the P-type layer forming opening,
Forming a second oxide film on the surface of the P-type layer during the diffusion of the P-type impurities;
Forming a plurality of first trench formation openings in the oxide film of the active region and the guard ring region;
Forming a plurality of first trenches in the active region and the guard ring region through a plurality of first trench formation openings;
By introducing and diffusing P-type impurities into the N − -type epitaxial layer through the side surfaces and bottom surfaces of the plurality of first trenches, the diffusion depth in the horizontal and vertical directions is about 0.1 to 0.2 μm. Forming a P-type layer with a concentration of the order of 10 ¹⁶ / cm ³ along the side and bottom surfaces of the plurality of first trenches,
Forming a third oxide film on the side and bottom surfaces of the plurality of first trenches;
Forming an opening in the third oxide film on the bottom surface of the plurality of first trenches;
By filling polysilicon into the plurality of first trenches and doping the polysilicon filled in the plurality of first trenches with a P-type impurity, the concentration becomes 10 ¹⁸ / cm ³ or more. Forming a P + type polysilicon layer inside the first trenches;
Heavy metal is deposited on the P + type polysilicon layer formed in the plurality of first trenches and the P-type layer and the N− type epitaxial layer immediately below the third oxide film through the openings of the third oxide films on the bottom surfaces of the plurality of first trenches.・ Diffusion,
Forming a fourth oxide film on the surface of the P + type polysilicon layer formed in the plurality of first trenches;
The N + type layer forming opening is a portion excluding the oxide film at the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip, excluding the portion adjacent to the peripheral portion of the active region, and excluding the first trench Formed with the oxide film,
Of the peripheral portion of the semiconductor chip and the central portion of the active region of the semiconductor chip through the N + type layer forming opening, the portion excluding the portion adjacent to the peripheral portion of the active region, excluding the first trench And an N + type layer is formed on
Forming a fifth oxide film on the surface of the N + type layer;
Forming a plurality of second trench formation openings in the oxide film in the center of the active region;
Forming a plurality of second trenches in the central portion of the active region through the plurality of second trench formation openings;
Forming a thermal oxide film to be a gate oxide film of the MOSFET on the side and bottom surfaces of the plurality of second trenches;
The polysilicon is filled in the plurality of second trenches and is deposited on a part of the peripheral portion of the active region of the semiconductor chip, and the polysilicon and the semiconductor chip filled in the plurality of second trenches are activated. By doping the polysilicon deposited on a part of the peripheral portion of the region with an N-type impurity, the N + -type polysilicon layer is formed inside the second trenches and on the peripheral portion of the active region of the semiconductor chip. Formed in the part,
Forming a sixth oxide film over the entire surface of the semiconductor chip;
Of the central portion of the active region, a portion of the oxide film excluding the second trench, a portion of the oxide film on the N + type polysilicon layer at the peripheral portion of the active region, and a portion of the guard ring region on the P + type polysilicon layer An opening for forming an electrode metal is formed in the oxide film and a part of the oxide film on the N + type layer at the periphery of the semiconductor chip,
Electrode metal is formed on the entire surface of the semiconductor chip,
The electrode metal on the entire surface of the semiconductor chip is divided into a source electrode metal at the center of the active region, a gate wiring routing electrode metal at the peripheral portion of the active region, and a source electrode metal positioned on the peripheral side of the gate wiring routing electrode metal. And electrically separating the guard ring electrode metal and the EQR electrode metal at the periphery of the semiconductor chip,
A final protective film is formed on the entire surface of the semiconductor chip,
Electrically connecting the N + type polysilicon layer inside the second trench functioning as the gate electrode and the gate wiring routing electrode metal;
A source electrode metal located above the N + type polysilicon layer at the periphery of the active region, and a P + type polysilicon layer inside the first trench located below the N + type polysilicon layer at the periphery of the active region; Electrically connect
A MOSFET characterized in that a drain electrode metal is formed on the back surface of a semiconductor chip.

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