JP2009124057A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Semiconductor apparatus and method of manufacturing the same Download PDF

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JP2009124057A
JP2009124057A JP2007298747A JP2007298747A JP2009124057A JP 2009124057 A JP2009124057 A JP 2009124057A JP 2007298747 A JP2007298747 A JP 2007298747A JP 2007298747 A JP2007298747 A JP 2007298747A JP 2009124057 A JP2009124057 A JP 2009124057A
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wiring
pad
region
surface layer
semiconductor device
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Toshihiko Sakashita
俊彦 阪下
Masao Takahashi
昌男 高橋
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus capable of preventing occurrence of cracks in an insulating film between layers under a pad, without reducing a wiring density of the next wiring layer below a surface layer on which a pad for external connection is formed. <P>SOLUTION: A thickness of a wiring 3a, passing under a region of a pad 1 among wirings formed on the next layer below a surface layer, is set smaller than that of a wiring 3b which is arranged deviating from under the region of the pad 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特に多層配線構造の半導体装置の、表層に形成された外部接続用のパッド下の配線構造に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a wiring structure under a pad for external connection formed on a surface layer of a semiconductor device having a multilayer wiring structure.

従来の多層配線構造の半導体装置では、表層に形成された外部接続用のパッドにプローブ針を接触させるプローブ検査時や、表層に形成された外部接続用のパッドにワイヤを接続するワイヤボンド時にパッドに印加される半導体装置の厚さ方向の応力によってパッド下の層間絶縁膜にクラックが発生するのを防止するため、図５に示すように、表層より一層下の配線層の配線１２の幅をパッド１１の径よりも広くして、その配線１２上にパッド１１を配置し、パッド１１の領域下には、表層より一層下の配線層の配線１２の端部や、表層より一層下の配線層の配線１２と他層の配線とを接続するための接続孔を配置しないようにしている。
特開平６−３０２６０５号公報 In a conventional semiconductor device having a multilayer wiring structure, a pad is used at the time of probe inspection in which a probe needle is brought into contact with an external connection pad formed on the surface layer, or at the time of wire bonding for connecting a wire to the external connection pad formed on the surface layer In order to prevent the generation of cracks in the interlayer insulating film under the pad due to the stress in the thickness direction of the semiconductor device applied to, the width of the wiring 12 in the wiring layer below the surface layer is reduced as shown in FIG. The pad 11 is arranged on the wiring 12 so as to be wider than the diameter of the pad 11. Below the area of the pad 11, the end of the wiring 12 in the wiring layer lower than the surface layer and the wiring lower than the surface layer are arranged. A connection hole for connecting the wiring 12 of the layer and the wiring of the other layer is not arranged.
JP-A-6-302605

近年、半導体装置に集積される素子の密度が増大し、外部接続用のパッドを形成する表層よりも下層の配線層の配線密度を上げる必要性が増してきた。しかし、従来の半導体装置では、表層より一層下の配線層の配線の幅をパッドの径よりも広くすることによって、半導体装置の厚さ方向の応力がパッドに印加されたときにパッド下の層間絶縁膜にクラックが発生するのを防止しているため、配線密度を上げることができないという問題点を有していた。   In recent years, the density of elements integrated in a semiconductor device has increased, and the necessity of increasing the wiring density of a lower wiring layer than the surface layer on which external connection pads are formed has increased. However, in the conventional semiconductor device, by making the wiring width of the wiring layer below the surface layer wider than the diameter of the pad, when stress in the thickness direction of the semiconductor device is applied to the pad, Since the generation of cracks in the insulating film is prevented, the wiring density cannot be increased.

本発明は、上記問題点に鑑み、外部接続用のパッドが形成される表層より一層下の配線層の配線密度を下げることなく、パッド下の層間絶縁膜のクラックを防止できる半導体装置およびその製造方法を提供することを目的とする。   In view of the above problems, the present invention provides a semiconductor device capable of preventing cracks in an interlayer insulating film below a pad without lowering the wiring density of a wiring layer below a surface layer on which a pad for external connection is formed, and its manufacture It aims to provide a method.

本発明の請求項１記載の半導体装置は、表層に形成された外部接続用のパッドと、前記表層より一層下の層に形成された配線と、前記表層およびその一層下の層に形成された層間絶縁膜と、半導体基板とを少なくとも備えた半導体装置であって、前記表層より一層下の層に形成された配線のうち、少なくとも一部が前記パッドの領域下に配置される配線は、その厚さが、前記パッドの領域下から外れて配置される配線の厚さよりも薄いことを特徴とする。   The semiconductor device according to claim 1 of the present invention is formed in a pad for external connection formed in a surface layer, a wiring formed in a layer lower than the surface layer, and the surface layer and a layer below it. A semiconductor device comprising at least an interlayer insulating film and a semiconductor substrate, wherein at least a part of wirings formed in a layer below the surface layer is disposed below the pad region. The thickness is smaller than the thickness of the wiring arranged out of the area of the pad.

また、本発明の請求項２記載の半導体装置は、表層に形成された外部接続用のパッドと、前記表層より一層下の層に形成された配線と、前記表層およびその一層下の層に形成された層間絶縁膜と、半導体基板とを少なくとも備えた半導体装置であって、前記表層より一層下の層に形成された配線のうち、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線は、その厚さが、前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の厚さよりも薄いことを特徴とする。   According to a second aspect of the present invention, there is provided a semiconductor device having an external connection pad formed in a surface layer, wiring formed in a layer lower than the surface layer, and formed in the surface layer and a layer below the surface layer. A semiconductor device comprising at least an interlayer insulating film and a semiconductor substrate, wherein at least a part of wiring formed in a layer lower than the surface layer is under a probe region or a wire bond region of the pad. The thickness of the wirings arranged in (1) is smaller than the thickness of the wirings arranged outside the probe region or the wire bond region.

また、本発明の請求項３記載の半導体装置は、請求項１記載の半導体装置であって、前記層間絶縁膜のヤング率は、少なくとも一部が前記パッドの領域下に配置される配線のヤング率よりも小さいことを特徴とする。   According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the Young's modulus of the interlayer insulating film is a Young's modulus of wiring that is at least partially disposed under the pad region. It is characterized by being smaller than the rate.

また、本発明の請求項４記載の半導体装置は、請求項２記載の半導体装置であって、前記層間絶縁膜のヤング率は、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線のヤング率よりも小さいことを特徴とする。   The semiconductor device according to claim 4 of the present invention is the semiconductor device according to claim 2, wherein the Young's modulus of the interlayer insulating film is at least partially below the probe region or the wire bond region of the pad. It is characterized by being smaller than the Young's modulus of the arranged wiring.

また、本発明の請求項５記載の半導体装置の製造方法は、外部接続用のパッドが形成される表層より一層下の層に配線を形成するに際し、第１のマスクを用いて、少なくとも一部が前記パッドの領域下に配置される配線、および前記パッドの領域下から外れて配置される配線の下部か、または、前記パッドの領域下から外れて配置される配線の下部を形成した後、前記第１のマスクとは異なる第２のマスクを用いて、前記パッドの領域下から外れて配置される配線の上部か、または、少なくとも一部が前記パッドの領域下に配置される配線、および前記パッドの領域下から外れて配置される配線の上部を形成することを特徴とする。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a wiring is formed in a layer below a surface layer on which pads for external connection are formed, using at least a part of the first mask. Forming a wiring arranged under the pad area and a lower part of the wiring arranged off the pad area, or a lower part of the wiring arranged out of the pad area; Using a second mask different from the first mask, the upper part of the wiring arranged out of the pad area or at least a part of the wiring arranged under the pad area, and An upper portion of the wiring arranged off the lower area of the pad is formed.

また、本発明の請求項６記載の半導体装置の製造方法は、外部接続用のパッドが形成される表層より一層下の層に配線を形成するに際し、第１のマスクを用いて、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線、および前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の下部か、または、前記パッドのプローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の下部を形成した後、前記第１のマスクとは異なる第２のマスクを用いて、前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の上部か、または、少なくとも一部が前記プローブ領域下あるいはワイヤボンド領域下に配置される配線、および前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の上部を形成することを特徴とする。   According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device using at least a part of a first mask when wiring is formed in a layer below a surface layer on which pads for external connection are formed. Is disposed below the probe region of the pad or the wire bond region, and below the wire disposed below the probe region or the wire bond region, or below the probe region of the pad or the wire bond. After forming the lower part of the wiring arranged off the area below, using the second mask different from the first mask, the upper part of the wiring arranged off the probe area or below the wire bond area Or at least a part of the wiring disposed under the probe region or the wire bond region, and the probe region or the wire. And forming an upper wiring which is arranged off the bottom Yabondo region.

本発明の好ましい実施の形態によれば、外部接続用のパッドが形成される表層より一層下の配線層の配線密度を下げることなく、パッド下の層間絶縁膜のクラックの発生を抑制でき、クラックによるパッドと配線のショートを抑制できる。さらに、表層より一層下の層の配線のうち、パッドの領域下、またはパッドのプローブ領域（プローブ針を接触させる領域）下あるいはワイヤボンド領域（ワイヤを接続する領域）下から外れて配置される配線については薄くせず、少なくとも一部がパッドの領域下、またはパッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線のみを薄くするので、配線抵抗の増加による半導体装置の特性の劣化を抑制でき、高信頼の半導体装置を得ることができる。   According to a preferred embodiment of the present invention, it is possible to suppress the occurrence of cracks in the interlayer insulating film under the pad without lowering the wiring density of the wiring layer below the surface layer on which the pad for external connection is formed. The short circuit between the pad and the wiring due to the Further, of the wirings in layers below the surface layer, the wiring is disposed below the pad area, below the pad probe area (the area where the probe needle contacts) or below the wire bond area (area where the wire is connected). Wiring is not thinned, and only the wiring that is at least partially under the pad area, or under the probe area of the pad or under the wire bond area is thinned. Thus, a highly reliable semiconductor device can be obtained.

以下に、本発明の半導体装置およびその製造方法の実施の形態について図面を用いて詳細に説明する。なお、本実施の形態では、多層配線構造の半導体装置について説明するが、本発明は、少なくとも、外部接続用のパッドが形成される表層と、その表層より一層下の配線層とを持つ半導体装置に適用することができる。   Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. Note that although a semiconductor device having a multilayer wiring structure is described in this embodiment, the present invention is a semiconductor device having at least a surface layer on which pads for external connection are formed and a wiring layer below the surface layer. Can be applied to.

本出願人は、表層に形成されている外部接続用のパッドに半導体装置の厚さ方向の応力を印加したときのパッド下の層間絶縁膜のクラック発生率が、表層より一層下の配線層に形成されたパッドの領域下を通過する配線（パッドの領域下に配置された配線）の厚さに依存していることを見出した。   The present applicant has found that the crack generation rate of the interlayer insulating film under the pad when the stress in the thickness direction of the semiconductor device is applied to the external connection pad formed in the surface layer is in the wiring layer lower than the surface layer. It has been found that this depends on the thickness of the wiring that passes under the formed pad region (wiring disposed under the pad region).

図１に、層間絶縁膜のクラックの発生率とパッドの領域下に配置される配線の厚さとの関係の一例を示す。このグラフは、ＡｌＳｉとＣｕの積層構造からなるパッドと、Ｃｕからなる配線と、ＳｉＯ２からなる層間絶縁膜を使用した場合の関係を示している。 FIG. 1 shows an example of the relationship between the occurrence rate of cracks in the interlayer insulating film and the thickness of the wiring disposed under the pad region. This graph shows the relationship when a pad made of a laminated structure of AlSi and Cu, a wiring made of Cu, and an interlayer insulating film made of SiO 2 are used.

なお、Ｃｕのヤング率は１３０ＧＰａ、ＳｉＯ２のヤング率は７１．３Ｇｐａであり、応力「σ」に対するひずみ「ε」はヤング率「Ｅ」を用いて『ε＝σ／Ｅ』となるので、半導体装置の厚さ方向の応力がパッドに印加されたとき、層間絶縁膜を構成するＳｉＯ２のひずみは、配線を構成するＣｕのひずみよりも大きくなる。 The Young's modulus of Cu is 130 GPa, the Young's modulus of SiO 2 is 71.3 Gpa, and the strain “ε” with respect to the stress “σ” becomes “ε = σ / E” using the Young's modulus “E”. When a stress in the thickness direction of the semiconductor device is applied to the pad, the strain of SiO2 constituting the interlayer insulating film becomes larger than the strain of Cu constituting the wiring.

図１に示すように、層間絶縁膜のクラックの発生率は配線の厚さに依存している。これは、同じ配線幅であれば、応力が印加される方向の厚さが厚いほど層間絶縁膜にかかるひずみ量が大きくなるためであると考えられる。   As shown in FIG. 1, the rate of occurrence of cracks in the interlayer insulating film depends on the thickness of the wiring. This is presumably because, for the same wiring width, the greater the thickness in the direction in which stress is applied, the greater the amount of strain applied to the interlayer insulating film.

図２は、本発明の実施の形態に係る半導体装置を説明するための断面図である。この半導体装置は多層配線構造であるが、簡単化するために、外部接続用のパッドが形成される表層とその一層下の配線層のみを図示する。   FIG. 2 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention. Although this semiconductor device has a multilayer wiring structure, for the sake of simplicity, only a surface layer on which pads for external connection are formed and a wiring layer below the surface layer are shown.

図２において、１は外部接続用のパッド、２はＳｉＯ２からなる層間絶縁膜、３ａ、３ｂはＣｕからなる配線、４は半導体基板である。表層に形成されているパッド１は、Ｃｕからなる下部１ｂと、ＡｌＳｉからなる上部１ａとを積層した構造をしている。また、配線３ａ、３ｂは表層より一層下の配線層に形成されており、配線３ａはその一部がパッド１の領域下に配置され、配線３ｂはパッド１の領域下から外れて配置されている。また、各層に形成された層間絶縁膜２は、各配線間、各配線と各パッドとの間、および各配線と半導体基板との間を電気的に絶縁している。 2, reference numeral 1 denotes a pad for external connection, 2 interlayer insulating film made of SiO 2, 3a, 3b is wiring made of Cu, 4 is a semiconductor substrate. The pad 1 formed on the surface layer has a structure in which a lower portion 1b made of Cu and an upper portion 1a made of AlSi are laminated. Further, the wirings 3a and 3b are formed in a wiring layer below the surface layer, and a part of the wiring 3a is disposed under the pad 1 region, and the wiring 3b is disposed outside the pad 1 region. Yes. In addition, the interlayer insulating film 2 formed in each layer electrically insulates the wirings, the wirings and the pads, and the wirings and the semiconductor substrate.

前述したように、表層より一層下の配線層の配線のうち、パッド１の領域下に配置される配線３ａの厚さが薄いほど、層間絶縁膜２のクラックの発生率が低い。そこで、本実施の形態では、図２に示すように、配線３ａの厚さを配線３ｂの厚さよりも薄くしている。このようにすれば、表層より一層下の配線層の配線密度を下げることなく、プローブ検査時やワイヤボンド時の応力による層間絶縁膜２のクラックの発生を抑制することができ、クラックによるパッドと配線のショートを抑制することができる。また、パッド１の領域下から外れて配置されている配線３ｂについては、薄くしないので、配線抵抗が増加することはない。   As described above, the crack generation rate of the interlayer insulating film 2 is lower as the thickness of the wiring 3a disposed below the pad 1 region in the wiring layers below the surface layer is smaller. Therefore, in this embodiment, as shown in FIG. 2, the thickness of the wiring 3a is made thinner than the thickness of the wiring 3b. In this way, it is possible to suppress the occurrence of cracks in the interlayer insulating film 2 due to stress during probe inspection or wire bonding without lowering the wiring density of the wiring layer below the surface layer. Short circuit of wiring can be suppressed. Further, since the wiring 3b arranged out of the area of the pad 1 is not thinned, the wiring resistance does not increase.

図３は、本発明の実施の形態に係る半導体装置の他例を説明するための断面図である。図３において、３ｃ、３ｄはＣｕからなる配線である。配線３ｃ、３ｄは表層より一層下の配線層に形成されており、配線３ｃはその一部がパッド１のプローブ領域下あるいはワイヤボンド領域下に配置され、配線３ｄはパッド１のプローブ領域下あるいはワイヤボンド領域下から外れて配置されている。   FIG. 3 is a cross-sectional view for explaining another example of the semiconductor device according to the embodiment of the present invention. In FIG. 3, 3c and 3d are wirings made of Cu. The wirings 3c and 3d are formed in a wiring layer below the surface layer, and a part of the wiring 3c is disposed under the probe region of the pad 1 or under the wire bond region, and the wiring 3d is under the probe region of the pad 1 or It is arranged off the wire bond area.

図３に示すように、厚さを薄くする配線を、プローブ検査時やワイヤボンド時に応力が印加される領域下に配置される配線に限定することにより、パッド下の層間絶縁膜のクラックの発生を抑制しつつ、配線抵抗の増加による半導体装置の特性の劣化をより抑制でき、より高信頼の半導体装置を得ることができる。   As shown in FIG. 3, the generation of cracks in the interlayer insulating film under the pad is limited by limiting the wiring to be thinned to a wiring disposed under a region where stress is applied during probe inspection or wire bonding. In addition, the deterioration of the characteristics of the semiconductor device due to the increase in wiring resistance can be further suppressed, and a more reliable semiconductor device can be obtained.

図４（ａ）〜（ｄ）は、図２に示す半導体装置の製造方法を説明するための工程断面図である。なお、ここでは、外部接続用のパッドと、そのパッドが形成される表層より一層下の配線層の配線を形成する工程についてのみ説明して、本工程の前後の工程については特に限定しない。   4A to 4D are process cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. Here, only the step of forming the external connection pad and the wiring of the wiring layer below the surface layer where the pad is formed will be described, and the steps before and after this step are not particularly limited.

まず、図４（ａ）に示すように、ＳｉＯ２からなる層間絶縁膜を堆積した後、パッドの領域下にはパターンが存在しない第１のマスク（図示せず）を用いて、層間絶縁膜をパターンニングし、メッキ法にてＣｕからなる配線３ｂの下部を形成する。なお、ここでは、配線抵抗を低くするために、パッドの領域下から外れて配置される配線３ｂの厚さを１５００ｎｍとし、パッド下の層間絶縁膜のクラックを防止するために、パッドの領域下に配置される配線３ａの厚さを４５０ｎｍとするので、配線３ｂの下部の厚さは１０５０ｎｍとする。 First, as shown in FIG. 4A, after depositing an interlayer insulating film made of SiO 2 , an interlayer insulating film is formed using a first mask (not shown) having no pattern under the pad region. Then, the lower part of the wiring 3b made of Cu is formed by plating. Here, in order to reduce the wiring resistance, the thickness of the wiring 3b arranged off the pad region is set to 1500 nm, and the interlayer insulating film under the pad is prevented from cracking under the pad region. Since the thickness of the wiring 3a arranged at 450 is 450 nm, the thickness of the lower portion of the wiring 3b is 1050 nm.

次に、図４（ｂ）に示すように、ＳｉＯ２からなる層間絶縁膜を堆積した後、パッドの領域下にもパターンが存在する第２のマスク（図示せず）を用いて、層間絶縁膜をパターンニングし、メッキ法にて、Ｃｕからなる配線３ｂの上部および配線３ａを形成する。配線３ｂの上部と配線３ａの厚さは４５０ｎｍとする。 Next, as shown in FIG. 4B, after an interlayer insulating film made of SiO 2 is deposited, an interlayer insulating film is used by using a second mask (not shown) in which a pattern also exists under the pad region. The film is patterned, and the upper part of the wiring 3b made of Cu and the wiring 3a are formed by plating. The upper part of the wiring 3b and the thickness of the wiring 3a are 450 nm.

次に、図４（ｃ）に示すように、ＳｉＯ２からなる層間絶縁膜を堆積した後、パッドの下部となる部分をパターニングし、メッキ法にてＣｕからなるパッドの下部１ｂを形成する。 Next, as shown in FIG. 4C, after depositing an interlayer insulating film made of SiO 2 , the lower portion of the pad is patterned and a lower portion 1b of the pad made of Cu is formed by plating.

次に、図４（ｄ）に示すように、ＳｉＯ２からなる層間絶縁膜を堆積した後、パッドの下部１ｂと接続するための開口部を形成し、ＡｌＳｉを堆積してパターニングし、パッドの上部１ａを形成して、積層構造からなるパッド１を形成する。 Next, as shown in FIG. 4D, after an interlayer insulating film made of SiO 2 is deposited, an opening for connecting to the lower portion 1b of the pad is formed, AlSi is deposited and patterned, and the pad The upper part 1a is formed, and the pad 1 having a laminated structure is formed.

なお、本実施の形態では、ＡｌＳｉとＣｕの積層構造からなるパッドと、ＳｉＯ２からなる層間絶縁膜と、Ｃｕからなる配線を用いた場合について説明したが、他の材料や多層の材料を用いてもよい。 In this embodiment, the case where a pad made of a laminated structure of AlSi and Cu, an interlayer insulating film made of SiO 2 , and a wiring made of Cu is used, but other materials or multilayer materials are used. May be.

また、パッドの配置については、特に限定されるものではなく、基板全面あるいは基板の周辺に配置してもよい。さらに、パッドの形状についても限定されるものではない。   Further, the arrangement of the pads is not particularly limited, and the pads may be arranged on the entire surface of the substrate or around the substrate. Further, the shape of the pad is not limited.

また、本実施の形態では、先にパッドの領域下から外れて配置される配線３ｂの下部を形成した後、配線３ｂの上部、およびパッドの領域下に配置される配線３ａを形成する場合について説明したが、順序を入れ替えて、先にパッドの領域下に配置される配線３ａ、およびパッドの領域下から外れて配置される配線３ｂの下部を形成した後、配線３ｂの上部を形成してもよい。このようにすれば、パッドと配線間の距離が長くなるので、クラックの発生をさらに防ぐことができる。   Further, in the present embodiment, the lower part of the wiring 3b arranged off the pad area is formed first, and then the wiring 3a arranged on the upper part of the wiring 3b and under the pad area is formed. As described above, the order is changed, and after forming the lower part of the wiring 3a arranged below the pad area and the wiring 3b arranged off the lower pad area, the upper part of the wiring 3b is formed. Also good. In this way, since the distance between the pad and the wiring is increased, the occurrence of cracks can be further prevented.

また、図２に示す半導体装置の製造方法について説明したが、図３に示す半導体装置についても、同様の方法で製造することができる。   Further, although the manufacturing method of the semiconductor device shown in FIG. 2 has been described, the semiconductor device shown in FIG. 3 can also be manufactured by a similar method.

本発明にかかる半導体装置およびその製造方法は、パッド下の層間絶縁膜のクラックの発生を抑制でき、多層配線構造の半導体装置に有用である。   INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention can suppress the occurrence of cracks in the interlayer insulating film under the pad and are useful for a semiconductor device having a multilayer wiring structure.

層間絶縁膜のクラックの発生率とパッドの領域下に配置される配線の厚さとの関係の一例を示す図The figure which shows an example of the relationship between the incidence rate of the crack of an interlayer insulation film, and the thickness of the wiring arrange | positioned under the area | region of a pad 本発明の実施の形態に係る半導体装置を説明するための断面図Sectional drawing for demonstrating the semiconductor device which concerns on embodiment of this invention 本発明の実施の形態に係る半導体装置の他例を説明するための断面図Sectional drawing for demonstrating the other example of the semiconductor device which concerns on embodiment of this invention 本発明の実施の形態に係る半導体装置の製造方法を説明するための工程断面図Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention 従来の半導体装置の平面図Plan view of a conventional semiconductor device

符号の説明Explanation of symbols

１ パッド
１ａ パッドの上部
１ｂ パッドの下部
２ 層間絶縁膜
３ａ〜３ｄ 配線
４ 半導体基板
１１ パッド
１２ 配線 DESCRIPTION OF SYMBOLS 1 Pad 1a Upper part of pad 1b Lower part of pad 2 Interlayer insulating film 3a-3d wiring 4 Semiconductor substrate 11 Pad 12 wiring

Claims (6)

表層に形成された外部接続用のパッドと、前記表層より一層下の層に形成された配線と、前記表層およびその一層下の層に形成された層間絶縁膜と、半導体基板とを少なくとも備えた半導体装置であって、前記表層より一層下の層に形成された配線のうち、少なくとも一部が前記パッドの領域下に配置される配線は、その厚さが、前記パッドの領域下から外れて配置される配線の厚さよりも薄いことを特徴とする半導体装置。   At least a pad for external connection formed on the surface layer, wiring formed on a layer below the surface layer, an interlayer insulating film formed on the surface layer and a layer below the surface layer, and a semiconductor substrate In the semiconductor device, among the wirings formed in a layer lower than the surface layer, a wiring in which at least a part is disposed under the pad region has a thickness that deviates from below the pad region. A semiconductor device characterized in that it is thinner than the thickness of wiring to be arranged. 表層に形成された外部接続用のパッドと、前記表層より一層下の層に形成された配線と、前記表層およびその一層下の層に形成された層間絶縁膜と、半導体基板とを少なくとも備えた半導体装置であって、前記表層より一層下の層に形成された配線のうち、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線は、その厚さが、前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の厚さよりも薄いことを特徴とする半導体装置。   At least a pad for external connection formed on the surface layer, wiring formed on a layer below the surface layer, an interlayer insulating film formed on the surface layer and a layer below the surface layer, and a semiconductor substrate Among the wirings formed in a layer below the surface layer of the semiconductor device, the wirings at least part of which are arranged under the probe region or the wire bond region of the pad have a thickness that is A semiconductor device characterized in that it is thinner than a thickness of a wiring arranged under the region or under the wire bond region. 前記層間絶縁膜のヤング率は、少なくとも一部が前記パッドの領域下に配置される配線のヤング率よりも小さいことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a Young's modulus of the interlayer insulating film is smaller than a Young's modulus of a wiring that is at least partially disposed under the pad region. 前記層間絶縁膜のヤング率は、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線のヤング率よりも小さいことを特徴とする請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein a Young's modulus of the interlayer insulating film is smaller than a Young's modulus of wiring disposed at least partially under the probe region or the wire bond region of the pad. 外部接続用のパッドが形成される表層より一層下の層に配線を形成するに際し、
第１のマスクを用いて、少なくとも一部が前記パッドの領域下に配置される配線、および前記パッドの領域下から外れて配置される配線の下部か、または、前記パッドの領域下から外れて配置される配線の下部を形成した後、
前記第１のマスクとは異なる第２のマスクを用いて、前記パッドの領域下から外れて配置される配線の上部か、または、少なくとも一部が前記パッドの領域下に配置される配線、および前記パッドの領域下から外れて配置される配線の上部を形成する
ことを特徴とする半導体装置の製造方法。 When forming the wiring in a layer below the surface layer where the pad for external connection is formed,
Using the first mask, at least a part of the wiring arranged below the pad area and the lower part of the wiring arranged off the pad area, or off the pad area After forming the lower part of the wiring to be placed,
Using a second mask different from the first mask, the upper part of the wiring arranged out of the pad area or at least a part of the wiring arranged under the pad area, and A method of manufacturing a semiconductor device, comprising: forming an upper portion of a wiring that is arranged out of a region below the pad. 外部接続用のパッドが形成される表層より一層下の層に配線を形成するに際し、
第１のマスクを用いて、少なくとも一部が前記パッドのプローブ領域下あるいはワイヤボンド領域下に配置される配線、および前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の下部か、または、前記パッドのプローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の下部を形成した後、
前記第１のマスクとは異なる第２のマスクを用いて、前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の上部か、または、少なくとも一部が前記プローブ領域下あるいはワイヤボンド領域下に配置される配線、および前記プローブ領域下あるいはワイヤボンド領域下から外れて配置される配線の上部を形成する
ことを特徴とする半導体装置の製造方法。 When forming the wiring in a layer below the surface layer where the pad for external connection is formed,
Using the first mask, at least a portion of the wiring disposed below the probe region or the wire bond region of the pad and the lower portion of the wiring disposed below the probe region or the wire bond region; Or, after forming the lower portion of the wiring that is disposed under the probe region or wire bond region of the pad,
Using a second mask different from the first mask, the upper part of the wiring disposed below the probe region or the wire bond region, or at least a part thereof is below the probe region or the wire bond region. A method for manufacturing a semiconductor device, comprising: forming a wiring disposed below and an upper portion of the wiring disposed below the probe region or the wire bonding region.
JP2007298747A 2007-11-19 2007-11-19 Semiconductor apparatus and method of manufacturing the same Pending JP2009124057A (en)

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